JP2717835B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP2717835B2
JP2717835B2 JP1040177A JP4017789A JP2717835B2 JP 2717835 B2 JP2717835 B2 JP 2717835B2 JP 1040177 A JP1040177 A JP 1040177A JP 4017789 A JP4017789 A JP 4017789A JP 2717835 B2 JP2717835 B2 JP 2717835B2
Authority
JP
Japan
Prior art keywords
film
resist film
bump electrode
plating
conductive material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1040177A
Other languages
Japanese (ja)
Other versions
JPH02220440A (en
Inventor
愛一郎 梅月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1040177A priority Critical patent/JP2717835B2/en
Publication of JPH02220440A publication Critical patent/JPH02220440A/en
Application granted granted Critical
Publication of JP2717835B2 publication Critical patent/JP2717835B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔概要〕 半導体装置の製造方法、特に半導体チップとパッケー
ジを接続するためのバンプ電極の形成方法に関し、 コスト低減及びスループットを向上でき、高信頼性の
あるバンプ電極の形成方法を提供することを目的とし、 基板にバンプ電極を形成する半導体装置の製造方法に
おいて、前記基板の電極形成部を除く領域に所定パター
ンの第1のレジスト膜を形成し、第1のレジスト膜上に
それよりも厚く、かつ、それの端部を超える広がりの第
2のレジスト膜を形成する工程と、前記第2のレジスト
膜をマスクとして電極形成部に第1の導電材からなるバ
ンプ電極を形成する工程と、前記第2のレジスト膜を剥
離する工程と、前記第1のレジスト膜をマスクとしてバ
ンプ電極の周囲に、かつ、第1のレジスト膜の端部ま
で、前記第1の導電材より耐腐食性のある第2の導電材
からなる金属膜をメッキする工程と、前記第1のレジス
ト膜を剥離する工程とを含むことを特徴とする半導体装
置の製造方法を含み構成する。
DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a bump electrode for connecting a semiconductor chip to a package. In a method of manufacturing a semiconductor device in which a bump electrode is formed on a substrate, a first resist film having a predetermined pattern is formed in a region excluding an electrode forming portion of the substrate, and a first resist film is formed. Forming a second resist film thicker and wider than the end thereof, and forming a bump electrode made of a first conductive material on an electrode forming portion using the second resist film as a mask; Forming the second resist film, removing the second resist film, and using the first resist film as a mask, around a bump electrode, and at an end of the first resist film. A step of plating a metal film made of a second conductive material that is more resistant to corrosion than the first conductive material, and a step of removing the first resist film. Including and including the manufacturing method.

〔産業上の利用分野〕[Industrial applications]

本発明は、半導体装置の製造方法、特に半導体チップ
とパッケージを接続するためのバンプ電極の形成方法に
関する。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a bump electrode for connecting a semiconductor chip to a package.

〔従来の技術〕[Conventional technology]

近年、半導体集積回路(IC)の高集積化、高信頼性、
コスト低減などの要求に伴い、各種メッキ技術が要求さ
れている。
In recent years, high integration, high reliability of semiconductor integrated circuits (IC),
With the demand for cost reduction and the like, various plating techniques are required.

例えば、高集積化のために箱型のストレートバンプ電
極の形成が必要であり、高信頼性のためには耐腐食性の
あるメッキ膜が要求され、コスト低減には安いメッキ膜
が要請されている。
For example, it is necessary to form a box-shaped straight bump electrode for high integration, a corrosion-resistant plating film is required for high reliability, and a cheap plating film is required for cost reduction. I have.

従来、半導体基板に選択的にメッキするためにはレジ
ストパターンをマスクとしているが、レジストが薄いと
横方向にもメッキがつき、メッキがマッシュルーム形状
になるために、高集積化には厚膜レジストが用いられて
いる。また、高信頼性のためにメッキには耐腐食性のあ
る金(Au)メッキが用いられている。
Conventionally, a resist pattern is used as a mask to selectively plate a semiconductor substrate.However, if the resist is thin, plating is applied in the horizontal direction, and the plating becomes a mushroom shape. Is used. Further, gold (Au) plating having corrosion resistance is used for plating for high reliability.

ところが、Auメッキを使用するためにコストがかか
り、またAuメッキは高速でメッキできず時間がかかり過
ぎるという欠点があった。
However, the use of Au plating is costly, and Au plating has the drawback that it cannot be plated at high speed and takes too much time.

また、銅(Cu)メッキを使用すると、コスト低減とス
ループットの向上になるが、Cuは耐腐食性が悪いため、
高信頼性が得られないといった問題があった。
The use of copper (Cu) plating reduces costs and improves throughput, but because Cu has poor corrosion resistance,
There was a problem that high reliability could not be obtained.

そこで、第3図(a)及び(b)に示すように、基板
1の電極部形成領域を除く領域に厚膜レジスト2を形成
し、この厚膜レジスト2をマスクとして、Cuのバンプ電
極3をメッキ形成し、その後にAuメッキによりバンプ電
極3上にAu膜4を形成し(同図(a))、次に、厚膜レ
ジスト2を剥離し(同図(b))した場合には、バンプ
電極3の側壁がAuメッキされずに腐食されてしまう。
Therefore, as shown in FIGS. 3 (a) and 3 (b), a thick film resist 2 is formed in a region other than the electrode portion forming region of the substrate 1, and using the thick film resist 2 as a mask, the Cu bump electrode 3 is formed. In the case where an Au film 4 is formed on the bump electrode 3 by Au plating (FIG. 2A), and then the thick film resist 2 is peeled off (FIG. 2B). Then, the side wall of the bump electrode 3 is not Au-plated and is corroded.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

すなわち、高信頼性のバンプ電極を形成するためにAu
を使用した場合には、コスト低減とスループットの向上
ができず、また、Cuを使用した場合には、高信頼性に問
題があった。
That is, in order to form a highly reliable bump electrode, Au
When Cu was used, cost reduction and throughput could not be improved, and when Cu was used, there was a problem in high reliability.

そこで本発明は、コスト低減及びスループットを向上
でき、高信頼性のあるバンプ電極の形成方法を提供する
ことを目的とする。
Therefore, an object of the present invention is to provide a highly reliable method for forming a bump electrode which can reduce cost and improve throughput.

〔課題を解決するための手段〕[Means for solving the problem]

上記課題は、基板にバンプ電極を形成する半導体装置
の製造方法において、前記基板の電極形成部を除く領域
に所定パターンの第1のレジスト膜を形成し、第1のレ
ジスト膜上にそれよりも厚く、かつ、それの端部を超え
る広がりの第2のレジスト膜を形成する工程と、前記第
2のレジスト膜をマスクとして電極形成部に第1の導電
材からなるバンプ電極を形成する工程と、前記第2のレ
ジスト膜を剥離する工程と、前記第1のレジスト膜をマ
スクとしてバンプ電極の周囲に、かつ、第1のレジスト
膜の端部まで、前記第1の導電材より耐腐食性のある第
2の導電材からなる金属膜をメッキする工程と、前記第
1のレジスト膜を剥離する工程とを含むことを特徴とす
る半導体装置の製造方法らよって解決される。
The object is to provide a method of manufacturing a semiconductor device in which a bump electrode is formed on a substrate, wherein a first resist film having a predetermined pattern is formed in a region excluding an electrode forming portion of the substrate, and a first resist film is formed on the first resist film. A step of forming a second resist film that is thick and extends beyond the end thereof; and a step of forming a bump electrode made of a first conductive material in an electrode forming portion using the second resist film as a mask. Stripping the second resist film, and using the first resist film as a mask, around the bump electrode and up to the end of the first resist film, more corrosion resistant than the first conductive material. A method for manufacturing a semiconductor device, comprising: a step of plating a metal film made of a second conductive material having a certain property; and a step of removing the first resist film.

〔作用〕[Action]

第1図(a)〜(c)は本発明の原理説明図である。 1 (a) to 1 (c) are diagrams for explaining the principle of the present invention.

まず、同図(a)に示すように、基板11の電極形成部
を除く領域に第1のレジスト膜12を形成し、かつこの第
1のレジスト膜12上に第2のレジスト膜13を第1のレジ
スト膜12よりも十分に厚く形成してから、第2のレジス
ト膜13をマスクとして電極形成部に第1の導電材からな
るバンプ電極14を形成する。
First, as shown in FIG. 1A, a first resist film 12 is formed in a region excluding an electrode forming portion of a substrate 11, and a second resist film 13 is formed on the first resist film 12 in a second step. After the first resist film 12 is formed sufficiently thicker than the first resist film 12, a bump electrode 14 made of a first conductive material is formed on the electrode forming portion using the second resist film 13 as a mask.

次に、同図(b)に示すように、第2のレジスト膜13
を剥離した後、第1のレジスト膜12をマスクとしてバン
プ電極14の周囲に、第1の導電材のバンプ電極14より耐
腐食性のある第2の導電材からなる金属膜15をメッキす
る。
Next, as shown in FIG.
Then, a metal film 15 made of a second conductive material, which is more resistant to corrosion than the bump electrode 14 of the first conductive material, is plated around the bump electrode 14 using the first resist film 12 as a mask.

次に、同図(c)に示すように、第1のレジスト膜12
を剥離する。
Next, as shown in FIG.
Is peeled off.

以上の工程により周囲に耐腐食性のある金属膜15をメ
ッキしたバンプ電極14が形成される。
Through the above steps, the bump electrode 14 is formed around which the metal film 15 having corrosion resistance is plated.

すなわち本発明によれば、基板11の電極形成部にメッ
キ速度の速いCuなどの第1の導電材からなるバンプ電極
14を形成し、このバンプ電極14の周囲に、耐腐食性のあ
るAuなどの第2の導電材からなる金属膜15をメッキする
ことで、バンプ電極の耐腐食性の面では問題がなく、ま
た、コスト及びスループットも向上する。
That is, according to the present invention, the bump electrode made of the first conductive material such as Cu having a high plating rate is formed on the electrode forming portion of the substrate 11.
By forming a metal film 15 made of a second conductive material such as Au having corrosion resistance around the bump electrode 14, there is no problem in terms of the corrosion resistance of the bump electrode. Also, cost and throughput are improved.

〔実施例〕〔Example〕

以下、本発明を図示の一実施例により具体的に説明す
る。
Hereinafter, the present invention will be described in detail with reference to an embodiment shown in the drawings.

第2図(a)〜(d)は本発明実施例のバンプ電極の
製造工程断面図である。
2 (a) to 2 (d) are cross-sectional views showing a manufacturing process of the bump electrode according to the embodiment of the present invention.

まず、同図(a)に示すように、ウエハ基板21には、
アルミニュウム(Al)配線22が形成され、カバー膜とし
て、1.0μm程度の膜厚のPSG膜23、0.3μm程度の膜厚
のSiN膜24、2.0μm程度の膜厚のP.I膜25が順次形成さ
れ、電極部として開口部26が形成される。
First, as shown in FIG.
An aluminum (Al) wiring 22 is formed, and a PSG film 23 having a thickness of about 1.0 μm, a SiN film 24 having a thickness of about 0.3 μm, and a PI film 25 having a thickness of about 2.0 μm are sequentially formed as a cover film. Then, an opening 26 is formed as an electrode portion.

次に、同図(b)に示すように、全面にバリアメタル
として、チタン(Ti)膜27を5000Å、続いてパラジウム
(Pd)膜28を3000Åそれぞれスパッター法により形成
し、その上に膜厚が1〜2μm程度の第1のレジスト膜
(例えば、富士ハント株式会社製のノボラック系レジス
トであるHPR204)29をパターニングし、その上に膜厚が
30μm程度の第2のレジスト膜(例えば、東京応化株式
会社製のアクリル系レジストであるBMR-SF1000)30を塗
布しパターニングする。このとき、第1のレジスト膜29
の開口部の方が第2のレジスト膜30の開口部よりやや大
きく形成する。その後、第2のレジスト膜30をマスクと
してCuメッキを行い、電極形成部の開口部内に25μm程
度の高さのバンプ電極31を箱形に形成する。
Next, as shown in FIG. 4B, a titanium (Ti) film 27 is formed as a barrier metal on the entire surface by 5000 ° and a palladium (Pd) film 28 is formed by 3000 ° on the entire surface by sputtering. Is patterned with a first resist film 29 having a thickness of about 1 to 2 μm (for example, HPR204 which is a novolak-based resist manufactured by Fuji Hunt Co., Ltd.)
A second resist film (for example, BMR-SF1000 which is an acrylic resist manufactured by Tokyo Ohka Co., Ltd.) 30 of about 30 μm is applied and patterned. At this time, the first resist film 29
The opening is formed slightly larger than the opening of the second resist film 30. Thereafter, Cu plating is performed using the second resist film 30 as a mask, and a bump electrode 31 having a height of about 25 μm is formed in a box shape in the opening of the electrode forming portion.

次に、同図(c)に示すように、第2のレジスト膜30
をアクリル系レジスト専用のウエット剥離液でウェット
剥離(例えば、東京応化株式会社製のBMR剥離液)を行
い、その後、第1のレジスト膜29をマスクとしてAuメッ
キを行いバンプ電極31の表面に膜厚が約2.0μm程度のA
u膜32を形成する。
Next, as shown in FIG.
Is subjected to wet stripping (for example, a BMR stripping solution manufactured by Tokyo Ohka Co., Ltd.) using a wet stripping solution dedicated to an acrylic resist, and then Au plating is performed using the first resist film 29 as a mask to form a film on the surface of the bump electrode 31. A about 2.0μm thick
The u film 32 is formed.

次に、同図(d)に示すように、第1のレジスト膜29
をアッシングによるドライ剥離またはウェット剥離(例
えば、東京応化株式会社製の502剥離液)によって除去
する。その後、Au膜32をマスクとして、バリアメタルで
あるPd膜28、Ti膜27を王水と過酸化水素アンモニアによ
りエッチングする。
Next, as shown in FIG.
Is removed by dry stripping or wet stripping by ashing (for example, 502 stripper manufactured by Tokyo Ohka Co., Ltd.). Thereafter, using the Au film 32 as a mask, the Pd film 28 and the Ti film 27, which are barrier metals, are etched with aqua regia and ammonia hydrogen peroxide.

上記方法によれば、基板21の電極形成部にメッキ速度
の速いCuなどの導電材からなるバンプ電極31が形成さ
れ、このバンプ電極31のすべての周囲に、耐腐食性のあ
るAu膜32をメッキすることで、バンプ電極31の耐腐食性
の面では問題がなくなった。また、この実施例では、Au
メッキ液がCuメッキ液よりも5倍程度の価格であるため
コストが1/5になり、スループットはAuメッキが1μm/4
分、Cuメッキが1μm/1.5分で2〜3倍に向上した。
According to the above method, a bump electrode 31 made of a conductive material such as Cu having a high plating rate is formed on the electrode forming portion of the substrate 21, and a corrosion-resistant Au film 32 is formed around the entire bump electrode 31. The plating eliminated the problem in terms of the corrosion resistance of the bump electrode 31. Further, in this embodiment, Au
Since the plating solution is about 5 times as expensive as the Cu plating solution, the cost is 1/5 and the throughput is 1μm / 4 for Au plating.
Min, Cu plating improved 2-3 times at 1 μm / 1.5 min.

なお、上記実施例では、Cuのバンプ電極31の周囲にAu
膜32を形成しているが、メッキ速度の速い第1の導電材
の周囲にそれより耐腐食性のある第2の導電材からなる
金属膜を形成すればよい。
In the above embodiment, the Au around the bump electrode 31 made of Cu is used.
Although the film 32 is formed, a metal film made of a second conductive material having higher corrosion resistance may be formed around the first conductive material having a high plating rate.

また、本発明の方法で形成したバンプ電極は、リード
フレームの配線に接合するTAB法、フリップチップボン
ディングによるCCB法などにそれぞれ適用することがで
きる。
Further, the bump electrode formed by the method of the present invention can be applied to a TAB method for bonding to a lead frame wiring, a CCB method by flip chip bonding, or the like.

〔発明の効果〕〔The invention's effect〕

以上説明した様に本発明によれば、電極形成部に形成
した第1の導電材からなるバンプ電極の周囲に、耐腐食
性のある第2の導電材からなる金属膜をメッキすること
で、バンプ電極の耐腐食性が向上し、また、コスト及び
スループットも向上する効果がある。
As described above, according to the present invention, a metal film made of a corrosion-resistant second conductive material is plated around a bump electrode made of a first conductive material formed on an electrode forming portion, There is an effect that the corrosion resistance of the bump electrode is improved, and the cost and the throughput are also improved.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(c)は本発明の原理説明図、 第2図(a)〜(d)は本発明実施例のバンプ電極の製
造工程断面図、 第3図(a)及び(b)は従来のバンプ電極の製造工程
断面図である。 図中、 11は基板、12は第1のレジスト膜、13は第2のレジスト
膜、14はバンプ電極、15は金属膜、21はウエハ基板、22
はAl配線、23はPSG膜、24はSiN膜、25はP.I膜、26は開
口部、27はTi膜、28はPd膜、29は第1のレジスト膜、30
は第2のレジスト膜、31はバンプ電極、32はAu膜 を示す。
FIGS. 1 (a) to 1 (c) are explanatory diagrams of the principle of the present invention, FIGS. 2 (a) to 2 (d) are cross-sectional views of a bump electrode manufacturing process according to an embodiment of the present invention, FIGS. FIG. 2B is a cross-sectional view illustrating a manufacturing process of a conventional bump electrode. In the figure, 11 is a substrate, 12 is a first resist film, 13 is a second resist film, 14 is a bump electrode, 15 is a metal film, 21 is a wafer substrate, 22
Is an Al wiring, 23 is a PSG film, 24 is a SiN film, 25 is a PI film, 26 is an opening, 27 is a Ti film, 28 is a Pd film, 29 is a first resist film, 30
Denotes a second resist film, 31 denotes a bump electrode, and 32 denotes an Au film.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】基板(11)にバンプ電極(14)を形成する
半導体装置の製造方法において、 前記基板(11)の電極形成部を除く領域に所定パターン
の第1のレジスト膜(12)を形成し、第1のレジスト膜
(12)上にそれよりも厚く、かつ、それの端部を超える
広がりの第2のレジスト膜(13)を形成する工程と、 前記第2のレジスト膜(13)をマスクとして電極形成部
に第1の導電材からなるバンプ電極(14)を形成する工
程と、 前記第2のレジスト膜(13)を剥離する工程と、 前記第1のレジスト膜(12)をマスクとしてバンプ電極
(14)の周囲に、かつ、第1のレジスト膜(12)の端部
まで、前記第1の導電材より耐腐食性のある第2の導電
材からなる金属膜(15)をメッキする工程と、 前記第1のレジスト膜(12)を剥離する工程とを含むこ
とを特徴とする半導体装置の製造方法。
1. A method of manufacturing a semiconductor device, wherein a bump electrode is formed on a substrate, wherein a first resist film having a predetermined pattern is formed in a region excluding an electrode forming portion of the substrate. Forming a second resist film (13) thicker than the first resist film (12) and extending beyond the end thereof on the first resist film (12); A) forming a bump electrode (14) made of a first conductive material on an electrode forming portion using the mask as a mask; (b) stripping the second resist film (13); Is used as a mask, around the bump electrode (14) and up to the end of the first resist film (12), a metal film (15) made of a second conductive material that is more resistant to corrosion than the first conductive material. ) And a step of stripping the first resist film (12). The method of manufacturing a semiconductor device according to claim.
JP1040177A 1989-02-22 1989-02-22 Method for manufacturing semiconductor device Expired - Lifetime JP2717835B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1040177A JP2717835B2 (en) 1989-02-22 1989-02-22 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1040177A JP2717835B2 (en) 1989-02-22 1989-02-22 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH02220440A JPH02220440A (en) 1990-09-03
JP2717835B2 true JP2717835B2 (en) 1998-02-25

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JP (1) JP2717835B2 (en)

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JP2004273591A (en) * 2003-03-06 2004-09-30 Seiko Epson Corp Semiconductor device and its fabricating process
US7468545B2 (en) * 2005-05-06 2008-12-23 Megica Corporation Post passivation structure for a semiconductor device and packaging process for same
JP2011035249A (en) * 2009-08-04 2011-02-17 Fujitsu Ltd Method of manufacturing semiconductor device

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