JP3521383B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor element (semiconductor chip).
The present invention relates to a technique useful for preventing peeling of a sealing resin in a semiconductor device having a structure in which a sealing resin is sealed, for example, a semiconductor device having a chip size package (CSP) structure.

In the following description, the term "semiconductor chip" refers to individual semiconductor elements after being cut and separated from the wafer, unless it is defined otherwise. The individual semiconductor elements in a state before being cut and separated are also referred to.

[0003]

2. Description of the Related Art In recent years, with the demand for miniaturization of electronic equipment and devices, miniaturization and high density of semiconductor devices used therein have been attempted. Therefore, a semiconductor device having a CSP structure has been developed and manufactured in which the shape of the semiconductor device is made as close as possible to the shape of each semiconductor element (semiconductor chip) to achieve miniaturization.

In a typical semiconductor device having a CSP structure, an insulating film made of polyimide or the like is formed on a wafer in which a large number of semiconductor elements (semiconductor chips) are formed, and the insulating film is formed on the insulating film. A rewiring layer is formed to connect the wiring layer (electrode pad) of each semiconductor chip to the outside of the package through a via hole formed in a required area of the rewiring layer. Is provided with via posts corresponding to the pins of the package, and the entire wafer is sealed with the sealing resin (however, the tops of the via posts are exposed).

In such a semiconductor device having a CSP structure, since sealing is performed in the state of a wafer in which a large number of semiconductor chips are formed, the interface between the wafer and a layer of sealing resin that seals the wafer is on the wafer. Microscopically, the insulating film in which the via holes are formed and the portion in which the rewiring layer is formed on the insulating film are somewhat uneven, but as a whole, It has a structure in which it is bonded almost flatly.

A thermosetting resin is typically used as a resin for sealing the wafer (each semiconductor chip). This thermosetting resin generally has a coefficient of thermal expansion different from that of the semiconductor chip.

[0007]

As described above, in the conventional semiconductor device having the CSP structure, the semiconductor chip formed on the wafer and the resin (thermosetting resin) for sealing the same have different coefficients of thermal expansion. Due to the temperature cycle, a considerable amount of shear stress due to the difference in thermal expansion acts on the interface between the two. Therefore, if a considerably large shear stress exceeding the degree of adhesion between the semiconductor chip and the sealing resin occurs, the sealing resin may be peeled off from the semiconductor chip.

The encapsulating resin should be provided for encapsulating and protecting the semiconductor chip, but if it is peeled off from the semiconductor chip, the final semiconductor device cannot be realized. . That is, peeling of the sealing resin leads to a reduction in reliability as a final semiconductor device, which is not preferable. Such a problem is not peculiar to a semiconductor device having a CSP structure, but is generally a semiconductor device having a structure in which a semiconductor chip is sealed with a sealing resin, and the thermal expansion of the semiconductor chip and the sealing resin is If the coefficients are different, this is a normal occurrence.

The present invention was created in view of the above problems in the prior art, and can prevent the sealing resin for sealing the semiconductor chip from peeling off, and thus contribute to the improvement of the reliability as a product. An object of the present invention is to provide a semiconductor device that can be manufactured and a method of manufacturing the same.

[0010]

In order to solve the above-mentioned problems of the prior art, according to one embodiment of the present invention, an electrode pad
In a semiconductor device having a sealed structure with a sealing resin a semiconductor chip but formed, on the semiconductor chip surface in the insulating film is formed of the side surface in contact with the sealing resin of the insulating film, the electrode An opening is formed to expose the pad
In addition, a recess or opening is formed at a specific position, and the recess or opening has a score along its periphery.
A semiconductor device having a formed shape is provided.

According to another aspect of the present invention, the surface of the semiconductor chip on which the electrode pad is formed has an opening through which the electrode pad is exposed and at a specific position.
A step of forming an insulating film so as to have a recess or an opening having a notch formed along the periphery thereof , and the electrode except for the recess or the opening formed at the specific position on the insulating film. And a step of forming a conductor layer so as to cover only the opening where the pad is exposed, and a step of sealing the semiconductor chip with a sealing resin, except for a region corresponding to the terminal forming portion of the conductor layer. A method for manufacturing a semiconductor device is provided.

According to still another aspect of the present invention, the step of forming an insulating film on the surface of the semiconductor chip on which the electrode pad is formed so as to have an opening through which the electrode pad is exposed; Forming a conductor layer on the film so as to cover the opening where the electrode pad is exposed; and forming a notch along the periphery of the insulating film portion exposed from the conductor layer.
A semiconductor including a step of forming a recess or an opening in which the semiconductor chip is formed and a step of sealing the semiconductor chip with a sealing resin except for a region corresponding to a terminal forming portion of the conductor layer. A method of manufacturing a device is provided.

According to the semiconductor device and the manufacturing method thereof according to the present invention, the insulating film formed on the surface of the semiconductor chip is
Since the recess or opening is formed on the surface that contacts the sealing resin, a part of the sealing resin has entered this recess or opening, and this part is called the "anchor" of the sealing resin. Constitute. In other words, as in the prior art, the interface between the semiconductor chip and the encapsulating resin is not planarly bonded, but the "anchor" of the encapsulating resin partially enters the insulating film on the semiconductor chip. It has a structure.

Therefore, even if a considerably large shear stress is generated at the interface due to the difference in thermal expansion coefficient between the semiconductor chip and the sealing resin, the shear stress is the "anchor" of the sealing resin.
Since it is reduced or absorbed by, it is possible to eliminate the disadvantage that the sealing resin is peeled off from the semiconductor chip as in the conventional case. This contributes to the improvement of reliability as a product.

Further, in addition to the concave portion or the opening portion, a convex portion may be formed on the surface of the insulating film. In this case,
Since the interface between the semiconductor chip and the sealing resin becomes uneven, the uneven stress more effectively reduces or absorbs the shear stress. As a result, the effect of preventing peeling of the sealing resin can be more reliably exhibited.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device having a CSP structure according to a first embodiment of the present invention will be described below with reference to FIGS. In the first step (see FIG. 1A), a wafer 1 having a plurality of semiconductor chips (not shown) formed therein by a known method.
Create 0. That is, silicon nitride (Si
N) or phosphorous glass (PSG) or the like after forming a passivation film 11 as a protective film, a large number of aluminum (A
The passivation film 11 corresponding to the region of the electrode pad 12 of l) is removed. As a result, the surface is covered with the passivation film 11 as shown, and the electrode pad 1
A wafer 10 having exposed 2 is manufactured.

In some cases, the semiconductor chip may not be provided with the passivation film 11, and a polyimide layer formed in a later step may also function as a passivation film. In the next step (see FIG. 1B), the insulating film 13 is first formed on the surface of the wafer 10 by photolithography.
A photosensitive polyimide is applied as a photosensitive resist for forming a resist, then a soft bake (prebake) of the resist is performed, and exposure and development (resist patterning) are performed using a mask (not shown). A hard bake (post bake) process is performed to form an insulating film (polyimide layer) 13 partially having openings P, Q1 and Q2 as shown in the figure.

The resist patterning is carried out by using the electrode pad 1
2 and the opening Q to be formed at a specific position of the polyimide layer 13 where a rewiring layer described later is not formed.
1 and Q2 are performed. Therefore, when exposure and development are performed, as shown in the figure, the resist (polyimide layer 13) in the portion corresponding to the electrode pad 12 and the resist (polyimide layer 13) at the specific position are removed to reach the electrode pad 12. Via holes (openings P) and dummy via holes (openings Q1 and Q2) reaching the upper end of the passivation film 11 are formed.

In the illustrated example, two openings Q are formed as openings to be formed at specific positions of the polyimide layer 13.
Although 1 and Q2 are shown, it goes without saying that the number of such openings is not limited to two. In the next step (see FIG. 1C), the metal thin film 14 is formed on the entire surface by sputtering. The metal thin film 14 has a two-layer structure of a chromium (Cr) layer forming an adhesion metal layer and a copper (Cu) layer laminated thereon. The metal thin film 14 is formed by depositing Cr on the entire surface by sputtering to form an adhesive metal layer (Cr layer) in the lower layer portion, and further depositing Cu on it by sputtering to form the Cu in the upper layer portion.
This is done by forming layers. Here, the Cu layer in the upper layer portion is formed with a thickness of several Å.

The metal thin film 14 thus formed
Functions as a power supply layer or a plating base film for the electrolytic plating process required in the subsequent wiring forming step and via / post forming step. In the next step (see FIG. 2A), for example, a dry film is formed as the photosensitive resist 15 on the metal thin film 14, and exposure and development (resist patterning) are performed using a mask (not shown). I do. This patterning is performed so as to follow the shape of the wiring pattern formed in the next step.

In the next step (see FIG. 2 (b)), electrolytic plating is performed by feeding power from the feeding layer (metal thin film 14),
Using the patterned resist 15 as a mask, a Cu wiring pattern, that is, a wiring layer 16 is formed with a thickness of about several tens of μm. The wiring layer 16 is also called a "rewiring layer". In the next step (see FIG. 2 (c)), a weakly alkaline chemical solution (for example, an aqueous solution of sodium hydroxide (NaOH))
Dry film or resist 15 (see FIG. 2).
(See (b)) is peeled off and removed.

In the next step (see FIG. 3A), a dry film, for example, is formed as a photosensitive resist 17 on the metal thin film 14 and the wiring layer 16, and is exposed by using a mask (not shown). And development (resist patterning)
I do. This patterning is performed so as to conform to the shape of the via post formed in the next step. In the next step (see FIG. 3B), Cu via posts 18 are similarly formed by electrolytic plating by feeding power from the feeding layer (metal thin film 14) using the patterned resist 17 as a mask. Furthermore, if desired, a barrier metal layer may be formed by electrolytic plating on the top of the via post 18.

In the next step (see FIG. 3C), a dry film, that is, a resist 17 is formed by using a weak alkaline chemical solution (for example, an aqueous solution of sodium hydroxide (NaOH)).
(See FIG. 3B) is peeled off and removed. In the next step (see FIG. 4A), the exposed plating base film (metal thin film 14) is removed by etching. That is, the Cu layer in the upper layer portion of the metal thin film 14 is removed with an etching solution that dissolves Cu, and then the adhesion metal layer (Cr layer) in the lower layer portion is removed with an etching solution that dissolves Cr. This exposes the polyimide layer 13 having the openings Q1 and Q2 as shown.

When an etching solution that dissolves Cu is used, Cu that constitutes the wiring layer 16 is also removed and the wiring pattern appears to be broken, but this does not actually occur. This is because, as described above, the upper layer portion of the plating base film 14 is formed by Cu sputtering, so that the film thickness is several Å, whereas the wiring layer 16 is formed by Cu electrolytic plating. Therefore, since the film thickness thereof is about several tens of μm, even if Cu of the plating base film 14 is completely removed, Cu of the wiring layer 16 is such that only its surface layer portion is removed. This is because the pattern never breaks.

In the next step (see FIG. 4B), the via
Wafer 10 in which polyimide layer 13 as an insulating film is formed between wiring layer 16 with post 18 (rewiring layer) 16
Is sealed with a sealing resin. This is, for example, in Japanese Patent Laid-Open No.
It can be carried out as follows using a well-known method as disclosed in Japanese Patent Publication No. 79362 or the like. First, a sealing mold, which is divided into an upper mold and a lower mold, is prepared and heated to a predetermined temperature. Next, the resin film is adsorbed to the upper mold, the wafer 10 is mounted in the concave portion of the lower mold, and a thermosetting resin having a high adhesive force is placed thereon as a sealing resin. And
The thermosetting resin is melted by the heat of the sealing die and the pressure of the press and spread over the entire surface of the wafer, and the thermosetting resin is cured while being held in the die. After that, the wafer 10 is removed from the mold. At this time, since the wafer 10 is integrated with the resin film, the resin film is peeled off from the wafer 10. As a result, the surface of the sealing resin layer 1 is as shown in the figure.
A wafer 10 covered with 9 and exposed on top of via posts 18 is made.

In the final step (see FIG. 4C), the solder balls 20 as external connection terminals are arranged on the tops of the exposed via posts 18 and reflow is performed to remove the solder balls 20 from the via posts 18. Fix on top. After that, the wafer 10 is cut together with the sealing resin layer 19 by a dicer or the like to separate into individual semiconductor elements (that is, semiconductor chips).

As described above, according to the configuration of the semiconductor device having the CSP structure according to the first embodiment, FIG.
As shown in FIG. 3, since the openings Q1 and Q2 are formed on the surface of the polyimide layer 13 formed on the semiconductor chip (wafer 10) on the side in contact with the sealing resin layer 19, the sealing resin A part thereof enters the openings Q1 and Q2, and this part constitutes an anchor of the sealing resin layer 19.

Therefore, even if a considerably large shear stress is generated at the interface due to the difference in thermal expansion coefficient between the semiconductor chip (wafer 10) and the sealing resin layer 19, the shear stress is the anchor of the sealing resin layer 19. Since it is effectively reduced or absorbed by, the inconvenience that the sealing resin is peeled off from the semiconductor chip can be eliminated. This leads to improvement in reliability as a product.

FIG. 5 shows a part of the manufacturing process of the semiconductor device according to the second embodiment of the present invention. The semiconductor device of this embodiment is basically shown in FIGS.
5 (a) to FIG. 5 after the same process as the process of FIG. 4 (a) (the process of removing the exposed plating base film 14) is performed. It is manufactured by going through the process shown in (c).

That is, in the step shown in FIG. 5A, the sealing resin layer 19a is transfer-molded or potted so as to cover the polyimide layer 13 having the openings Q1 and Q2 and the rewiring layer 16 formed thereon. Formed by
Next, in a step shown in FIG. 5B, a via hole VH is formed by laser processing in a region of the sealing resin layer 19a corresponding to a terminal forming portion of the rewiring layer 16, and further, FIG.
In the step shown in (c), the solder balls 20a as external connection terminals are arranged in the via holes VH, and reflow is performed to fix the solder balls 20a on the rewiring layer 16.

According to the present embodiment, in addition to the effects obtained in the first embodiment described above, at least the steps of FIGS. 3A to 3C are different from those in the case of the first embodiment. Since the number of steps is reduced accordingly, there is an advantage that the process can be simplified. FIG. 6 shows a part of the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

The semiconductor device of this embodiment is basically the same as the steps shown in FIGS. 1A to 2C, and is further processed in the step shown in FIG. 6) after a process similar to that of removing the plating base film 14 present).
It is manufactured by going through the steps shown in (a) and FIG. 6 (b). That is, in the step shown in FIG. 6A, a wire of gold (Au) is formed on the terminal forming portion of the rewiring layer 16 formed on the polyimide layer 13 having the openings Q1 and Q2 by using the wire bonding technique. An S-shaped external connection terminal is bonded with 20b, and a nickel (Ni) alloy is further adhered to the surface of the wire 20b by electrolytic plating.
In the step shown in (b), the sealing resin layer 19b is formed by potting so as to cover the polyimide layer 13 and the rewiring layer 16.

According to the present embodiment, in addition to the effects and advantages obtained in the second embodiment described above, the presence of the S-shaped wire 20b having the Ni alloy deposited on the surface thereof causes some problems. Benefits are obtained. First, since the wire 20b can be made to have an elastic force by the Ni alloy deposited on the surface, the stress when this device is mounted on a printed circuit board or the like can be relaxed and the connection reliability can be improved. Further, the impedance can be optimized depending on the length and shape of the wire 20b, and the electrical characteristics can be improved. Furthermore, since heat dissipation is improved, heat sinks can be reduced.

In each of the above-described embodiments, the polyimide layer 13 on the semiconductor chip (wafer 10) has the openings Q1 and Q2 reaching the passivation film 11 therebelow (see FIG. 1B). Of course, the form of the opening is not limited to this. For example, you may form the opening part (namely, recessed part) which stops the termination | terminus in the middle of the polyimide layer 13.

In short, the surface of the polyimide layer 13 forming the insulating film formed on the semiconductor chip (wafer 10) is
It is sufficient that the semiconductor chip (wafer 10) and the sealing resin layer 19 have an uneven shape effective for reducing or absorbing the shear stress generated at the interface due to the difference in thermal expansion coefficient between the semiconductor resin and the sealing resin layer 19. Therefore, the shape of the surface of the polyimide layer 13 is not limited to the concave portion or the opening portion, and may be, for example, a convex portion. Such a convex portion can be formed by performing processing such as exposure and development used in the step of FIG. 1B, for example.
Can be formed. In this case, after forming a concave portion or an opening portion on the surface of the polyimide layer 13, a convex portion may be additionally formed on the surface of the polyimide layer 13, or a concave portion or an opening portion may be formed on the surface of the polyimide layer 13. Instead of forming the opening, a protrusion may be formed on the surface of the polyimide layer 13. In the former case, the interface between the polyimide layer 13 on the semiconductor chip (wafer 10) and the encapsulating resin layer 19 becomes uneven, and thus the uneven stress more effectively reduces or absorbs the shear stress. .

Further, it goes without saying that the sizes and shapes of the recesses and the openings can be arbitrarily selected. For example, as shown in FIG. 7 as a plan view of the concave portion , as shown in FIG. 7, (a) a circular concave portion Q3, (b) a rectangular concave portion Q4, and (c) a polygonal shape made up of a set of rectangles. The concave portion Q5 may be the concave portion Q5, or (d) the concave portion Q6 may be a concave portion having a notch formed around the circle. In particular, as shown in (d), when the shape of the peripheral edge of the recess Q6 becomes more complicated, the adhesiveness with the sealing resin can be improved, so that the shear stress can be reduced or absorbed more effectively. It will be possible. In addition, in the example of FIG.
Notches are formed along the periphery of the "shaped" recess Q6.
However, the shape of the notched peripheral edge is the "circle" shown in the figure.
In addition, "rectangle" as shown in Fig. 7 (b) and (c)
Of course, it may be a “polygon” or the like .

Further, in each of the above-described embodiments, the wafer 10 is used.
Although the openings Q1 and Q2 are formed in the polyimide layer 13 in the step of forming the polyimide layer 13 on top (step of FIG. 1B), such openings (or concave portions, convex portions, etc.) are
It may be formed at another stage as long as the polyimide layer 13 is exposed. For example, in the first embodiment, since the polyimide layer 13 is exposed at the stage where the exposed plating base film (metal thin film) 14 is removed (step of FIG. 4A),
At this stage, openings and the like can be formed. In this case, the openings and the like can be formed even if the processes such as the exposure and development used in the step of FIG. 1B are performed, but for this purpose, photolithography is necessary, and the process is complicated. However, the polyimide layer 1 is formed by laser processing.
It is easier in the process to partially roughen the surface of No. 3 and form the uneven portion. As a laser, an excimer laser,
A YAG laser, a CO ₂ laser or the like can be used.

Further, in each of the above-mentioned embodiments, the recesses and the openings are formed by photolithography or laser processing, but it goes without saying that the means for forming the recesses is not limited to this. For example, it is also possible to form the recesses and the like by machining. As an example, a jig provided with a protruding cutting tool can be used. In such a jig, the protruding portion of the cutting tool is pressed against the surface of the polyimide layer 13 and scratched to form a groove-shaped recess Q7.
(See FIG. 8A) can be formed, and a triangular pyramidal recess Q8 (see FIG. 8B) can be formed by piercing the protruding portion of the cutting tool on the surface of the polyimide layer 13. it can. The groove-shaped recess Q7 can also be formed by photolithography.

Further, in each of the embodiments described above, the wafer 1
Although the case where the photosensitive polyimide is used as the insulating film 13 formed on the surface of 0 has been described, the material of the insulating film is not limited to the photosensitive resin, for example, non-photosensitive polyimide or the like. You may use the resin of. However, in this case, since photolithography cannot be used, necessary openings and the like are formed by laser processing, for example.

[0040]

As described above, according to the present invention, the resin layer for sealing the semiconductor chip is configured to have the anchor effect, so that the semiconductor chip and the sealing resin layer having different thermal expansion coefficients are different from each other. Even if a large shear stress is generated at the interface, the encapsulating resin does not peel off, and the product has high reliability.
It is possible to obtain a semiconductor device having a P structure or the like.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing process (1) of a semiconductor device having a CSP structure according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process (2) following the manufacturing process of FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process (3) following the manufacturing process of FIG. 2;

FIG. 4 is a cross-sectional view showing a manufacturing process (4) following the manufacturing process in FIG. 3;

FIG. 5 is a cross-sectional view showing a part of the manufacturing process for the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a part of a manufacturing process for a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a diagram showing an example of the shape of a recess formed on the surface of a polyimide layer.

FIG. 8 is a diagram showing an example of forming a recess or the like by machining.

[Explanation of symbols]

10 ... Wafer 11 ... passivation film 12 ... Electrode pad 13 ... Polyimide layer (insulating film) 14 ... Metal thin film (power supply layer, plating base film) 16 ... Wiring layer (rewiring layer) 18 ... Beer Post 19, 19a, 19b ... Encapsulating resin layer 20, 20a ... Solder balls (external connection terminals) 20b ... Wire (external connection terminal) P: Opening (via hole) Q1, Q2 ... Openings (dummy via holes) Q3, Q4, Q5, Q6, Q7, Q8 ... Recesses

Claims (3)

(57) [Claims] 1. A semiconductor device having a structure in which a semiconductor chip on which an electrode pad is formed is sealed with a sealing resin, wherein an insulating film is formed on the surface of the semiconductor chip and is in contact with the sealing resin of the insulating film. On the side surface, the electrode pad
With openings exposing is formed, is formed <br/> recess or opening in a particular position, recess or opening, the
A semiconductor device having a shape in which a notch is formed along a peripheral edge . 2. An opening for exposing the electrode pad is formed on the surface of the semiconductor chip on which the electrode pad is formed .
The notch is formed along the periphery at a specific position.
A step of forming an insulating film so as to have a recess or an opening formed on the insulating film, except for the opening where the electrode pad is exposed, except for the recess or the opening formed at the specific position. Manufacturing of a semiconductor device comprising: a step of forming a conductor layer so as to cover; and a step of sealing the semiconductor chip with a sealing resin, except for a region corresponding to a terminal forming portion of the conductor layer. Method. 3. A step of forming an insulating film on a surface of a semiconductor chip on which the electrode pad is formed so as to have an opening for exposing the electrode pad, and an opening for exposing the electrode pad on the insulating film. A step of forming a conductor layer so as to cover the portion, and the insulating film portion exposed from the conductor layer along the periphery thereof.
Characterized in that it includes a step of forming a concave portion or an opening portion in which a notch is formed, and a step of sealing the semiconductor chip with a sealing resin except for a region corresponding to a terminal formation portion of the conductor layer. Of manufacturing a semiconductor device.