JPH04312924A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To remove residue of Cr-etching by using a sulfuric acidic dichromate- based etchant as an etching solution for buffer layer made of copper and a ferrycyanide-based etchant as an etching solution for barrier metal layer made of chrome. CONSTITUTION:An aluminum pad 2 is formed on an integrated circuit substrate 1, a passivation film 3 is coated by plasma CVD method, and a hole portion 5 is formed in a predetermined region on the pad 2. Then, Cr and Cu are continuously deposited by sputtering method on the passivation film and the hole portion 5, and a barrier metal layer 6 and buffer layer 7 are formed. Then, a solder bump 8 having a size large enough to close fully the hole portion 5 is formed on the buffer layer 7 by plating method. By doing this, the occurrence of etching residue of Cr film can be prevented, and a bump electrode having a wide solder composition can be produced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming solder bumps.

[Summary of the invention]

The present invention relates to a semiconductor device manufacturing method in which a buffer layer and a barrier metal layer are collectively etched in a self-aligned manner using solder bumps formed on an integrated circuit as a mask. An acidic dichromic acid etchant and a ferricyanide etchant are used as an etching solution for a barrier metal layer made of chromium.

[Conventional technology]

In the solder bump electrode, Cr is deposited on the Al pad as a diffusion barrier metal. This Cr film is made of Al
, plays the role of not only preventing the diffusion of Cu but also increasing adhesion strength and reducing contact resistance.

However, Cr is easier to passivate and more difficult to etch than solder or Cu. In a normal manufacturing process, a photolithography process is performed to etch the Cr film, and then solder bumps are formed. However, it has been found that by using a ferrician-based Cr etchant, it is possible to etch the barrier metal layer using the solder bump as a mask, and the continuous deposition of the barrier metal layer and buffer layer and the photolithography process can be omitted once. The manufacturing process can be greatly simplified.

[Problem to be solved by the invention]

However, the composition of the solder surface is Sn compared to the eutectic composition.
When rich bumps are formed, there is a problem in that etched Cr remains as shown in FIG. 2 in the vicinity of the solder bumps.

[Means to solve the problem]

In order to solve the above problems, a sulfuric acid acidic dichromate-based etchant is used as an etching solution for a buffer layer made of Cu.

[Effect]

In the conventional process, a sulfuric acid-hydrogen peroxide solution was used as an etchant to selectively etch Cu without corroding solder or Cr. After lightly bombarding the etched surface of the Cr film generated in this case with Ar, Auger electron spectroscopy was performed, and Sn or Sn oxide was detected on the remaining surface of the Cr film. The results of various verification experiments revealed that this Sn was deposited on the Cr film exposed during Cu etching. Especially Sn
Because the tetravalent oxide does not react with ordinary chemicals at all,
It is thought that these act as a mask and Cr remains.

By the way, in order to prevent the precipitation of Sn or Sn oxides, it is important to suppress the elution of Sn. Therefore, C
By using dichromic acid, which has a lower electrode potential in an aqueous solution than hydrogen peroxide, as an oxidizing agent in the etching solution, Cr
Residue can be prevented.

〔Example〕

Hereinafter, an embodiment of the manufacturing method of the present invention will be described with reference to FIG.

An aluminum pad 2 was formed on an integrated circuit substrate 1 and covered with a passivation film 3 made of phosphosilicate glass (PSG) or silicon nitride by plasma CVD. Pad 2 is etched using normal photolithography technology and plasma etching method.
When the opening 5 is formed in the upper predetermined area, the structure shown in FIG. 2(A) is obtained.

Subsequently, 15,000 Å of Cr and 5,000 Å of Cr were successively deposited on the passivation film and the opening 5 by sputtering to form a barrier metal layer 6 and a buffer layer 7. Note that the Cr and Cu films can be deposited by physical vapor deposition or chemical vapor deposition other than the sputtering method. Next, solder bumps 8 having a size that completely covers the openings 5 are formed on the buffer layer 7 by plating, as shown in the same figure (B).
The structure is shown in . Incidentally, as a method for forming solder bumps, in addition to the plating method, a vapor deposition method using a metal mask is also used. If so, the formation method is not limited.

Next, the buffer layer 7 was etched with a potassium dichromate solution adjusted to be acidic with sulfuric acid. The composition of the etchant is H2SO4 (conc.)...20-30%K2Cr2 in weight%.
O7...Use an aqueous solution of 15 to 20% (or CrO3 of the same amount of Cr), and in a large excess of new solution at 25℃, approximately 10%
Buffer layer 7 was completely removed in 0 seconds.

After washing with water, the barrier metal layer 6 was etched with an alkaline potassium ferricyanide aqueous solution having the following composition.

K3 [Fe(CN)6]...500g KOH...250g H2O...3000g Completely etched in about 120 seconds in a large excess of new solution at 25°C.

Table 1 shows the evaluation of the effect of preventing Cr etching residue by the manufacturing method of the present invention. As a conventional example, Cu with the following composition
This is compared to when using etchant. (Immersion time 60 seconds) H2SO4 (conc.)...25mlH2O2 (30
%aq. )...340 ml H2O...635 ml All etching was performed at 25°C under the same conditions with a large excess of etchant.

Note) Shown as weight ratio. The composition was estimated by differential thermal analysis.

〔Effect of the invention〕

The present invention makes it possible to prevent etching residues on the Cr film even in the production of bump electrodes with Sn-rich solder compositions, making it possible to produce bump electrodes with a wider range of solder compositions than ever before.

[Brief explanation of drawings]

FIGS. 1(a), (b), and (b) are cross-sectional views showing the method of manufacturing a solder bump electrode according to the present invention, and FIG. 2 is a cross-sectional view showing the etching residue of the Cr film generated in the conventional example. It is a diagram. 1...Integrated circuit board 2...Pad 3...Passivation film 5...Opening part 6...Barrier metal layer 7...Buffer layer 8...Solder bump 9...More than etching remaining Applicant Seiko Electronic Industries Co., Ltd. Agent Patent attorney Keinosuke Hayashi

Claims (1)

[Claims] A method for manufacturing a solder bump electrode formed on an integrated circuit board, comprising: forming an opening in a passivation film on a pad existing on the integrated circuit board; Barrier metal layer mainly composed of chromium in the hole,
A process of sequentially depositing a buffer layer containing copper as a main component and forming a solder bump large enough to cover the opening on the buffer layer; A method for manufacturing a semiconductor device, comprising the following steps: etching away the barrier metal layer using a ferrician etchant using a solder bump as a mask.