JPH04116831A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04116831A
JPH04116831A JP23768490A JP23768490A JPH04116831A JP H04116831 A JPH04116831 A JP H04116831A JP 23768490 A JP23768490 A JP 23768490A JP 23768490 A JP23768490 A JP 23768490A JP H04116831 A JPH04116831 A JP H04116831A
Authority
JP
Japan
Prior art keywords
opening part
solder
resist
buffer layer
barrier metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23768490A
Other languages
Japanese (ja)
Inventor
Jun Tsuneyoshi
潤 恒吉
Kenichi Ogawa
健一 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP23768490A priority Critical patent/JPH04116831A/en
Publication of JPH04116831A publication Critical patent/JPH04116831A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask

Landscapes

  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent attachments from being formed by a method wherein after a solder bump is formed, an annealing treatment is performed and thereafter, a buffer layer and a barrier metal layer are removed in such a way as to perform an etching. CONSTITUTION:A pad 2 consisting of Al is formed on an integrated circuit board 1 and thereafter, the pad 2 is covered with a passivation film 3 consisting of silicon nitride by a plasma CVD method and an opening part 4 is formed. Then, a barrier metal film 5 consisting of Cr is deposited on the film 3 and the opening part 4 by sputtering, subsequently, a buffer layer 6 consisting of Cu is deposited. Then, a resist having a heat resistance to the melting point or higher of solder is applied, a resist opening part 7 of a size enough to cover the opening part 4 is formed on the pad 2 and a solder bump 8 is formed by a plating method which is selected in the opening part. Subsequently, an annealing treatment is performed in an oven in an inert gas atmosphere. Then, the resist is peeled and after that, the layers 6 and 5 are respectively removed with an etchant using a solder bump 8' as a mask. Thereby, the generation of attachments at the time of a reflow can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に係わるもので、特に、
はんだバンプ方式の半導体装置の製造方法に関するもの
である。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular,
The present invention relates to a method of manufacturing a solder bump type semiconductor device.

〔発明の概要〕[Summary of the invention]

本発明は集積回路上に形成されたはんだバンプをマスク
として、バッファ層およびバリアメタル層を自己整合的
にエツチング除去する半導体装置の製造方法において、
エツチング中にはんだが受けるダメージを軽減させるこ
とを目的としてエツチング工程の前にはんだのアニール
工程を追加したものである。
The present invention provides a method for manufacturing a semiconductor device in which a buffer layer and a barrier metal layer are etched away in a self-aligned manner using solder bumps formed on an integrated circuit as a mask.
A solder annealing process is added before the etching process in order to reduce damage to the solder during etching.

〔従来の技術〕[Conventional technology]

従来より貴金属を主成分としたバンプに関しては、バン
プをマスクとした自己整合的なエツチングも行われてい
る0通常バリアメタルとして用いられるCrは不働態化
し易く、腐食性の強いエンチャントが使用されているた
め、Auなどの貴金属を主成分とするバンプでは自己整
合的なエツチングが可能であったが、耐食性に劣るはん
だバンプでは前述の製造方法に関して詳述している報告
は少ない、開示例としては特開平2−71272号公報
が挙げられる程度である。
Conventionally, for bumps made mainly of noble metals, self-aligned etching using the bumps as a mask has also been carried out. Cr, which is normally used as a barrier metal, is easily passivated and highly corrosive enchantments are used. Therefore, self-aligned etching was possible for bumps mainly composed of noble metals such as Au, but there are few reports detailing the above manufacturing method for solder bumps with poor corrosion resistance. JP-A-2-71272 can be mentioned.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

フェリシアン系のエッチャントを使用することで、はん
だバンプにダメージを与えずにCrを主成分としたバリ
アメタル層のエツチングが可能である。しかし、Sn 
−Pb系ないし5n−Pb−Bi系のはんだで比較的S
nを多く含有する組成のバンプにおいて、実装時に無色
透明〜茶褐色の付着物が若干発生するという1llll
を有していた。
By using a ferrician-based etchant, it is possible to etch the barrier metal layer mainly composed of Cr without damaging the solder bumps. However, Sn
- Relatively S with Pb-based or 5n-Pb-Bi-based solder
In bumps with a composition containing a large amount of n, some colorless and transparent to brownish deposits are generated during mounting.
It had

AES分析およびFPMA分析の結果より、この付着物
はSnの酸化物ないし水酸化物とフラフクスの混合物で
あることが判明した。
The results of AES analysis and FPMA analysis revealed that this deposit was a mixture of Sn oxide or hydroxide and flux.

〔課題を解決するための手段〕[Means to solve the problem]

上記の課題を解決するために、はんだバンプを形成後、
アニール処理を施してからバッファ層およびバリアメタ
ル層のエツチングを行うようにした。
In order to solve the above problems, after forming solder bumps,
After annealing, the buffer layer and barrier metal layer are etched.

〔作用〕[Effect]

はんだバンプは一般的にめっき法ないし蒸着法により形
成される。従ってバンプ表面は凹凸が激しく比表面積が
大きい上に、Sn、 Pbが合金化していないために腐
食され易い、ところがエツチング工程の前にアニール処
理することでSo、 Pb粒子の凝集・緻密化さらに合
金化の効果によりSnの溶出が抑制され、前述の付着物
の生成が防止される。
Solder bumps are generally formed by plating or vapor deposition. Therefore, the bump surface is highly uneven, has a large specific surface area, and is easily corroded because Sn and Pb are not alloyed.However, by annealing before the etching process, the So and Pb particles agglomerate and become densified, and the alloy is Due to the effect of oxidation, the elution of Sn is suppressed, and the formation of the above-mentioned deposits is prevented.

〔実施例〕〔Example〕

本発明によるはんだバンプ形成の実施例を第1図fa)
〜+dlの断面図に示した。
An example of solder bump formation according to the present invention is shown in FIG.
It is shown in the cross-sectional view of ~+dl.

集積回路基板1上にMからなるバンド2を形成後、プラ
ズマCVD法により窒化珪素からなるパンシベーション
膜3で被覆し、フォトリソ工程とドライエツチング法に
より開孔部4を形成すると同図ta+の構造となる。
After forming a band 2 made of M on an integrated circuit substrate 1, it is coated with a pansivation film 3 made of silicon nitride by a plasma CVD method, and an opening 4 is formed by a photolithography process and a dry etching method, resulting in the structure shown in the figure ta+. becomes.

次に、パンシベーシヲン膜3および開孔部4上にCrか
らなるバリアメタル層5をスパッタリングにより約15
00人析出し、続いてCuからなるバッファ層6を同じ
くスパッタリングにより約5ooo人析出した。はんだ
の融点以上の耐熱性を有するレジスト (実施例ではポ
リイミド系のものを使用)をスピンコータを使用して厚
さ数10JQIにコーティングし、フォトリソ工程によ
りバッド2上かつ開孔部4を覆う大きさのレジスト開孔
部7を形成し、その開孔部に選択されるめっき法により
はんだバンプ8を形成すると同図(b)の構造となる。
Next, a barrier metal layer 5 made of Cr is deposited on the pansibasion film 3 and the opening 4 by sputtering for a thickness of approximately 15 cm.
Then, a buffer layer 6 made of Cu was similarly deposited by sputtering in a thickness of about 500 mm. A resist having a heat resistance higher than the melting point of the solder (polyimide is used in the example) is coated using a spin coater to a thickness of several 10 JQI, and a size that covers the pad 2 and the opening 4 is formed using a photolithography process. When resist openings 7 are formed, and solder bumps 8 are formed in the openings by a selected plating method, the structure shown in FIG. 3(b) is obtained.

続いて、本発明の特徴とする不活性ガス雰囲気のオープ
ン中(約250℃)で30分間アニール処理を施すこと
によりはんだは軟化・溶融し、同図(C1に示したよう
な形状になる。
Subsequently, the solder is softened and melted by performing an annealing treatment for 30 minutes in an open inert gas atmosphere (approximately 250° C.), which is a feature of the present invention, and the solder becomes shaped as shown in the same figure (C1).

次に、レジスト剥離し、その後にはんだバンプ8゛をマ
スクとしてCuからなるバッファ層6を以下の組成のエ
ッチャントを使用して除去した。
Next, the resist was stripped off, and then, using the solder bumps 8' as a mask, the buffer layer 6 made of Cu was removed using an etchant having the following composition.

H□SO4・・・・・・・ 25− HtOx (30%水溶液)・・・34〇−HtOx・
・・・・・・・635− 次に、Crからなるバリアメタル層5を以下の組成のエ
ッチャントを使用して除去した。
H□SO4・・・・・・25-HtOx (30% aqueous solution)・・・34〇-HtOx・
635- Next, the barrier metal layer 5 made of Cr was removed using an etchant having the following composition.

Ks [F e (CN)&]  ・・500 gKO
H・・・・・・・・ 250g H1O・・・・・・・・・2500g 以上の製造方法により形成されたはんだバンプの構造を
同図Tdlに示した。
Ks [F e (CN) &]...500 gKO
H...250g H1O...2500g The structure of the solder bump formed by the above manufacturing method is shown in Tdl in the same figure.

本発明の製造方法によって共晶点付近のはんだ組成にお
いてもリフロー時に付着物が生成しなくなった0通常の
はんだバンプではSnウィスカーの発生を防止するため
、共晶点よりSnクリンチ組成のものは使用されないた
め、必要にして十分な組成領域のはんだバンプの製造が
可能である。
Due to the manufacturing method of the present invention, deposits are no longer generated during reflow even with solder compositions near the eutectic point.In order to prevent the formation of Sn whiskers in normal solder bumps, those with a Sn clinch composition below the eutectic point are used. Therefore, it is possible to manufacture solder bumps with a necessary and sufficient composition range.

〔発明の効果〕〔Effect of the invention〕

本発明により、Snの含有量が多いはんだ組成において
もリフロー時の付着物発生が防止され、外観不良品が減
少した。また、はんだバンプの表面がつや消し状態にな
るので外観検査時の目の疲労を軽減する等の効果がある
According to the present invention, the generation of deposits during reflow is prevented even in solder compositions with a high content of Sn, and the number of products with poor appearance is reduced. Furthermore, since the surface of the solder bump becomes matte, it has the effect of reducing eye fatigue during appearance inspection.

【図面の簡単な説明】[Brief explanation of drawings]

第1図+a+、 (b)、 (C1,(dlは本発明に
よるはんだバンプの製造方法を断面図で示したものであ
る。 1・・・集積回路基板 ・パッド ・バ7シベーション膜 ・開孔部 ・バリアメタル層 ・バッファ層 ・レジスト開孔部 ・はんだバンプ ・アニール後のはんだバンプ 以上 出願人 セイコー電子工業株式会社 代理人 弁理士 林  敬 之 肋 木発明の製造工種E示オ断面図 第1図
Figure 1 +a+, (b), (C1, (dl) is a cross-sectional view showing the method of manufacturing a solder bump according to the present invention. 1...Integrated circuit board, pad, busivation film, opening Holes, barrier metal layers, buffer layers, resist openings, solder bumps, solder bumps after annealing, etc. Applicant: Seiko Electronics Industries Co., Ltd. Agent Patent attorney: Takayuki Hayashi Cross-sectional diagram showing the manufacturing type E of the crossbar invention No. 1 figure

Claims (1)

【特許請求の範囲】  集積回路基板上に形成されるバンプ電極の製造方法に
おいて、 集積回路基板上に存在するパッド上のパッシベーション
膜に開孔部を形成する工程と、 該パッシベーション膜上および開孔部にバリアメタル層
およびバッファ層を順次積層し、耐熱性のレジストを用
いてバッファ層上に開孔部を覆う大きさのはんだバンプ
を形成する工程と、 該はんだバンプを合金化した後にレジスト剥離を行い、
バンプをマスクとしてバッファ層、バリアメタル層をエ
ッチング除去する工程と、 を含むことを特徴とする半導体装置の製造方法。
[Claims] A method for manufacturing a bump electrode formed on an integrated circuit board, comprising: forming an opening in a passivation film on a pad existing on the integrated circuit board; A process of sequentially stacking a barrier metal layer and a buffer layer on the buffer layer, forming a solder bump large enough to cover the opening on the buffer layer using a heat-resistant resist, and removing the resist after alloying the solder bump. and
A method for manufacturing a semiconductor device, comprising: etching away a buffer layer and a barrier metal layer using a bump as a mask.
JP23768490A 1990-09-06 1990-09-06 Manufacture of semiconductor device Pending JPH04116831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23768490A JPH04116831A (en) 1990-09-06 1990-09-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23768490A JPH04116831A (en) 1990-09-06 1990-09-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04116831A true JPH04116831A (en) 1992-04-17

Family

ID=17018977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23768490A Pending JPH04116831A (en) 1990-09-06 1990-09-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04116831A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165382A (en) * 2004-12-09 2006-06-22 Seiko Epson Corp Semiconductor device and method for manufacturing the same
US7153765B2 (en) * 2005-03-31 2006-12-26 Intel Corporation Method of assembling soldered packages utilizing selective solder deposition by self-assembly of nano-sized solder particles
JP2008160168A (en) * 2008-03-26 2008-07-10 Seiko Epson Corp Semiconductor device, and method for manufacturing the same
EP1926144A3 (en) * 2006-11-24 2009-10-07 Shinko Electric Industries Co., Ltd. Semiconductor device and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165382A (en) * 2004-12-09 2006-06-22 Seiko Epson Corp Semiconductor device and method for manufacturing the same
JP4606145B2 (en) * 2004-12-09 2011-01-05 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof
US7153765B2 (en) * 2005-03-31 2006-12-26 Intel Corporation Method of assembling soldered packages utilizing selective solder deposition by self-assembly of nano-sized solder particles
EP1926144A3 (en) * 2006-11-24 2009-10-07 Shinko Electric Industries Co., Ltd. Semiconductor device and manufacturing method thereof
US7763977B2 (en) 2006-11-24 2010-07-27 Shinko Electric Industries Co., Ltd. Semiconductor device and manufacturing method therefor
JP2008160168A (en) * 2008-03-26 2008-07-10 Seiko Epson Corp Semiconductor device, and method for manufacturing the same

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