JPH04116831A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04116831A JPH04116831A JP23768490A JP23768490A JPH04116831A JP H04116831 A JPH04116831 A JP H04116831A JP 23768490 A JP23768490 A JP 23768490A JP 23768490 A JP23768490 A JP 23768490A JP H04116831 A JPH04116831 A JP H04116831A
- Authority
- JP
- Japan
- Prior art keywords
- opening part
- solder
- resist
- buffer layer
- barrier metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 229910000679 solder Inorganic materials 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000002161 passivation Methods 0.000 claims abstract 2
- 238000005275 alloying Methods 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract description 7
- 238000007747 plating Methods 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- 239000011261 inert gas Substances 0.000 abstract description 2
- 230000008018 melting Effects 0.000 abstract description 2
- 238000002844 melting Methods 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052802 copper Inorganic materials 0.000 abstract 1
- 239000000203 mixture Substances 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 208000003464 asthenopia Diseases 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010828 elution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
Landscapes
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に係わるもので、特に、
はんだバンプ方式の半導体装置の製造方法に関するもの
である。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular,
The present invention relates to a method of manufacturing a solder bump type semiconductor device.
本発明は集積回路上に形成されたはんだバンプをマスク
として、バッファ層およびバリアメタル層を自己整合的
にエツチング除去する半導体装置の製造方法において、
エツチング中にはんだが受けるダメージを軽減させるこ
とを目的としてエツチング工程の前にはんだのアニール
工程を追加したものである。The present invention provides a method for manufacturing a semiconductor device in which a buffer layer and a barrier metal layer are etched away in a self-aligned manner using solder bumps formed on an integrated circuit as a mask.
A solder annealing process is added before the etching process in order to reduce damage to the solder during etching.
従来より貴金属を主成分としたバンプに関しては、バン
プをマスクとした自己整合的なエツチングも行われてい
る０通常バリアメタルとして用いられるＣｒは不働態化
し易く、腐食性の強いエンチャントが使用されているた
め、Ａｕなどの貴金属を主成分とするバンプでは自己整
合的なエツチングが可能であったが、耐食性に劣るはん
だバンプでは前述の製造方法に関して詳述している報告
は少ない、開示例としては特開平２−７１２７２号公報
が挙げられる程度である。Conventionally, for bumps made mainly of noble metals, self-aligned etching using the bumps as a mask has also been carried out. Cr, which is normally used as a barrier metal, is easily passivated and highly corrosive enchantments are used. Therefore, self-aligned etching was possible for bumps mainly composed of noble metals such as Au, but there are few reports detailing the above manufacturing method for solder bumps with poor corrosion resistance. JP-A-2-71272 can be mentioned.
フェリシアン系のエッチャントを使用することで、はん
だバンプにダメージを与えずにＣｒを主成分としたバリ
アメタル層のエツチングが可能である。しかし、Ｓｎ
−Ｐｂ系ないし５ｎ−Ｐｂ−Ｂｉ系のはんだで比較的Ｓ
ｎを多く含有する組成のバンプにおいて、実装時に無色
透明〜茶褐色の付着物が若干発生するという１ｌｌｌｌ
を有していた。By using a ferrician-based etchant, it is possible to etch the barrier metal layer mainly composed of Cr without damaging the solder bumps. However, Sn
- Relatively S with Pb-based or 5n-Pb-Bi-based solder
In bumps with a composition containing a large amount of n, some colorless and transparent to brownish deposits are generated during mounting.
It had
ＡＥＳ分析およびＦＰＭＡ分析の結果より、この付着物
はＳｎの酸化物ないし水酸化物とフラフクスの混合物で
あることが判明した。The results of AES analysis and FPMA analysis revealed that this deposit was a mixture of Sn oxide or hydroxide and flux.
上記の課題を解決するために、はんだバンプを形成後、
アニール処理を施してからバッファ層およびバリアメタ
ル層のエツチングを行うようにした。In order to solve the above problems, after forming solder bumps,
After annealing, the buffer layer and barrier metal layer are etched.
はんだバンプは一般的にめっき法ないし蒸着法により形
成される。従ってバンプ表面は凹凸が激しく比表面積が
大きい上に、Ｓｎ、 Ｐｂが合金化していないために腐
食され易い、ところがエツチング工程の前にアニール処
理することでＳｏ、 Ｐｂ粒子の凝集・緻密化さらに合
金化の効果によりＳｎの溶出が抑制され、前述の付着物
の生成が防止される。Solder bumps are generally formed by plating or vapor deposition. Therefore, the bump surface is highly uneven, has a large specific surface area, and is easily corroded because Sn and Pb are not alloyed.However, by annealing before the etching process, the So and Pb particles agglomerate and become densified, and the alloy is Due to the effect of oxidation, the elution of Sn is suppressed, and the formation of the above-mentioned deposits is prevented.
本発明によるはんだバンプ形成の実施例を第１図ｆａ）
〜＋ｄｌの断面図に示した。An example of solder bump formation according to the present invention is shown in FIG.
It is shown in the cross-sectional view of ~+dl.
集積回路基板１上にＭからなるバンド２を形成後、プラ
ズマＣＶＤ法により窒化珪素からなるパンシベーション
膜３で被覆し、フォトリソ工程とドライエツチング法に
より開孔部４を形成すると同図ｔａ＋の構造となる。After forming a band 2 made of M on an integrated circuit substrate 1, it is coated with a pansivation film 3 made of silicon nitride by a plasma CVD method, and an opening 4 is formed by a photolithography process and a dry etching method, resulting in the structure shown in the figure ta+. becomes.
次に、パンシベーシヲン膜３および開孔部４上にＣｒか
らなるバリアメタル層５をスパッタリングにより約１５
００人析出し、続いてＣｕからなるバッファ層６を同じ
くスパッタリングにより約５ｏｏｏ人析出した。はんだ
の融点以上の耐熱性を有するレジスト （実施例ではポ
リイミド系のものを使用）をスピンコータを使用して厚
さ数１０ＪＱＩにコーティングし、フォトリソ工程によ
りバッド２上かつ開孔部４を覆う大きさのレジスト開孔
部７を形成し、その開孔部に選択されるめっき法により
はんだバンプ８を形成すると同図（ｂ）の構造となる。Next, a barrier metal layer 5 made of Cr is deposited on the pansibasion film 3 and the opening 4 by sputtering for a thickness of approximately 15 cm.
Then, a buffer layer 6 made of Cu was similarly deposited by sputtering in a thickness of about 500 mm. A resist having a heat resistance higher than the melting point of the solder (polyimide is used in the example) is coated using a spin coater to a thickness of several 10 JQI, and a size that covers the pad 2 and the opening 4 is formed using a photolithography process. When resist openings 7 are formed, and solder bumps 8 are formed in the openings by a selected plating method, the structure shown in FIG. 3(b) is obtained.
続いて、本発明の特徴とする不活性ガス雰囲気のオープ
ン中（約２５０℃）で３０分間アニール処理を施すこと
によりはんだは軟化・溶融し、同図（Ｃ１に示したよう
な形状になる。Subsequently, the solder is softened and melted by performing an annealing treatment for 30 minutes in an open inert gas atmosphere (approximately 250° C.), which is a feature of the present invention, and the solder becomes shaped as shown in the same figure (C1).
次に、レジスト剥離し、その後にはんだバンプ８゛をマ
スクとしてＣｕからなるバッファ層６を以下の組成のエ
ッチャントを使用して除去した。Next, the resist was stripped off, and then, using the solder bumps 8' as a mask, the buffer layer 6 made of Cu was removed using an etchant having the following composition.
Ｈ□ＳＯ４・・・・・・・ ２５−
ＨｔＯｘ （３０％水溶液）・・・３４〇−ＨｔＯｘ・
・・・・・・・６３５−
次に、Ｃｒからなるバリアメタル層５を以下の組成のエ
ッチャントを使用して除去した。H□SO4・・・・・・25-HtOx (30% aqueous solution)・・・34〇-HtOx・
635- Next, the barrier metal layer 5 made of Cr was removed using an etchant having the following composition.
Ｋｓ ［Ｆ ｅ （ＣＮ）＆］ ・・５００ ｇＫＯ
Ｈ・・・・・・・・ ２５０ｇ
Ｈ１Ｏ・・・・・・・・・２５００ｇ
以上の製造方法により形成されたはんだバンプの構造を
同図Ｔｄｌに示した。Ks [F e (CN) &]...500 gKO
H...250g H1O...2500g The structure of the solder bump formed by the above manufacturing method is shown in Tdl in the same figure.
本発明の製造方法によって共晶点付近のはんだ組成にお
いてもリフロー時に付着物が生成しなくなった０通常の
はんだバンプではＳｎウィスカーの発生を防止するため
、共晶点よりＳｎクリンチ組成のものは使用されないた
め、必要にして十分な組成領域のはんだバンプの製造が
可能である。Due to the manufacturing method of the present invention, deposits are no longer generated during reflow even with solder compositions near the eutectic point.In order to prevent the formation of Sn whiskers in normal solder bumps, those with a Sn clinch composition below the eutectic point are used. Therefore, it is possible to manufacture solder bumps with a necessary and sufficient composition range.
本発明により、Ｓｎの含有量が多いはんだ組成において
もリフロー時の付着物発生が防止され、外観不良品が減
少した。また、はんだバンプの表面がつや消し状態にな
るので外観検査時の目の疲労を軽減する等の効果がある
。According to the present invention, the generation of deposits during reflow is prevented even in solder compositions with a high content of Sn, and the number of products with poor appearance is reduced. Furthermore, since the surface of the solder bump becomes matte, it has the effect of reducing eye fatigue during appearance inspection.
第１図＋ａ＋、 （ｂ）、 （Ｃ１，（ｄｌは本発明に
よるはんだバンプの製造方法を断面図で示したものであ
る。
１・・・集積回路基板
・パッド
・バ７シベーション膜
・開孔部
・バリアメタル層
・バッファ層
・レジスト開孔部
・はんだバンプ
・アニール後のはんだバンプ
以上
出願人 セイコー電子工業株式会社
代理人 弁理士 林 敬 之 肋
木発明の製造工種Ｅ示オ断面図
第１図Figure 1 +a+, (b), (C1, (dl) is a cross-sectional view showing the method of manufacturing a solder bump according to the present invention. 1...Integrated circuit board, pad, busivation film, opening Holes, barrier metal layers, buffer layers, resist openings, solder bumps, solder bumps after annealing, etc. Applicant: Seiko Electronics Industries Co., Ltd. Agent Patent attorney: Takayuki Hayashi Cross-sectional diagram showing the manufacturing type E of the crossbar invention No. 1 figure
Claims (1)
おいて、 集積回路基板上に存在するパッド上のパッシベーション
膜に開孔部を形成する工程と、 該パッシベーション膜上および開孔部にバリアメタル層
およびバッファ層を順次積層し、耐熱性のレジストを用
いてバッファ層上に開孔部を覆う大きさのはんだバンプ
を形成する工程と、 該はんだバンプを合金化した後にレジスト剥離を行い、
バンプをマスクとしてバッファ層、バリアメタル層をエ
ッチング除去する工程と、 を含むことを特徴とする半導体装置の製造方法。[Claims] A method for manufacturing a bump electrode formed on an integrated circuit board, comprising: forming an opening in a passivation film on a pad existing on the integrated circuit board; A process of sequentially stacking a barrier metal layer and a buffer layer on the buffer layer, forming a solder bump large enough to cover the opening on the buffer layer using a heat-resistant resist, and removing the resist after alloying the solder bump. and
A method for manufacturing a semiconductor device, comprising: etching away a buffer layer and a barrier metal layer using a bump as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23768490A JPH04116831A (en) | 1990-09-06 | 1990-09-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23768490A JPH04116831A (en) | 1990-09-06 | 1990-09-06 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04116831A true JPH04116831A (en) | 1992-04-17 |
Family
ID=17018977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23768490A Pending JPH04116831A (en) | 1990-09-06 | 1990-09-06 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04116831A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006165382A (en) * | 2004-12-09 | 2006-06-22 | Seiko Epson Corp | Semiconductor device and method for manufacturing the same |
| US7153765B2 (en) * | 2005-03-31 | 2006-12-26 | Intel Corporation | Method of assembling soldered packages utilizing selective solder deposition by self-assembly of nano-sized solder particles |
| JP2008160168A (en) * | 2008-03-26 | 2008-07-10 | Seiko Epson Corp | Semiconductor device, and method for manufacturing the same |
| EP1926144A3 (en) * | 2006-11-24 | 2009-10-07 | Shinko Electric Industries Co., Ltd. | Semiconductor device and manufacturing method thereof |
-
1990
- 1990-09-06 JP JP23768490A patent/JPH04116831A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006165382A (en) * | 2004-12-09 | 2006-06-22 | Seiko Epson Corp | Semiconductor device and method for manufacturing the same |
| JP4606145B2 (en) * | 2004-12-09 | 2011-01-05 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof |
| US7153765B2 (en) * | 2005-03-31 | 2006-12-26 | Intel Corporation | Method of assembling soldered packages utilizing selective solder deposition by self-assembly of nano-sized solder particles |
| EP1926144A3 (en) * | 2006-11-24 | 2009-10-07 | Shinko Electric Industries Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US7763977B2 (en) | 2006-11-24 | 2010-07-27 | Shinko Electric Industries Co., Ltd. | Semiconductor device and manufacturing method therefor |
| JP2008160168A (en) * | 2008-03-26 | 2008-07-10 | Seiko Epson Corp | Semiconductor device, and method for manufacturing the same |
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