JP3104232B2 - Gate array structure and method allowing selection with only a second metal mask - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to methods and structures for forming metallization in semiconductor structures. In particular, it relates to forming metallization on a semiconductor gate array so that custom circuits can be completed in less time.

BACKGROUND A gate array is an array of semiconductor circuit elements formed on a substrate of semiconductor devices according to some standard design, usually up to the point where electrical interconnects are manufactured. The electrical interconnects are provided according to a custom pattern so that the resulting integrated circuit performs a particular desired function. Electrical interconnects usually include two layers of metal (or sometimes metal silicide for the first layer) lines, and vias are formed between the two layers to connect the two layers at selected locations. I do.

The formation of a gate array on a semiconductor substrate as a standard lifted item greatly reduces the time required to produce a completed semi-custom integrated circuit after being ordered by a customer. However, in current semi-custom integrated circuit processing techniques, three custom masking steps should still be performed after the custom integrated circuit is ordered. These three steps include creating and patterning a first metal layer, creating an insulating layer and patterning vias (openings in the insulation on the first metal layer), and The creation and patterning of a layer of a second metal, thus completing the interconnect forming the integrated circuit. A final passivation layer is usually provided and patterned for protection from the elements.

SUMMARY The structure and process of the present invention provide a first layer of metal, pattern it with a universal first layer mask (which can be used in many custom circuits), create a dielectric and create a universal Taking into account the patterning with the bias mask and the creation of the second metal layer, all are part of the standard part of producing gate array integrated circuits. A custom masking step to complete the circuit is then only required to pattern the second metal layer. As a novel feature of the present invention, the step of patterning the second metal layer also selectively opens connections in the first metal layer, thus producing the intended circuit function.

The structure and method of the present invention, after ordered, as compared to a standard gate array metallization process
Reduces time and the number of custom steps left to complete an integrated circuit. Manufacturing costs are also significantly reduced since only one custom mask is required.

The structures and processes of the present invention also have greater tolerance for alignment errors in the relative positions of the first metal layer lines, vias and second metal layer lines.

By making the vias wider than the lines to which they connect, as compared to the prior art, and by planarizing the insulating layer created on the first metal before forming the vias, The step of etching after patterning and forming the second metal not only removes the second metal from the undesired regions but also extends the second metal extending into the via located below the exposed second metal. Remove the metal
In addition, the first metal under these exposed vias is removed. It is necessary that the via be wider than the first layer metal line so that the etching of the second metal after patterning also results in a clean cut of the first metal layer line below the exposed via. . However, when forming biases larger than the metal lines below them, extras may be used to avoid etching the silicon substrate under the vias adjacent to the metal lines when these large vias are being etched. Precautionary measures must be taken. Planarizing the dielectric layer created over the first metal layer allows for a controlled via etch down to the first metal without exposing the substrate. With this invention, a standard first metal pattern having excess interconnects can be manufactured, and unnecessary first metal interconnects are broken during the second metal patterning step to perform the desired logic function. To form

A preferred standard layout provides the first layer metal wherever needed in any of many possible circuit designs. The preferred standard layout also provides unusually large vias on the first layer metal wherever the first metal line would have to be cut for any of many circuit designs. . Thereafter, a single custom mask can pattern the second metal and prepare to cut the first metal where needed.

Another feature of the present invention is that the first and second
Are the same material or materials that can be etched with the same etchant. Preferred embodiments use aluminum or aluminum alloys. Alternatively, two different materials can be used for the first and second layer interconnects, and the two materials are sequentially etched with a sequential etchant.

As another feature of the present invention, the first will have vias thereon for the second layer contact.
If it is desired to protect certain parts of the first layer metal, but it is not desired that the first layer line be cut there, then use it to etch the first layer metal. A layer of barrier metal that reacts differently to the etchant to be deposited can be placed over these portions of the first layer metal, so etching the second layer metal also includes etching the first layer metal under the barrier metal. Will not etch.

Providing this barrier metal allows for unusually large vias. This has the advantage that the first layer metal lines can be made smaller, as the alignment error tolerance can be provided by vias instead of the first metal lines. The second metal can likewise be made smaller.
This means that the entire device can be scaled down. Thus, the structure and method of the present invention not only allows for faster completion between order and shipment, but also allows for more compact integrated devices to take into account more complex integrated circuits on a given size die. Results.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1a and 1b illustrate a first metal interconnect pattern on a gate array substrate formed using the teachings of the present invention in plan and side views.

FIG. 2 illustrates the structure of FIG. 1b with the addition of an insulating layer.

FIG. 3 illustrates the structure of FIG. 2 with the addition of a photoresist layer.

FIG. 4a illustrates the structure of FIG. 3 planarized to a first metal level.

FIG. 4b illustrates the structure of FIG. 4a with the addition of a dielectric layer.

5a and 5b show a plan view and a cross-sectional view of the structure of FIG. 4, wherein the dielectric layer of FIG. 4b is patterned to form vias.

FIG. 6 illustrates the structure of FIG. 5b with the addition of a second layer of metal.

FIG. 7 illustrates the structure of FIG. 6 provided with a custom layer of photoresist and patterned.

8a and 8b illustrate the structure of FIG. 7 in which the first and second metal layers have not been covered by the photoresist.

FIG. 9 illustrates the structure of FIG. 8b, provided with a final insulating layer.

FIG. 10 shows the first insulating and exposed barrier metal layer.
FIG. 10 illustrates a side view of a patterned structure similar to that of FIG. 9 provided on the layer metal of FIG.

FIGS. 11a-11e illustrate top view layouts of vias and interconnects that may be made using the teachings of the present invention.

DETAILED DESCRIPTION FIGS. 1a and 1b show a plan view and a cross-sectional view, respectively, the cross-section of FIG. 1b being taken along line A--A of FIG. 1a, which is formed on a gate array substrate. Figure 3 illustrates a first metallization layer that has been applied. Like numbers indicate like elements throughout the description and figures.

The layout illustrated in FIG. 1a is AND, OR, NAND, N
It is commonly used to form CMOS structures with groups of four transistors useful for implementing OR and other logic functions. FIG. 1b illustrates a P-type substrate 51 which forms an N-type well 51a therein. Prior to the formation of the metallization layer 53, an oxide insulating layer 52 will have been formed on the surface of the substrate, and a gate such as gate 24 (FIG. 1a) will be formed,
A patterned, self-aligned source region (not shown in cross section in FIG. 1b), used to form a P + drain region 51b in well 51a, and an N + drain region 51c in substrate 51. Will. In terms of the process represented by FIG. 1b, the metallization layer 53
(A first metal) is formed over the patterned oxide layer to make source and drain region contacts at locations such as 53a, 53b, 53c and 53d,
Patterned to create metal interconnects. Oxide regions 52a and 52c are thus exposed.

A single gate, such as gate 24 shown in FIG. 1a, controls adjacent N-channel and P-channel transistors. The N-channel transistor has drain contacts 53c and 53d. The P-channel transistor has drain contacts 53a and 53b. In the example of FIG. 1a, the polysilicon gate 24 controls electron flow through the two substrate channels, for example, a contact
This is between the source region located under 53e and the drain region located under contact 53d. Each source, drain, channel, and gate includes one MOS transistor.

The particular logic function depends on the patterning of the first and second metal connections. With the present invention, custom patterning of both the first and second metals that achieves a wide variety of logic functions can be achieved in a single step, as will be described.

Next, in order to planarize the metallization layer 53,
On the surface of the structure illustrated in FIG. 1b, an insulating layer 54 is provided (see FIG. 2). Then, a photoresist layer 55 is applied to the insulating layer 54, as shown in FIG.

As shown in FIG. 4, photoresist layer 55 and insulating layer 54 are etched by a process that removes photoresist 55 at substantially the same rate as removing insulating layer 54. Etching is performed on the upper portion 54a of the insulating layer 54.
Is removed until the first metallization layer 53 is exposed. The etching may be completed earlier, when all the photoresist is removed, thus producing a flat top layer, or preferably,
It may be terminated at a later point in time when the first metallization layer 53 is exposed. It is advantageous to finish when the first metal is exposed, because it allows for the re-formation of a layer of dielectric over the first metal to a predictable thickness. In each case, the upper surface is flat. Importantly, as FIG. 4a illustrates, no substrate 51 is exposed.
The dielectric is then layered again, as shown in FIG. 4b.
Generated on the entire surface as 56.

Alternatively, to achieve planarization of the insulating layer 54, a layer of polyimide may be used instead of providing a photoresist 55.
May be given to 54. The polyimide is planar by itself, avoiding the step of having to remove the photoresist and the plasma oxide from it, and then regenerate the plasma oxide. However, polyimides will absorb moisture if exposed, and may therefore need to be surface treated with a layer of plasma oxide.

Further alternatively, using coated glass to form insulating layer 54 can result in leveling. Thus, the coated glass allows the insulating layer 54 to be directly planarized. In the past, coated glass was not preferred because the available impurity levels of the coated glass were not high enough.

Due to the planarization step, the lower part of the upper surface of the first metal 53
The dielectric at locations 54a and 54b is hardly etched away.

This planarization step is an important feature of the present invention.
Without that, providing an unusually large via of the present invention would result in etching the silicon substrate 51 at about the same time that the top surface of the first metal 53 became exposed during the via etch. It will be.

FIG. 5a illustrates a plan view, FIG. 5b illustrates a cross-sectional view,
Insulating layer 56 is formed therein, and vias 56a, 56b, 56
c, 56d, and 56e are formed at all locations where it may be desirable later to connect the second metal to the first metal or to break the contact at the earlier formed first metal. Was. FIG. 5b is a cross-sectional view of FIG. 5a taken along line AA. As shown in FIG. 5b, an insulating layer 56 is created over the top surface of the planarized layer including the metallization layer 53 and the insulating layer 54.
Passivation layer 56 is then patterned to form vias such as 56a, 56b, 56c, 56d, and 56e. Next, as shown in FIG. 6, a second metallization layer 57 is formed over the top surface of the semiconductor wafer, and contact regions 57a, 57b, are formed in vias formed in insulating layer 56. Form 57c, 57d, and 57e.

All these steps are part of forming a universal semiconductor structure that can be used for many custom circuits, depending on the master used to pattern the second metal layer 57.

FIGS. 7, 8a, 8b, and 9 illustrate the final customization steps required to produce the circuit specified by the customer. As shown in FIG. 7, a layer of photoresist 58 is created over the second metal layer 57 and regions 58a, 58b, 58c, and 58d are formed using a single custom mask that can be used in the present invention. Is patterned into This patterning exposes locations where the second and also some first metal is to be removed. These exposed portions are removed, as shown in FIG. 8b. Residual photoresist is also removed. A plasma or reactive ion etching process may be selected to avoid cutting under the first and second metals.

In FIG. 8b, a portion of the second metal 57, some of the second metal contacts, and a portion of the first metal have been removed. The resulting circuit is illustrated in plan view in FIG. 8a. After removal of the undesired portions of the first and second metals, as shown in FIG. 9, a final passivation layer 59 is formed.

As shown in FIG. 8b, the patterning step results in the removal of the second metal region 57g (shown in FIG. 7), whereby the second metal regions 57f and 5g are removed.
Disconnect the connection to 7e. The patterning also removes the second metal contact region 57c, a portion of the second metal contact regions 57b and 57d, and further removes the first metal region 53h, 53
Removal of j and 53l resulted (see FIG. 8b). Therefore, the connection was broken between the second metal region 57a and the first metal region 53i. Despite the fact that no photoresist protected the second metal over the first metal region 53a, the connection was broken between the second metal region 57a and the first metal region 53a. Did not. This is because the vias in the insulating layer 56 are the first metal regions 53a.
Because it was not formed on Thus, the structure and method of the present invention take into account both the resiliency of semi-custom circuit design and the speed and low cost of a single custom masking step, resulting in low cost and fast delivery to customers. Occurs.

The single masking and patterning step illustrated in FIG. 7 thus results in customization of the entire circuit. In the prior art, typically three custom masking / patterning steps are required to produce a semi-custom circuit, one for patterning a first metal and one for patterning vias. One was to pattern the second metal. By contrast, with the method of the present invention, only a single custom patterning step after the creation of the second metal is required to form a semi-custom circuit.

The planarization step provided after patterning the first metal and isolating the patterned regions (eg, regions 54a and 54b) requires that the vias for the second metal contact be smaller than the surrounding metal lines Means that there is no Thus, vias can serve the dual function of taking into account the contact between the first and second metals and interrupting the contact between adjacent first metal regions.

As another feature of a given invention, the via does not need to be included within the boundaries of the first metal line at all, and the first metal line has sufficient alignment error tolerance for the via. While maintaining, it can be made narrower than under prior art design criteria. Prior art devices that do not planarize the insulating layer over the first metal must prevent vias from overlapping the first metal, because without planarization, the etching step etches the silicon substrate Or at least it will be exposed. The design criteria requires 1 micron of space on each side of the via above the first metal line,
Taking the vias over the first metal line to account for alignment errors is avoided. Thus, for a 3 micron via, the prior art line width must be 5 microns. Eliminating the prior art requirement that vias do not hang over the first metal allows the first metal to be at least 2 microns smaller, and allows vias to hang over the first metal. If desired (or desired), the first metal line would be 5 in our example.
It can be reduced from one micron wide to one or two microns wide.
In this way, design criteria can be significantly reduced and the entire device can be made significantly smaller. This same principle would be applied if tolerances became tighter in the future and line width could be further reduced.

In some cases, the first metal and the second
Providing contact between the first metal and the second metal, but allowing the contact between the first metal and the second metal to be interrupted without allowing the first metal line to be interrupted. It might be desirable.

In this case, after forming and patterning a first metal layer, forming and patterning an insulating layer thereon, a thin layer of barrier metal is generated and patterned before the second metal layer is generated. Barrier metal formation increases the number of steps required to form the structure, however, these extra steps occur during the formation of the universal structure and do not lengthen the customization process. The number of custom masks needed remains one. The barrier metal is selected to withstand the etchant used to etch the first and second metal lines. The barrier metal is patterned and located above the via in the insulating layer where it is desirable not to interrupt the first metal layer below the via. FIG. 10 illustrates an end view of a structure using barrier metal. As shown in FIG. 10, two regions 61 and 62 of the first metal have been formed. The formation and patterning of the oxide layer 64 followed the planarization oxide layer 63. After formation of these oxide layers, a barrier metal layer 65 was formed and patterned. As illustrated in FIG.
Barrier metal region 65 is larger than first metal regions 61a and 61b that it must protect. Thus, alignment is not critical.

In customizing the structure of FIG. 10, the goal is to connect the first metal region 61a to the first metal region 62a.
And disconnect the connection from the second metal region 66a to the first metal region 61a or 61b, and disconnect the connection between the first metal regions 62a and 62b. However, the connection between the region 61a and the region 61b is not cut. As shown in FIG. 10, barrier metal 65 is patterned to cover first metal regions 61a and 61b, but not to first metal regions 62a and 62b.

Prior to custom patterning, the second metal layer contacts first metal regions 61a and 61b via barrier metal 65 and vias 68a. The second metal layer contacts regions 62a and 62b through via 68b. A single custom mask patterns the photoresist, leaving openings in the area
Etch in the second metal at 69a and 69b. Etching of opening 69a is stopped by barrier metal 65, but etching of opening 69b proceeds in region 69c until regions 62a and 62b are separated. At this point in the process, the barrier metal layer 65 has a second metal region 66a.
Are connected to the first metal regions 61a and 61b. Subsequent etching of this barrier metal (which does not require further masking and patterning) removes the exposed portions of the barrier metal 65 and thus the second metal area 66
Disconnect the connection from a to the first metal regions 61a and 61b.

The tolerance in the alignment of the barrier metal is not critical, because the barrier metal area may be made much larger than the via it is to cover. Also, providing a barrier metal does not further limit alignment tolerances for the custom mask. The opening 69a between the second metal regions 66a and 66b need only be large enough to ensure the separation between these adjacent second metal regions. The alignment between the custom mask and the cell to be customized is simply that region 66b contacts regions 61a and 62a, and that the first metal gap between regions 62a and 62b is sufficient for reliable isolation; Area 66
It only has to be enough for a to be separated from the region 61b.

A successfully used barrier metal with silicon substrate, silicon oxide insulation, and first and second metals of aluminum is titanium-tungsten. When this combination of materials is used, the titanium-tungsten barrier is placed above the insulating layer rather than below, because a fluorine-based etchant that is preferably used to form vias in the oxide is Also, it will remove titanium-tungsten.

FIGS. 11a to 11e illustrate several geometries of first metal, via, and second metal patterning using a single custom mask of the present invention to reach various connection patterns. In FIG. 11b, the first metal layer 11
Are patterned after generation, leaving a cross-shaped pattern as indicated by outline 11-3. After forming the insulating layer over the patterned first metal cross pattern, vias 12 are patterned into the insulating layer, thus exposing the center of first metal cross 11-3. . The formation of the second metal 13 on the upper surface of the wafer is the second metal 13
Contact the first metal cross 11-3 within the outline of the via 12. FIG. 11b illustrates the remaining structure after patterning of the second metal 13, only the L-shaped portion of the second metal 13 remains. In the area 12-1,
The removal of the second metal 13 where the via 12 is located results in the removal of the first metal 11 from the first cross-shaped first metal pattern 11-3, and thus the first metal region 11-1. Disconnect the electrical connection between the first metal regions 11-2 and 11-4. The presence of the insulating layer over the first metal regions 11-1 and 11-2 is such that subsequent removal of the second metal 13 also
From removing the metal regions 11-1 and 11-2. In region 13-1, the second metal remains over the first metal, but is separated from the first metal by insulating layer 12. In region 13-2, it is within via 12, but second metal 13 is in contact with first metal 11. Thus, the second metal pattern selected in FIG. 11b maintains the electrical connection between the first metal regions 11-4 and 11-5, while at the same time the first metal regions 11-1 and 11-1 11−
It can be seen that this has resulted in the disconnection to connection 2.

Other patterns are illustrated in FIGS. 11a, 11c, 11d, and 11e. In FIG. 11d, the first metal line on which the via is located has been cut during the second metal patterning. In FIG. 11c, the first metal region 15-2 has been cut from the metal region 15-3, and at the same time remains connected to the second metal region 15-1. No. 11a
In the figure, a second metal region 17-1 is a region 16-1 and
Connect 16-3 to each other, but leave region 16-2 disconnected. Of course, many other geometries will be apparent to those skilled in the art. The second metal as used in the present invention may also pass over the first metal region covered by the insulating layer, and between the first metal separated portions or between the separated portions of the semiconductor substrate. Install jumpers between them. It is clear that excellent resilience in customizing the circuit in this way can be achieved through a single patterning step used in the present invention.

This provides a full and complete disclosure of the present invention. Additional embodiments incorporating the teachings of the present invention will be apparent to those skilled in the art in light of this disclosure. In particular, embodiments can be formed that include a third metal layer, so that a single patterning step performed after the formation of the third metal layer is three times.
It will be clear that a semi-custom circuit with two metal layers can result. It will also be apparent that subsequent custom steps may be performed after performing a single custom step that removes portions of two or more layers of metal. Such changes are intended to fall within the scope of the present invention.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-53-78789 (JP, A) JP-A-62-35537 (JP, A) JP-A-57-106146 (JP, A) JP-A 58-78 37933 (JP, A) JP-A-61-168244 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 27/118

Claims (13)

(57) [Claims] A semiconductor substrate on which a semiconductor structure is formed; a first insulating layer formed and patterned on the substrate, exposing a portion of the substrate; A first conductive layer formed on the exposed portion of the substrate, wherein the first conductive layer is formed by removing a part of the first conductive layer and forming a first line width. Patterned to leave a first conductive line having a first conductive layer formed thereon and patterned to form a plurality of vias, at least some of the vias being the first conductive line. The width of the first line of the conductive line is at least equal to or greater than the width of the first line;
And a second conductive layer formed on the flattened insulating layer, exposing the entire width of a part of the conductive line, and the second conductive layer. Subsequent patterning can remove a portion of both the second conductive layer and the first conductive layer, thereby patterning the second conductive layer and removing the second conductive layer. Blocking a selected connection between a conductive layer and the first conductive layer, blocking a connection between a selected portion of the first conductive layer, and on the first conductive layer. The semiconductor structure further comprising a barrier conductive layer formed on the substrate. 2. The method of claim 1, wherein the via is wider than the first line width of the first conductive line, thereby allowing a tolerance in alignment between the via and the first conductive line. Item 2. The semiconductor structure according to item 1. 3. The barrier conductive layer is patterned such that said subsequent patterning of said second conductive layer leaves a complete portion of said first metal underlying said barrier metal. The semiconductor structure according to claim 1. 4. The semiconductor structure of claim 1, wherein said barrier conductive layer is formed on said planarized insulating layer. 5. The semiconductor device according to claim 1, wherein said substrate is silicon, said insulating layer is silicon oxide,
5. The semiconductor structure of claim 4, wherein said conductive layer is aluminum and said barrier conductive layer is titanium-tungsten. 6. A step of forming a semiconductor substrate on which a semiconductor structure is formed, a step of forming a first insulating layer on the semiconductor substrate, and patterning the first insulating layer to form a semiconductor substrate. Exposing a portion; forming a first conductive layer on the first insulating layer and the exposed portion of the substrate; patterning the first conductive layer to form a first conductive layer; Leaving a first conductive line having a line width and leaving a contact for contacting the substrate; and forming a second insulating layer on the first conductive line and the first insulating layer. Flattening the second insulating layer to avoid immersion on the area where the first conductive layer has been removed; and patterning the second insulating layer. Forming vias, at least some of the vias are at least as wide as or wider than the first line width of the first conductive line, such that the first conductive line has Exposing a part of the entire width, further comprising forming a second conductive layer on the second insulating layer and the exposed portion of the first conductive line, wherein the second conductive layer Subsequent patterning may remove portions of both the second conductive layer and the first conductive layer, and provide electrical connections between selected portions of the second conductive layer. Blocking a selected connection between the second conductive layer and the first conductive layer, and a selected connection between a selected portion of the first conductive layer; Forming a barrier metal layer between the second conductive layer and the second insulating layer; Step further comprises a method for forming a semiconductor structure. 7. After forming the second conductive layer, the method further includes patterning the semiconductor structure and removing a portion of the first and second conductive layers, thereby providing semi-custom integration. 7. The method for forming a semiconductor structure according to claim 6, wherein the method forms a circuit. 8. The device of claim 1, wherein the via is wider than the first width of the first conductive line, thereby allowing a tolerance in alignment between the via and the first conductive line. 7. A method for forming a semiconductor structure according to claim 6. 9. The method further comprising patterning the barrier metal layer to expose a portion of the first conductive layer.
A method for forming a semiconductor structure according to claim 6. 10. A semiconductor substrate, comprising: a first metal layer formed on the semiconductor substrate and in contact with the substrate at a selected location, wherein the first metal layer is patterned. Forming a first metal line at every location where a portion of said first metal layer must be able to be connected to another portion of said first metal layer in any semi-custom circuit; A second metal layer formed on the first metal layer and between the first metal layer and the second metal layer cannot be cut to form any semi-custom circuit. And a planarized insulating layer in which vias are patterned over all portions of the first metal layer that must be connected to a second metal layer. The process for removing metal in the second metal layer located within the via is sufficiently large that the via also results in cutting the first metal line at a location below the via And further comprising a barrier conductive layer formed on the first metal layer, wherein a single mask is formed between the first metal layer and the second metal layer to produce the semi-custom circuit. A semiconductor gate array structure to form a semi-custom circuit that can help pattern both. 11. Adjacent to said patterned first metal layer such that an upper surface of said patterned first metal layer and an upper surface of a planarizing insulating layer are approximately coplanar. 11. The semiconductor gate array structure according to claim 10, further comprising the planarizing insulating layer located at a distance. 12. A semiconductor substrate, a first metal layer formed on the semiconductor substrate, contacting the substrate at a selected position, and patterned with a selected pattern; A second metal layer formed on the first metal layer, wherein the second metal layer is patterned such that in any semi-custom circuit a portion of the second metal layer is the second metal layer. Forming a second metal line at every location that must be able to be connected to another part of the first metal layer and between the first metal layer and the second metal layer; A first planarized insulating layer having vias connecting a portion of the first metal layer to the second metal layer; a third metal layer formed on the second metal layer; The second metal layer and the third gold A second planarized insulating layer having vias over all portions of said second metal line that must be able to be cut to form any semi-custom circuits between the layers; Wherein the via is sufficiently large that the process for removing metal from the third metal layer at a location within the via also results in cutting the second metal line at a location below the via. And further comprising a barrier conductive layer formed on the second metal layer, wherein a single mask combines both the second metal layer and the third metal layer to produce the semi-custom circuit. Semiconductor gate array structure for forming a semi-custom circuit, which can help pattern the semiconductor device. 13. The patterned first metal layer, wherein the top surface of the patterned first metal layer and the top surface of the first planarizing insulating layer are approximately coplanar. The first planarizing insulating layer and the upper surface of the patterned second metal layer and the upper surface of the second planarizing insulating layer are approximately flush with each other. 13. The semiconductor gate array structure of claim 12, further comprising: said second planarizing insulating layer positioned adjacent to said patterned second metal layer.