JPS5837933A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS5837933A JPS5837933A JP13546181A JP13546181A JPS5837933A JP S5837933 A JPS5837933 A JP S5837933A JP 13546181 A JP13546181 A JP 13546181A JP 13546181 A JP13546181 A JP 13546181A JP S5837933 A JPS5837933 A JP S5837933A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring layer
- insulating layer
- filler
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体集積回路装置、特にマスタースライス方
式による大規模集積回路装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to an improvement in a large-scale integrated circuit device using a master slice method.
半導体集積回路装置の製法の一つとして、マスタースラ
イス方式が知られている。マスタースライス方式とは、
一つの半導体基板中に各種用途に共通な回路素子の集合
体を予め大量に形成しておき、その後用途に応じて配線
マスクを変え回路素子相互を所望の電気回路動作を呈す
る如く接続して集積回路装置を得る方式で、配線マスク
を変更するのみで各種用途に応じた集積回路装置力ｉ得
られ、開発期間及び製造期間の短縮並びに製造コストの
低減が図れるという利点を有する。この利点は装置の集
積度が高くなればなる程顕著になり、従ってマスタース
ライス方式は、大規模集積回路装置（以下ＬＳＩと称す
）を多品種少量生産する場合に適している。A master slicing method is known as one of the manufacturing methods for semiconductor integrated circuit devices. What is the master slice method?
A large number of circuit elements common to various applications are formed in advance on one semiconductor substrate, and then wiring masks are changed depending on the application and the circuit elements are interconnected and integrated so as to exhibit the desired electrical circuit operation. This is a method for obtaining a circuit device, and has the advantage that integrated circuit device capabilities suitable for various uses can be obtained by simply changing the wiring mask, and development and manufacturing periods can be shortened, as well as manufacturing costs. This advantage becomes more pronounced as the degree of integration of the device increases, and therefore, the master slice method is suitable for producing large-scale integrated circuit devices (hereinafter referred to as LSI) in small quantities in a wide variety of products.
従来のマスタースライス方式を採用したＴ、 Ｓ Ｉ（
以下マスタースライスＬＳＩと称す）は、第１図に示す
ように、一方の主面側に複数個の回路素子よシなる基本
セル１１を多数個一方向に配列して構成した基本セル列
１２を、列間に一定の幅を有する配線領域１３を介して
複数個並設した半導体基板１を準備しておき、用途に応
じて基本セルを所望数接続して論理ブロックを構成し、
論理ブロック間を必要に応じて接続することにより１個
のＬ Ｓ Ｉ ｆ構成している。２は基本セル相互及び
論理ブロック相互を接続する配線である。この配線２は
半導体基板１の一方の主面上の配線領域Ｉ３に対応する
個所に基本セル列と略平行に形成されたアルミニウムの
第１配線層２１と、その上方［６って第１配線層２１と
直交するように形成されたアルミニウムの第２配線層２
２とを選択的に接続して構成される。T, SI (using the conventional master slice method)
As shown in FIG. 1, a master slice LSI (hereinafter referred to as a master slice LSI) has a basic cell array 12 configured by arranging a large number of basic cells 11 each having a plurality of circuit elements in one direction on one main surface side. , prepare a plurality of semiconductor substrates 1 arranged in parallel via wiring regions 13 having a constant width between columns, connect a desired number of basic cells according to the purpose to form a logic block,
One L S I f is constructed by connecting logical blocks as necessary. Reference numeral 2 denotes wiring that connects basic cells and logic blocks. This wiring 2 includes a first wiring layer 21 made of aluminum formed approximately parallel to the basic cell row at a location corresponding to the wiring region I3 on one main surface of the semiconductor substrate 1, and above it [6 is a first wiring layer 21]. A second wiring layer 2 of aluminum formed perpendicular to the layer 21
2 are selectively connected.
このようなマスタースライスＬＳＩの課題の１つは、で
きるだけ少ない配線によって所望の機能を有するＬＳＩ
全実現することである。配線を少なくすれば、単に配線
領域を狭くでき高集積化が図れるだけでなく、配線に余
裕がなくて基本セルを有効に利用することができなくな
るという事態を解消して、基本セルを有効に利用して高
集積化が図れるのである。One of the challenges of such a master slice LSI is to create an LSI that has the desired functions with as few wiring lines as possible.
It is all about realization. Reducing the amount of wiring not only narrows the wiring area and achieves higher integration, but also eliminates the situation where the basic cells cannot be used effectively due to lack of wiring, making the basic cells more effective. This can be used to achieve high integration.
配線を少なくする方法としては、マスタースライス方式
でＬＳＩ＝ｉ設計する場合に生じる未使用の基本セル或
いは回路素子上を配線領域として利用することが考えら
れる。しかしながら、未読用の基本セル或いは回路素子
上に配線を形成すると種々の不都合が生じ好ましくない
。これを第２図により説明する。第２図は未使用の回路
素子であるＰチャネルトランジスタ上に配線を形成した
場合の一例で、１は半導体基板、１１１ｓ及び１１１Ｄ
は半導体基板に形成されノース領域及びドレイン領域、
１１１Ｇはソース領域とドレイ／領域間のチャネルが形
成される部分の半導体基板ｌ上にＳｉ□、、膜３１全介
して形成されポリシリコンのゲート電極、３２はソース
領域及びドレイン領域を形成する際に形成された５ｉｏ
２膜、３３はソース領域、ドレイン領域、ゲート電極及
びＳｉ□、膜上に形成した燐ガラスの如き絶縁層。One possible method for reducing the number of wiring lines is to use as a wiring area an unused basic cell or circuit element that occurs when LSI=i is designed using the master slice method. However, forming wiring on unread basic cells or circuit elements causes various problems and is not preferable. This will be explained with reference to FIG. Figure 2 shows an example of wiring formed on a P-channel transistor, which is an unused circuit element, where 1 is a semiconductor substrate, 111s and 111D.
are formed on the semiconductor substrate, and include a north region and a drain region,
111G is a polysilicon gate electrode formed on the semiconductor substrate 1 in the portion where the channel between the source region and the drain/region is formed, through the entire Si□ film 31, and 32 is the polysilicon gate electrode formed when forming the source region and the drain region. 5io formed in
2 film, 33 are a source region, a drain region, a gate electrode, Si□, and an insulating layer such as phosphor glass formed on the film.
２１は絶縁層３３上に形成されたアルミニウムの第１配
線層、３４は第１配線層２１上に形成した有機材料或い
は無機材料から成る絶縁層、２２は絶縁層３４上に形成
したアルミニウムの第２配線層、２３は絶縁層３４に形
成したスルーボール３４１を介して第１配線層と第２配
線層とを接続するコンタクト部分である。21 is an aluminum first wiring layer formed on the insulating layer 33; 34 is an insulating layer made of an organic or inorganic material formed on the first wiring layer 21; 22 is an aluminum first wiring layer formed on the insulating layer 34; The second wiring layer 23 is a contact portion that connects the first wiring layer and the second wiring layer via a through ball 341 formed in the insulating layer 34.
図から明らかなように、未使用の回路素子部分は他の部
分より絶縁層が薄いこと及び凹凸が激しいことから、こ
の部分ヲ配線領域として利用すると次のような欠点があ
る。As is clear from the figure, the insulating layer in the unused circuit element portion is thinner than in other portions and the unevenness is severe. Therefore, if this portion is used as a wiring area, there are the following drawbacks.
（１） 配線層と半導体基板との距離が小さいため。(1) Because the distance between the wiring layer and the semiconductor substrate is small.
両者間の寄生容量が増大し、ＬＳＩの動作速度が低下す
る。The parasitic capacitance between the two increases, and the operating speed of the LSI decreases.
Ｑ）傾斜面にコンタクト用のスルーボールを設けると、
図からもわかるようにスルーホール開口付近で配線層が
薄くなったシ、場合によっては断線のおそれがある。Q) If a through ball for contact is provided on the inclined surface,
As can be seen from the figure, the wiring layer becomes thinner near the through-hole opening, and there is a risk of wire breakage in some cases.
（３）配線層を単に通過させる場合でも、凹凸のために
配線層が薄くなったり断線のおそれがある。(3) Even when the wiring layer is simply passed through, there is a risk that the wiring layer may become thin or disconnected due to unevenness.
これらの欠点のため、未使用の回路素子部分上及びその
周辺は配線領域として利用できず、配線のレイアウトル
ールに制限が増えることになる。Because of these drawbacks, the areas on and around unused circuit element portions cannot be used as wiring areas, which increases restrictions on wiring layout rules.
この結果、基本セル列間の配線領域を広くしたり、基本
セル内の未使用の回路素子が増加したりして集積度が低
下することになる。また、ＬＳＩの設計は電算機が使用
されておシ、配線のレイアウトルールに制限が増加する
と、プログラムが複雑となり演算に時間を要するという
不都合が生じる。As a result, the wiring area between the basic cell rows becomes wider, the number of unused circuit elements in the basic cells increases, and the degree of integration decreases. Furthermore, since computers are used to design LSIs, increasing restrictions on wiring layout rules create problems in that programs become complex and calculations take time.
一方、マスタースライスＬＳＩの基本セル内の回路素子
及び基本セル列間の配線領域全有効に利用するために、
配線領域内に予め所望の回路素子全所望数形成しておき
、必要に応じて論理回路のｖ４成に利用するという思想
がある。この場合には未使用の回路素子が配線領域に相
当数存在することになり、前述の欠点の他に配線領域が
配線のために使用できなくなるという不都合がある。On the other hand, in order to effectively utilize the entire wiring area between the circuit elements in the basic cells of the master slice LSI and between the basic cell columns,
The idea is to form all the desired number of circuit elements in advance in the wiring area and use them for the V4 configuration of the logic circuit as needed. In this case, a considerable number of unused circuit elements will exist in the wiring area, and in addition to the above-mentioned disadvantage, the wiring area cannot be used for wiring.
本発明の目的は、上記の欠点？除去して配線レイアウト
の自由度金高め、集積度の向上全図ったマスタースライ
スＬＳＩに適した半導体巣償回路装置を提供することに
ある。The purpose of the present invention is to solve the above drawbacks? It is an object of the present invention to provide a semiconductor compensation circuit device suitable for a master slice LSI which increases the degree of freedom in wiring layout and improves the degree of integration.
かかる目的を達成する本発明半導体集積回路装置の特徴
とするところは、未使用の回路素子衣面全充填材により
平坦化した点にある。本発明の特徴を具体的に言えば、
マスタースライスＬＳＩの第１金属配線層を形成する表
面の未使用回路素子に対応する個所全充填材により平坦
化した点にある。充填材としては、電気的絶縁物であれ
ば有機材料、無機材料を問わず使用できるが、現時点で
は作業性の点から有機材料が好ましい。A feature of the semiconductor integrated circuit device of the present invention that achieves this object is that the entire surface of an unused circuit element is flattened with a filling material. Specifically speaking, the features of the present invention are as follows:
The point is that all the areas corresponding to unused circuit elements on the surface forming the first metal wiring layer of the master slice LSI are flattened with the filling material. As the filler, any electrically insulating material can be used, regardless of whether it is organic or inorganic, but organic materials are currently preferred from the viewpoint of workability.
以下、本発明を実施例として示した図面により詳細に説
明する。Hereinafter, the present invention will be explained in detail with reference to the drawings shown as examples.
第３図は未使用の回路素子であるＰチャネルトランジス
タ上音本発明に従って平坦化した場合の実施例で、第２
図と同一部分は同一符号を付してるる。４１は絶縁層３
３上のＰチャネルトランジスタに対応する個所に存在す
る凹部に充填され。FIG. 3 shows an example in which a P-channel transistor, which is an unused circuit element, is flattened according to the present invention.
The same parts as those in the figure are given the same reference numerals. 41 is the insulating layer 3
The concave portion existing at the location corresponding to the P-channel transistor on No. 3 is filled.
その表面は平坦化され絶縁層３３の平坦部分の表面と略
同−レベルとなるように形成された充填材である。この
充填材４１のため、第１配線層２１は絶縁ノー３３及び
充填材４１の上に形成される。The filling material is formed so that its surface is planarized and is approximately at the same level as the surface of the flat portion of the insulating layer 33. Because of this filling material 41, the first wiring layer 21 is formed on the insulation layer 33 and the filling material 41.
かかる構成の本発明半導体集積回路装置によれば次のよ
うな利点がある。The semiconductor integrated circuit device of the present invention having such a configuration has the following advantages.
（１）充填材の形成により、未使用の回路素子付近にお
ける半導体基板と第１配線層との距４を他の個所と同等
にできるため、寄生容量が小さくなり、未使用の回路素
子上に配線を設けても動作速度の低下は生じなくなる。(1) By forming the filler, the distance 4 between the semiconductor substrate and the first wiring layer in the vicinity of unused circuit elements can be made equal to that in other areas, reducing parasitic capacitance and increasing the distance between the semiconductor substrate and the first wiring layer near unused circuit elements. Even if wiring is provided, there will be no reduction in operating speed.
２０００ゲートのマスタースライスＬＳＩで確認したと
ころ、従来構造において未使用回路素子上に配線を設け
ると、未使用回路素子上に配線を設けない場合に比較し
て動作速度は１／１．８と約半分くらいに低下するが、
本発明の構成にすると低下は生じなかった。Confirmed on a 2000-gate master slice LSI, when wiring is provided on unused circuit elements in a conventional structure, the operating speed is approximately 1/1.8 compared to when wiring is not placed on unused circuit elements. It decreases by about half, but
With the configuration of the present invention, no decrease occurred.
（２ン 第１配線層２１が絶縁層３３及び充填材４１
によって平坦化された面に形成されるため、第１配線層
２１が部分的に薄くなったり、ｆＩｊＴ線したシするお
それがなくなる。(2) The first wiring layer 21 is the insulating layer 33 and the filler 41.
Since the first wiring layer 21 is formed on a planarized surface, there is no possibility that the first wiring layer 21 will become partially thin or that the fIjT line will be distorted.
（３）第１配線層２１が平坦面に形成されると、その上
に形成される絶縁層３４及び第２配線層２２を略平坦面
に形成されるため、第１配線層２１と第２配線層２２と
をスルーホール３４１で接続した場合スルーホール３４
１の開口付近で第２配線層２２が薄くなったり、断線し
たりするおそれがなくなる。(3) When the first wiring layer 21 is formed on a flat surface, the insulating layer 34 and the second wiring layer 22 formed thereon are formed on a substantially flat surface. When connecting the wiring layer 22 with the through hole 341, the through hole 34
There is no fear that the second wiring layer 22 will become thinner or disconnected near the opening 1.
（４） 上記（１）、 （２）及び（３）の理由から
配線のレイアウトルール上の制限条件が大幅に低減され
、未使用回路素子上も配線領域として使用できるため、
集積度の向−ヒが図れる。これを２０００ゲートのマス
タースライスＬＳＩで確認したところ、基本セル列間の
みを配線領域とする場合に比較して半導体基板の面積を
７５％に低減できることがわかった。(4) For reasons (1), (2), and (3) above, the restrictions on wiring layout rules are significantly reduced, and unused circuit elements can also be used as wiring areas.
The degree of integration can be improved. When this was confirmed using a master slice LSI with 2000 gates, it was found that the area of the semiconductor substrate could be reduced to 75% compared to a case where the wiring area is only between the basic cell columns.
（５）また、配線のレイアウトルール上の制限条件が大
幅に低減されると、電算機による設計が容易となる。(5) Furthermore, if the restrictive conditions on wiring layout rules are significantly reduced, designing using a computer becomes easier.
次に、本発明の効果の１つである集積度向上を図面を用
いて説明する。Next, an increase in the degree of integration, which is one of the effects of the present invention, will be explained using the drawings.
第４図は基本セル１１を並設して形成される基本セル列
１２内に未使用の回路素子１５が存在する場合に、従来
法による配線（ａ）と本発明による配線（ｂ）とを比較
して示したものである。太い実線は第１配線層２１を、
太い破線は第２配線層２２をそれぞれ示す。従来法では
、未使用の回路素子１５上では第１配線層が通過するこ
と及び第１配線層と第２配線層との接続はできない。こ
のため（ａ）のように第１配線層と第２配線層との接続
は、基本セル列間の配線領域１３で行なわねばならない
。配線領域にも配線（チャネル）数に限度があり、例え
ば図のように４チヤネルであれば隣の配線領域を使わな
いと第１配線層と第２配線層とを接続できなくなる。隣
の配線領域に余裕がない場合には、配線領域を広く設計
しなければ２ｔらない。FIG. 4 shows how wiring by the conventional method (a) and wiring by the present invention (b) are performed when there is an unused circuit element 15 in a basic cell row 12 formed by arranging basic cells 11 in parallel. This is a comparison. The thick solid line indicates the first wiring layer 21,
The thick broken lines indicate the second wiring layer 22, respectively. In the conventional method, the first wiring layer cannot pass over the unused circuit element 15, and the first wiring layer and the second wiring layer cannot be connected. Therefore, as shown in (a), the connection between the first wiring layer and the second wiring layer must be made in the wiring region 13 between the basic cell columns. There is also a limit to the number of wiring (channels) in the wiring area; for example, if there are four channels as shown in the figure, the first wiring layer and the second wiring layer cannot be connected unless the adjacent wiring area is used. If there is not enough room in the adjacent wiring area, the wiring area must be designed to be wider than 2t.
これに対し、本発明を適用すれば、未使用の回路素子上
を第１配線層が、也過することは勿論第１配線層と第２
配線層との接続も可能である。従って、（ｂ）に示すよ
うに配線領域を広くしたり或いは隣の配線領域を便用す
ることなく所望の配線ができる。On the other hand, if the present invention is applied, it goes without saying that the first wiring layer crosses over unused circuit elements.
Connection with wiring layers is also possible. Therefore, as shown in (b), desired wiring can be performed without widening the wiring area or using an adjacent wiring area.
第５図Ｑま基本セル列１２間の配線領域１３に形成した
回路素子１３１が未使用である場合に、従来法による配
線（ａ）と本発明による悶己線（ｂ）とを比較して示し
たものでおる。従来法による場合は１回路素子１３１が
未使用であるとき、回路素子の中央部では第１配線層と
第２配線層との接続は可ｌ止であるが１周辺部ではでき
ない。そこで、第１配線層を（ａ）に示すように折り曲
げて接続の可能な位置まで移動しなければならない。従
って、配線領域を広くして配線数を増加することになる
。FIG. 5 Q shows a comparison between the conventional wiring (a) and the wiring according to the present invention (b) when the circuit element 131 formed in the wiring area 13 between the basic cell rows 12 is unused. It is as shown. In the case of the conventional method, when one circuit element 131 is unused, connection between the first wiring layer and the second wiring layer is possible in the center part of the circuit element, but not in one peripheral part. Therefore, the first wiring layer must be bent as shown in (a) and moved to a position where connection can be made. Therefore, the wiring area must be widened to increase the number of wiring lines.
これに対し１本発明によれば回路素子１３１上のどの個
所においても第１配線層と第２配線層との接続ができる
。従って、第１配線層を折り曲げる必要がなくなり、使
用する配線数が少なくてすむことになる。In contrast, according to the present invention, the first wiring layer and the second wiring layer can be connected at any location on the circuit element 131. Therefore, there is no need to bend the first wiring layer, and the number of wires used can be reduced.
以上のように本発明によれば配線領域内の配線数を低減
することができるため、前述のように東積度の向上を図
ることができるのである。As described above, according to the present invention, it is possible to reduce the number of wires within the wiring region, and therefore, it is possible to improve the East stack ratio as described above.
次に、本発明半導体集積回路装置の製法を第６図により
説明する。Next, a method for manufacturing the semiconductor integrated circuit device of the present invention will be explained with reference to FIG.
まず１通常の方法例えば拡散法によって、複数個の回路
素子よりなる基本セルを多数個一方向に配列して構成し
た基本セル列を、列間に一定の幅を有する配線領域を介
して複数個並設したマスク−と呼ばれる半導体基板１を
準備し、半導体基板の基本セルが露出する側の長面を被
覆している絶縁層３３の、使用される回路素子である左
側のＰチャネルトランジスタのソース及びドレイン頑域
に対応する個所を除去して、ソース及びドレイン領域を
露出する（２す。次に、半４体基板１の絶縁層３３を形
成した側全面に例えばａ磯材料からなる充填材４１を塗
布する（ｂ）。この塗布方法としては凹部を充填してそ
の表面を略平面する必ばかあることから、スピンナー塗
布が好ましい。充填材４１は未使用の回路素子に対応す
る部分を残して他を例えばエンチングによシ除去する（
Ｃ）。これによって、未使用の回路素子上が平坦化され
る。しかる後、第１配線層２１．絶縁層３４及び第２配
線層２２を順次形成して、所望のマスタースライスＬＳ
丁を痔る（ｄ）。First, by using a normal method such as the diffusion method, a plurality of basic cell rows, which are constructed by arranging a large number of basic cells each consisting of a plurality of circuit elements in one direction, are connected via a wiring area having a constant width between the rows. A semiconductor substrate 1 called a mask is arranged in parallel, and the source of the P-channel transistor on the left side, which is the circuit element to be used, of the insulating layer 33 covering the long surface of the semiconductor substrate on the side where the basic cell is exposed is prepared. The source and drain regions are exposed by removing the portions corresponding to the and drain regions (step 2).Next, a filler made of, for example, Aiso material is applied to the entire side of the half-quad substrate 1 on which the insulating layer 33 is formed. 41 is applied (b). As this application method, spinner application is preferable because it is necessary to fill the recesses and make the surface substantially flat.The filler 41 is applied by leaving a portion corresponding to an unused circuit element. and remove others, for example by enching (
C). This flattens the unused circuit elements. After that, the first wiring layer 21. A desired master slice LS is formed by sequentially forming an insulating layer 34 and a second wiring layer 22.
Hemorrhoids (d).
以上は本発明を代表的な実施例を用いて説明したが、本
発明はこれに限定されることなく本発明の思想の範囲内
で種々の変形が可能である。Although the present invention has been described above using typical embodiments, the present invention is not limited thereto, and various modifications can be made within the scope of the idea of the present invention.
′ｉｌ ２ 図 第 ３ 図 第４ 図 （ｂ） 第 ５ 図 ４Ｌノ 'il 2 Figure Figure 3 Figure 4 (b) Figure 5 4L no
Claims (1)
基板と、半導体基板の一方の主面を被覆する第１の絶縁
層と、第１の絶縁層の回路構成に使用されない回路素子
に対応する個所に形成されている四部に充填して第１の
絶縁層表面を平坦化する絶縁物から成る充填材と、第１
の絶縁層及び充填材上に形成された第１配線層と、第１
配線層上に形成された第２の絶縁層と、第２の絶縁層上
に形成され第１配線層と共に回路素子を所望の回路構成
に接続する第２配線層とを具備することを特徴とする半
導体集積回路装置。 ２、特許請求の範囲第１項において、充填材が有機材料
であることを特徴とする半導体集積回路装置。[Claims] 1. A semiconductor substrate in which a large number of circuit elements are arranged in parallel on one main surface side, a first insulating layer covering one main surface of the semiconductor substrate, and a first insulating layer. a filling material made of an insulator, which is filled into four parts formed in locations corresponding to circuit elements not used in the circuit configuration to planarize the surface of the first insulating layer;
a first wiring layer formed on the insulating layer and filler;
It is characterized by comprising a second insulating layer formed on the wiring layer, and a second wiring layer formed on the second insulating layer and connecting the circuit elements together with the first wiring layer to a desired circuit configuration. Semiconductor integrated circuit device. 2. A semiconductor integrated circuit device according to claim 1, wherein the filler is an organic material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13546181A JPS5837933A (en) | 1981-08-31 | 1981-08-31 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13546181A JPS5837933A (en) | 1981-08-31 | 1981-08-31 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5837933A true JPS5837933A (en) | 1983-03-05 |
Family
ID=15152248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13546181A Pending JPS5837933A (en) | 1981-08-31 | 1981-08-31 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5837933A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60193361A (en) * | 1984-03-14 | 1985-10-01 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
| JPH0228369A (en) * | 1988-04-13 | 1990-01-30 | Seiko Epson Corp | Semiconductor device |
| JPH02503972A (en) * | 1988-03-31 | 1990-11-15 | アドバンスト・マイクロ・ディバイシズ・インコーポレーテッド | Gate array structure and method that allows selection using only a second metal mask |
-
1981
- 1981-08-31 JP JP13546181A patent/JPS5837933A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60193361A (en) * | 1984-03-14 | 1985-10-01 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
| JPH02503972A (en) * | 1988-03-31 | 1990-11-15 | アドバンスト・マイクロ・ディバイシズ・インコーポレーテッド | Gate array structure and method that allows selection using only a second metal mask |
| JPH0228369A (en) * | 1988-04-13 | 1990-01-30 | Seiko Epson Corp | Semiconductor device |
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