JP3102281B2 - Layout design method of semiconductor integrated circuit chip and semiconductor integrated circuit chip - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit chip in which a layout pattern of at least a part of a basic cell is shared irrespective of an electronic circuit to be formed, and at least a part of the wiring, The present invention relates to a layout design method for a semiconductor integrated circuit chip when designing a layout according to an electronic circuit to be formed with vias and contacts, and a semiconductor integrated circuit chip designed by such a layout design method for a semiconductor integrated circuit chip. In particular, the present invention relates to a semiconductor integrated circuit chip layout design method and a semiconductor integrated circuit chip that can reduce manufacturing defects such as a via defect and a contact defect of the semiconductor integrated circuit chip.

[0002]

2. Description of the Related Art A semiconductor integrated circuit of an electronic device has many advantages such as a reduction in the size of the entire electronic device, an improvement in reliability, and a reduction in power consumption. In addition, there are various design methods of semiconductor integrated circuits today, and design man-hours and TAT (turn around time) related to the design of semiconductor integrated circuits, design costs and manufacturing costs are reduced. For example, there is a design method and a manufacturing method in which at least a part of the design process and the manufacturing process is shared and prepared in advance, and the other processes are customized.

[0003] This is what is called a semi-custom system, for example, a standard cell system or a gate array system. First, in the standard cell system, registered cells (functional blocks) are arranged and interconnected according to a circuit to be incorporated in a semiconductor integrated circuit. On the other hand, in the gate array method, a basic cell group arranged in a matrix processed before a wiring step is shared, and a subsequent wiring step is performed according to an electronic circuit actually incorporated in the semiconductor integrated circuit. is there. According to such a semi-custom method, it is possible to provide a semiconductor integrated circuit designed for a customer while reducing the TAT at the time of design and production and reducing the cost.

[0004] On the other hand, various techniques have been disclosed for reducing manufacturing defects of semiconductor integrated circuits.

For example, Japanese Unexamined Patent Publication No. 6-85080 discloses a technique for reducing non-uniformity of formation of vias and contacts in a semiconductor integrated circuit chip at the time of manufacturing, and suppressing a defect of the semiconductor integrated circuit due to this. . In Japanese Patent Application Laid-Open No. 6-85080, when the arrangement of contact holes in one chip becomes non-uniform, the etching rate of the tungsten film changes between a dense portion and a sparse portion of the contact hole distribution. We focus on the loading effect that occurs in For this reason, JP-A-6-85080 discloses that
In the semiconductor integrated circuit chip, an appropriate number of dummy contacts are arranged in portions where the distribution of actual contacts is sparse, so that the uneven distribution of the arrangement of contact holes is eliminated. In this way, contact formation defects and the like are reduced.

[0006]

However, a via defect and a contact defect of a semiconductor integrated circuit chip are only caused by a mere non-uniform distribution of vias and contacts as described in JP-A-6-85080. Not found. That is, according to the investigation by the inventors of the present invention, when the number of vias and contacts arranged on the semiconductor integrated circuit chip is small, via defects and contact defects other than factors related to the uniform or non-uniform distribution of the arrangement are considered. Has been found to be more prone to manufacturing defects.

For example, in a semiconductor integrated circuit chip layout-designed by the semi-custom method, an unused layout area where a logic gate or the like is not arranged may be widened. For example, in the gate array system, the number of unused basic cells may increase abnormally depending on the circuit scale (the number of gates) of the logic circuit to be manufactured.
In such a case, it has been found that the via failure and the contact failure tend to be relatively large.

The present invention has been made to solve the above-mentioned conventional problems, and a layout design method of a semiconductor integrated circuit chip capable of more effectively reducing manufacturing defects such as via defects and contact defects. And a semiconductor integrated circuit.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit chip layout design method in which at least a part of a basic cell has a common layout pattern regardless of an electronic circuit to be formed. In the layout design method of the semiconductor integrated circuit chip at the time of layout design at least a part of the wiring, vias and contacts related to the wiring, according to the electronic circuit to be manufactured,
After the layout design of the via and the contact,
The total area occupied by the vias or the contacts arranged on the semiconductor integrated circuit chip is determined. Next, the ratio of the total occupied area to the chip area of a plane on which the electronic circuit of the semiconductor integrated circuit chip is formed is determined by opening. The electronic circuit to be built into the unused basic cell is called a dummy cell if the aperture ratio is less than or equal to a predetermined aperture ratio reference value. independent of the via or the contact and, by which is adapted to the layout designed for placement as a dummy via or dummy contact, which has provided a method of designing a layout of a semiconductor integrated circuit chip which can achieve the above objects is there.

[0010] In the first invention, further,
And two or more dummy vias or dummy
Lay the wiring that connects the tacts together as a dummy wiring.
The above design achieves the above-mentioned object and realizes the isolated die which is not connected to any wiring.
At the via or dummy contact,
Small island-shaped independent wiring (on the upper layer) covering the wiring
The plug may be missing during the process,
Side) island-shaped small independent wiring before the plug formation
Missing during the process, the semiconductor integrated circuit at the time of manufacturing
Adversely affect the chip and cause product defects
Can be prevented.

Further, in the first invention, the above-described object is achieved by designing a layout so that more dummy vias or more dummy contacts are arranged in the dummy cells within a range permitted by a design rule. In addition, when the aperture ratio is equal to or less than the aperture ratio reference value, the aperture ratio can be more effectively improved.

In the first aspect of the present invention, the above-described object is achieved and the layout pattern of the dummy via or the dummy contact is designed in advance as a macro pattern of one dummy cell. Or the dummy con
The layout design of the tact can be performed more efficiently for each dummy cell.

The semiconductor integrated circuit chip according to the second aspect of the present invention has a layout pattern common to at least a part of a basic cell irrespective of an electronic circuit to be manufactured. In a semiconductor integrated circuit chip in which some wirings and vias and contacts related to the wirings are layout-designed, to unused basic cells, the vias or the contacts irrelevant to an electronic circuit to be built, dummy vias or Dummy cells on which dummy contacts are arranged are provided, and further, at least two or more of the dummy vias or dummy wirings for interconnecting the dummy contacts are provided on both the upper layer and the lower layer of these dummy vias or dummy contacts. As a result, while achieving the above-mentioned subject, In the isolated dummy vias or dummy contacts that are not connected, small island-shaped independent wiring (on the upper layer side) covering the plug may be lost during the manufacturing process, or an island-shaped small island under the plug (lower layer side). Provided is a semiconductor integrated circuit chip capable of preventing an independent wiring from being lost in a process before forming the plug, adversely affecting the semiconductor integrated circuit chip at the time of manufacturing, and causing a product defect. Things.

[0014]

Here, first, the gate array system is assumed. That is, it is assumed that a semiconductor integrated circuit chip in which at least a part of a basic cell has a common layout pattern regardless of an electronic circuit to be formed, and that at least a part of wiring and vias and contacts related to the wiring are formed. It is assumed that a semiconductor integrated circuit chip whose layout is designed according to an electronic circuit is used.

In the present invention, first, after layout design of the via and the contact, a total occupied area of the via or the contact arranged on the semiconductor integrated circuit chip is defined. The via and the contact are
Each of them occupies a predetermined layout area. Therefore, the total occupied area is the total occupied area on the layout of the vias actually arranged on the semiconductor integrated circuit chip after the layout design of the vias and the contacts, or on the layout of the contacts. Is the total occupied area.

Next, a ratio of the total occupied area to a chip area of a plane on which the electronic circuit of the semiconductor integrated circuit chip is formed, that is, an aperture ratio (= (the total occupied area / the chip area)) is defined.

Here, according to the investigation by the inventors, it has been confirmed that when the aperture ratio decreases, the via failure and the contact failure tend to increase. This trend is
This is a factor other than the difference in the uniform or non-uniform distribution of the via arrangement or the difference in the uniform or non-uniform distribution of the contact arrangement.

For example, in a standard product of a semiconductor integrated circuit chip having a gate array system, the aperture ratio is 0.5
%. In this product, the aperture ratio is 0.
At 3% or more, product defects due to the via defect and the contact defect were extremely small. On the other hand, in a product having an aperture ratio of 0.2% or less, a product defect occurs due to the via defect or the contact defect.

Focusing on this point, in the present invention, the aperture ratio of a standard type semiconductor integrated circuit chip whose aperture ratio is equal to or less than a predetermined aperture ratio reference value is intentionally increased. ing.

Specifically, if the aperture ratio is equal to or less than the aperture ratio reference value, a dummy via or a dummy contact is arranged in the unused basic cell. These dummy vias or dummy contacts are irrelevant to the electronic circuit to be formed, and are not electrically connected to the electronic circuit to be formed. In the present invention, such unused basic cells, in which these dummy vias or dummy contacts are arranged, are referred to as dummy cells.

As described above, in the present invention, when the aperture ratio is equal to or less than the aperture ratio reference value, the dummy via or the dummy contact is arranged to improve the aperture ratio to the aperture ratio reference value or more. I try to make it. Therefore, according to the present invention, it is possible to further reduce the via failure and the contact failure due to the low aperture ratio.

The present invention is not limited to these.
However, special consideration may be given to the structure of the dummy via or the dummy contact . For example , it has been found that a failure may occur during the manufacture of a semiconductor integrated circuit chip with respect to the dummy via or the dummy contact as described below, and a countermeasure for this may be taken .

As described above, since the via and the dummy contact are independent of the electronic circuit to be formed,
It is conceivable that each of the dummy vias or each of the dummy contacts is separately formed. However, in such an isolated dummy via or dummy contact that is not connected to any wiring, a small island-shaped independent wiring (on the upper layer side) covering the plug may be lost in the manufacturing process.
It has been found by the present inventors that small island-like independent wiring under the plug (lower layer side) is lost in a process before the plug is formed. If a part or all of the wiring or the like relating to the dummy vias and the dummy contacts is missing as described above, the semiconductor integrated circuit chip at the time of manufacture is adversely affected, resulting in a product defect.

Therefore, the present invention is not limited to this.
However , dummy wiring may be performed for all of the dummy vias and the dummy contacts so that at least two or more of the dummy vias or the dummy contacts are connected to each other. With such a dummy wiring, the dummy via itself, the dummy contact itself, and the wiring related thereto are more surely adhered to the semiconductor integrated circuit chip, so that a part of the dummy via is reduced.

FIG. 1 is a flowchart showing the outline of a layout design method for a semiconductor integrated circuit chip according to the present invention.

The layout design method shown in FIG. 1 is based on the gate array type semiconductor integrated circuit. That is, it is assumed that a semiconductor integrated circuit chip in which at least a part of a basic cell has a common layout pattern regardless of an electronic circuit to be formed, and that at least a part of wiring and vias and contacts related to the wiring are formed. A layout design method for performing a layout design according to an electronic circuit is assumed.

In FIG. 1, first, in step 112, the layout of the vias and the contacts is designed so that the user's electronic circuit is built in the semiconductor integrated circuit chip, and then the electronic circuit is actually placed on the semiconductor integrated circuit chip. The total occupied area of the via or the contact is determined. Next, in step 114, step 11
The ratio of the total occupied area determined in 2 to the chip area of the plane on which the electronic circuit of the semiconductor integrated circuit chip is formed is determined as the aperture ratio.

After the aperture ratio is obtained in this way, in step 116, it is determined whether the aperture ratio is equal to or less than a predetermined aperture ratio reference value. If it is determined that the aperture ratio is equal to or less than the aperture ratio reference value, the process proceeds to step 118.
Then, a layout design is performed to arrange the dummy vias or the dummy contacts. Step 118
Then, the present invention is not limited to this, but the layout of the dummy wiring may be designed.
On the other hand, if it is determined in step 116 that the aperture ratio is larger than the aperture ratio reference value, the layout of the dummy vias and the dummy contacts and the layout design of the dummy wiring are not particularly performed.

The inventors are also studying how to facilitate layout design for the dummy vias and the dummy contacts. Although the present invention is not limited to this, the layout pattern of the dummy via or the dummy contact and the dummy wiring is reduced by one because the dummy via and the dummy contact are laid out in units of the dummy cells. The layout can be designed in advance as a macro pattern of the dummy cell. When the layout is designed in advance as a macro pattern in this way, when arranging the dummy via or the dummy contact and the dummy wiring, the dummy via can be designed in units of the dummy cell, and the dummy via or the dummy The layout design of the contact and the dummy wiring can be performed immediately.

The present invention does not specifically limit the size of the dummy via and the dummy contact, the width of the dummy wiring, and the like. However, if the dummy vias and the dummy contacts are too large,
During the manufacturing process, for example, there is a possibility that a concave portion will be formed at the center portion in the etching process. On the other hand, if the size is too small, there arises a problem that the formed dummy vias and dummy contacts are partially missing. Therefore, it is preferable that the layout design of the dummy vias and the dummy contacts and the layout design of the dummy wirings related to the dummy vias and the dummy contacts be performed according to the minimum design rule.

The present invention does not limit the number of the dummy vias provided in the dummy cells or the number of the dummy contacts. However, when designing the layout of a semiconductor integrated circuit chip, the number of unused basic cells may not be sufficient. Therefore, it is preferable to arrange more dummy vias and more dummy contacts in one dummy cell. Therefore, in the present invention, it is preferable to design the layout so that more dummy vias or more dummy contacts are arranged in the dummy cells within the range permitted by the design rules.

The present invention focuses on the fact that the via failure and the contact failure increase when the aperture ratio is low. Here, first, the cause of the increase in the via defect and the contact defect when the aperture ratio decreases can be considered as follows.

FIG. 2 is a sectional view of a via such as a dummy via provided in a semiconductor integrated circuit chip.

In FIG. 2, an insulating film on a semiconductor integrated circuit chip, that is, LOCOS (local oxidation of silicide) is used.
icon) On the layer 11, the wiring 12 by the first metal wiring layer
(For example, dummy wiring) is formed. Also, the LOC
On the OS layer 11, a first CVD film 15, a SOG (spin o
n glass) layer 17 and second CVD (chemical vapor dep)
osition) The layers are stacked in this order.

The first CVD film 15 and the second C
A via hole 5a is provided so as to penetrate the VD film. The via hole 5a is for forming a via for connecting a wiring made of a second metal wiring layer provided on the second CVD film 16 and a wiring 12 made of the first metal wiring layer.

Here, a gas is generated after the SOG layer 17 is formed. This gas is emitted from the location indicated by reference numeral 5c on the wall surface 5b of the via hole 5a via the interface 7 between the first CVD film 15 and the second CVD film 16.

Here, when the number of vias and contacts designed for layout is small and the aperture ratio is low, as a result,
The emission path of the gas emitted from the SOG layer 17 is reduced. In addition, when the gas release path is reduced in this way, the gas remains in the SOG layer 17, and
Higher concentration gas is continuously released into the via hole 5a for a longer period. As described above, when the aperture ratio is reduced and a higher concentration of gas is released for a longer period of time, it is considered that the via failure and the contact failure increase.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 3 is an integrated circuit layout diagram centering on three basic cells of a semiconductor integrated circuit chip to which the present invention is applied.

FIG. 3 shows an integrated circuit layout diagram centering on three basic cells of the semiconductor integrated circuit chip designed by the semiconductor integrated circuit chip layout designing method of the first invention. Alternatively, this FIG.
3 shows an integrated circuit layout centered on three basic cells of an embodiment to which the semiconductor integrated circuit chip of the second invention is applied.

As shown in FIG. 3, in the semiconductor integrated circuit chip of the present embodiment, basic cells indicated by reference numerals 3 or 3A are arranged vertically and horizontally in a matrix without gaps. Further, in such a basic cell, a plurality of MOS (metal oxide semiconductor) transistors and the like are formed in a common pattern regardless of an electronic circuit to be formed.

In accordance with the electronic circuit to be built in the semiconductor integrated circuit chip, a layout design for wiring in each basic cell and vias and contacts for the wiring is performed.
In the basic cell, for example, a NAND logic gate, an OR logic gate, or an inverter gate is formed.
The basic cells having the predetermined functions (logic gates) are interconnected with each other by designing the layout of the wiring, vias, and contacts according to the electronic circuit to be built.

Here, the basic cell 3A shown in FIG. 3 is an unused cell irrelevant to an electronic circuit to be formed. In this embodiment, the unused basic cell 3A is used as the dummy cell.

That is, with respect to the dummy cell 3A, the layout is designed so that the via 5A unrelated to the electronic circuit to be formed is arranged as a dummy via. Further, the layout of all the wirings provided for all the dummy vias 5A is designed as a dummy wiring so that at least two or more dummy vias 5A are connected to each other.

In FIG. 3, specifically, dummy wiring 9A
To 9F. For example, the dummy wiring 9A
Connects three dummy vias 5A in total.
The dummy wirings 9B to 9E connect a total of five dummy vias 5A to each other. The dummy wiring 9
E and 9F represent a total of three dummy vias 5A, respectively.
Are connected to each other.

In this embodiment, the plurality of dummy vias 5A and the dummy wirings 9A shown in FIG.
-9F are all designed in layout according to the minimum design rule. That is, the plurality of dummy vias 5
The length of one side of the layout shape of the square A is the minimum design unit at the time of layout design. The width of the dummy wirings 9A to 9F is the minimum unit of the layout design, and the length is a multiple of the minimum unit of the layout design.

In this embodiment, more dummy vias 5A are arranged in the dummy cells 3A within the range permitted by the design rules. In FIG. 3, the dummy via 5A has a total of 2 except for the power supply wiring 9V and the ground wiring 9G.
Eight are arranged.

Reference numeral 9V indicates a power supply wiring, and reference numeral 9V
G is a ground wiring. The power supply wiring 9V and the ground wiring 9G are arranged in the horizontal direction in FIG. 3 with respect to the basic cells 3 or 3A arranged in a matrix in the vertical and horizontal directions as described above. Power is supplied to each of the basic cells 3 or 3A by a pair of the power supply line 9V and the ground line 9G.

The basic cell 3 shown in FIG.
For each of the dummy cells 3A, the length of the long side on the integrated circuit layout is 24 μm, for example, and the short side is 7.2 μm. Also, the square dummy via 5A
Is 0.8 μm, for example. The aperture ratio (= 1) of one dummy cell 3A in FIG.
(Total occupied area of via in one dummy cell / Dummy cell 1
Chip area) is about 7%.

FIG. 4 is a sectional view of the dummy cell used in this embodiment.

FIG. 4 is a cross-sectional view of a portion shown in FIG .

As shown in FIG. 4, above the insulating layer on the semiconductor substrate, that is, above the LOCOS layer 11, a dummy wiring 12 of a first metal wiring layer is formed. Also, the L
Above the OCOS layer 11, the first CVD film 15 and the second C
A VD film 16 is formed. Via holes are provided in these CVD films 15 and 16, and vias 5 are formed. Above the CVD films 15, 16 and the via 5, a dummy wiring 13 made of a second metal wiring layer is formed. The plurality of vias 5 connect one dummy wiring 12 made of the first metal wiring layer to another dummy wiring 13 made of the second metal wiring layer.

As shown in FIG. 4 or FIG.
In this embodiment, as shown in FIG. 2, the dummy cell 3A is used as an unused basic cell in an electronic circuit to be formed, and a total of 28 dummy vias 5A are arranged for each dummy cell 3A. The rate is improving.
Therefore, even if the aperture ratio is equal to or smaller than the aperture ratio reference value, the aperture ratio of the semiconductor integrated circuit chip can be improved by using such a dummy cell 3A. Thereby, manufacturing defects such as the via defect and the contact defect can be reduced.

Further, in this embodiment, at least two or more dummy vias 5A are connected to each other by the dummy wiring 12 formed by the first metal wiring layer and the dummy wiring 13 formed by the second metal wiring layer. ing. For example, in FIG. 4, a total of three dummy vias 5A are interconnected by dummy wirings 12 and 13. For this reason, the possibility that the dummy via 5A and the wiring or the like relating to the dummy via 5A are lost during the manufacturing process is reduced.

In particular, in the present embodiment, the plurality of dummy vias 5A are connected from above by the dummy wirings 12 of the first metal wiring layer, and
The lack of A is prevented. Further, in this embodiment,
Since the dummy wiring 13 of the second metal wiring layer is provided below the dummy vias 5A, the degree of connection adhesion under the dummy vias 5A is improved.

Generally, the bonding strength between a metal and a metal is better than the bonding strength between a metal and a silicon substrate. Therefore, by forming the dummy via 5A on the dummy wiring 13 by the second metal wiring layer 13, it is possible to more effectively prevent the dummy via 5A from being lost.

Further, in this embodiment, the layout pattern of the dummy vias 5A and the layout pattern of the dummy wirings 9A to 9F in the dummy cell 3A as shown in FIG.
It is registered in advance in units of A. Therefore, if the registered layout pattern of the dummy cell 3A is arranged for the unused cell, the layout design of the dummy via 5A and the dummy wirings 9A to 9F in the dummy cell 3A can be performed at one time. Therefore, it is possible to more easily perform the layout design for the dummy cell 3A.

The pattern of such a dummy cell 3A is not limited to the pattern shown in FIG. For example, as shown in FIG. 5, a layout pattern of the dummy via 5A and the dummy wiring as shown in FIG. Alternatively, as shown in each of FIGS. 5B and 5C, the dummy cell 3A
Layout pattern. These (A) ~
It is also possible to register the layout pattern as shown in (C) in advance.

It should be noted that FIG. 3 and FIG.
With respect to the layout pattern of the dummy cell 3A as shown in (C), the dummy via 5A is not arranged in the power supply wiring 9V or the ground wiring 9G. Here, the power supply wiring 9V
And the arrangement route of the ground wiring 9G may be different. In such a case, the arrangement of the dummy via 5A and the arrangement of the dummy wiring related to the dummy via 5A may be automatically made to correspond to the power supply wiring 9V and the ground wiring 9G set by default or the like. Good.

Hereinafter, the manufacturing process of the semiconductor integrated circuit chip of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 6, a dummy wiring 12 is formed in a first metal wiring layer 12 on a LOCOS layer 11 on a semiconductor substrate. In FIG. 7, the dummy wiring 12
The first CVD film 15 is formed thereon. The first CVD
The film 15 is made of a silicon oxide film 80 by plasma CVD.
00 angstrom deposited. As a source gas used in the plasma CVD, a mixed gas of SiH ₄ (silane) and O ₂ is used. Further, TEOS (organic oxysilane) may be used instead of SiH ₄ .

Subsequently, in FIG. 8, an SOG layer 17 is formed. The SOG layer 17 is formed by spin-coating SOG by 10,000 angstroms and then performing baking. Subsequently, in FIG. 9, the SOG layer 17 is formed.
Then, the first CVD film 15 is etched back. This etch-back is performed by an oxide film dry etching apparatus, and the SOG layer 17 is formed by (CF ₄ / CHF ₃ ).
And etching back the first CVD film 15. This (CF ₄ / CHF ₃ ) is a general mixed gas used for etching.

Subsequently, in FIG. 10, a second CVD film 16 serving as a “cap” is formed. This is plasma CVD
In this case, a silicon oxide film is deposited at 6000 Å. Subsequently, in FIG. 11, a via hole 5a is formed. The via hole 5a is for a dummy via, for example. Also, such a via hole 5a
Is formed by a photolithography / etching technique. When the via hole 5a is formed as described above, the gas starts to be released from the SOG layer 17 through the via hole 5a.

Subsequently, in FIG. 12, a tungsten film 14 is formed. The tungsten film 14 is for forming a tungsten plug used for a dummy via or a general via. This tungsten film 14 is formed by C
About 8000 angstroms of tungsten is deposited by VD (WF ₆ / H ₂ ). That is,
This tungsten film 14 is made of H _{2 of} WF ₆ gas or SiH
It is formed using the reduction reaction by ₄ .

Subsequently, in FIG. 13, the tungsten film 14 is etched back while leaving only the via hole 5a. Thus, a tungsten plug serving as the dummy via 5A is formed. In FIG. 14, a dummy wiring 13 is formed by the second metal wiring layer (SF ₆ ).
The formation of the dummy wiring 13 is performed by etching the deposited tungsten film using SF ₆ as an etching gas. In addition, as this etching gas,
Generally, SF ₆ is used, but NF ₃ may be used. However, NF ₃ is generally expensive.

In this embodiment, the dummy via 5A
Is provided, the aperture ratio of the semiconductor integrated circuit chip can be improved. Therefore, it is possible to discharge more gas from the SOG layer 17 at the stage shown in FIG. Therefore, in FIG. 11 and subsequent figures, in particular, the dummy wiring 13 by the second metal wiring layer
Before the outgassing becomes more difficult,
Outgassing from the OG layer 17 can be effectively performed. This makes it possible to further reduce manufacturing defects such as the via defect and the contact defect.

As described above, in this embodiment, when designing the layout of an electronic circuit created by the user using the basic cells, if the aperture ratio is equal to or less than a predetermined aperture ratio reference value, By using the dummy cell 3A, the aperture ratio can be improved. In this embodiment,
The aperture ratio reference value is 0.4%. This is because, empirically, when the aperture ratio is 0.5% or more, the via failure and the contact failure are reduced, and the aperture ratio is reduced to 0.5%.
This is because it has been confirmed that when the content is 3% or less, these via defects and contact defects increase .

In this embodiment, when the aperture ratio is equal to or less than the aperture ratio reference value, the aperture ratio per dummy cell 3A is 7% as described above.
By arranging the dummy cell 3A, the aperture ratio of the entire semiconductor integrated circuit chip can be improved. The design work of arranging the dummy cell 3A in this manner uses the layout pattern for one dummy cell 3A in which the dummy cell 5A and the dummy wirings 9A to 9F are designed and registered in advance.
It can be done more easily.

In the present embodiment, the dummy via 5
A is at least two of the upper surface and the lower surface, and is connected to each other by the dummy wiring as described above. Therefore, the tungsten plug of the dummy via 5A and the wiring of the dummy via 5A are not dropped. Has been reduced.
For this reason, manufacturing defects due to falling off products are further reduced.

This embodiment relates to the dummy via 5A as described above. However, it is equally possible to apply the invention to dummy contacts.

[0071]

As described above, according to the present invention,
An excellent effect that manufacturing defects such as via defects and contact defects of the semiconductor integrated circuit chip can be more effectively reduced can be obtained.

[Brief description of the drawings]

FIG. 1 is a flowchart showing the outline of a semiconductor integrated circuit chip layout design method according to a first invention of the present application;

FIG. 2 is a sectional view of a via such as a dummy via provided in the semiconductor integrated circuit chip of the first invention or the second invention of the present application;

FIG. 3 is an integrated circuit layout diagram centering on dummy cells of the semiconductor integrated circuit chip to which the first invention and the second invention are applied ;

FIG. 4 is a sectional view of the dummy cell of the embodiment.

FIG. 5 is an integrated circuit layout diagram showing an example of a layout pattern of the dummy cell.

FIG. 6 is a cross-sectional view of the first metal wiring layer of the embodiment after a wiring is formed.

FIG. 7 is a cross-sectional view after a first CVD film is formed in the embodiment.

FIG. 8 is a cross-sectional view after the formation of the SOG layer of the embodiment.

FIG. 9 is a cross-sectional view after etching back the SOG layer of the embodiment.

FIG. 10 is a cross-sectional view of the embodiment after a second CVD film is formed.

FIG. 11 is a cross-sectional view after forming a via hole in the embodiment.

FIG. 12 is a cross-sectional view after forming a tungsten film in the embodiment.

FIG. 13 is a sectional view of the embodiment after etching back the tungsten film.

FIG. 14 is a cross-sectional view of the second metal wiring layer after the wiring is formed in the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit chip 2 ... Semiconductor substrate 3 ... Basic cell 3A ... Dummy cell 5 ... Via 5A ... Dummy via 5a ... Via hole 5b ... Via wall surface 7 ... Film interface 9A-9F ... Dummy wiring 9G ... Ground wiring 9V ... Power supply wiring DESCRIPTION OF SYMBOLS 11 ... LOCOS layer 12 ... Dummy wiring by 1st metal wiring layer 13 ... Dummy wiring by 2nd metal wiring layer 14 ... Tungsten film 15 ... 1st CVD film 16 ... 2nd CVD film 17 ... SOG layer

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Toshiya Takahashi 2-3-2 Uchisaiwai-cho, Chiyoda-ku, Tokyo Kawasaki Steel Corporation, Tokyo Head Office (56) References JP-A-60-226140 (JP, A) (58) ) Surveyed field (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 27/118

Claims (5)

(57) [Claims] 1. A semiconductor integrated circuit chip in which at least a part of a basic cell has a common layout pattern irrespective of an electronic circuit to be formed, at least a part of wiring, a via and a contact related to the wiring are formed. In a layout design method of a semiconductor integrated circuit chip when performing a layout design according to an electronic circuit to be embedded, after the layout design of the via and the contact,
The total occupied area of the via or the contact arranged on the semiconductor integrated circuit chip is obtained. Next, the ratio of the total occupied area to the chip area of a plane on which the electronic circuit of the semiconductor integrated circuit chip is formed is determined by opening. It is determined whether the aperture ratio is equal to or less than a predetermined aperture ratio reference value. If the aperture ratio is equal to or less than the aperture ratio reference value, the electronic circuit is referred to as a dummy cell and is built into the unused basic cell. A layout design method for a semiconductor integrated circuit chip, wherein a layout design is performed such that the via or the contact irrelevant to the layout is arranged as a dummy via or a dummy contact. 2. The semiconductor integrated circuit chip according to claim 1, further comprising a wiring for interconnecting at least two or more of the dummy vias or the dummy contacts as a dummy wiring. Layout design method. 3. The semiconductor device according to claim 1, wherein the layout is designed so that more dummy vias or more dummy contacts are arranged in the dummy cells within a range permitted by a design rule. Layout design method for integrated circuit chips. 4. The method according to claim 1, wherein a layout pattern of the dummy via or the dummy contact is designed in advance as a macro pattern of one dummy cell. A layout design method for a semiconductor integrated circuit chip. 5. A layout pattern of at least a part of a basic cell is shared irrespective of an electronic circuit to be manufactured.
Depending on the electronic circuit to be built, at least some of the wiring,
In a semiconductor integrated circuit chip in which vias and contacts related to the wiring are layout-designed, dummy vias or contacts, which are the vias or the contacts unrelated to the electronic circuit to be built, are arranged in unused basic cells, A dummy cell is provided, and further, a dummy wiring for wiring at least two or more of the dummy vias or the dummy contacts so as to connect them to each other is provided in both the upper layer and the lower layer of the dummy via or the dummy contact. Semiconductor integrated circuit chip.