EP0403571A4 - Gate array structure and process to allow optioning at second metal mask only - Google Patents

Gate array structure and process to allow optioning at second metal mask only

Info

Publication number
EP0403571A4
EP0403571A4 EP19890904937 EP89904937A EP0403571A4 EP 0403571 A4 EP0403571 A4 EP 0403571A4 EP 19890904937 EP19890904937 EP 19890904937 EP 89904937 A EP89904937 A EP 89904937A EP 0403571 A4 EP0403571 A4 EP 0403571A4
Authority
EP
European Patent Office
Prior art keywords
metal
layer
conductive
vias
portions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19890904937
Other versions
EP0403571A1 (en
Inventor
Bradley A. Sharpe-Geisler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP0403571A1 publication Critical patent/EP0403571A1/en
Publication of EP0403571A4 publication Critical patent/EP0403571A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to a process and structure for
  • Gate arrays are arrays of semiconductor circuit elements
  • interconnects are applied according to a custom pattern to
  • the electrical interconnects usually
  • a final passivation layer is usually applied and 6 patterned for protection from the elements.
  • a final passivation layer is usually applied and 6 patterned for protection from the elements.
  • 7 8 SUMMARY The structure and process of this invention allow for applying the first layer of metal, and patterning it with a universal (usable for many custom circuits) first layer mask, depositing the dielectric and patterning this with a universal via mask, and depositing the second layer of metal, all as part of the standard portion of producing a gate array integrated circuit. Custom masking steps to complete a circuit are then required only for patterning the second layer of metal. As a novel feature of this invention, the step of patterning the second layer of metal also selectively opens connections in the first layer of metal, thus producing the intended circuit function.
  • the structure and method of this invention decrease the time and number of custom steps remaining to complete the integrated circuit after it is ordered in comparison to a standard gate array metallization process.
  • the cost of manufacture is also significantly reduced because only one custom mask is required.
  • the structure and process of this invention also have a larger tolerance for alignment error in the relative locations of the first metal layer lines, the vias and the second metal layer lines. in contrast to the prior art, by making vias wider than the lines which they will connect, and by planarizing the insulation layer deposited on the first metal before forming the vias, the step of etching after patterning and depositing second metal removes not only the second metal from unwanted areas but also removes second metal extending into vias located beneath exposed second metal and further removes the first metal located beneath these exposed vias.
  • a standard -> first metal pattern having excess interconnections can be * ⁇ " * manufactured, and unnecessary first metal interconnections cut during the second metal patterning step to form a
  • a preferred standard layout provides first layer metal 1* - ) everywhere it is likely to be needed in any of many possible H circuit designs.
  • a preferred standard layout also provides • - • 2 oversized vias above first layer metal everywhere it is
  • a layer of a 28 barrier metal which responds differently to the etchant used 29 for etching first layer metal can be placed over these 30 portions of first layer metal so that etching the second
  • barrier metal Providing this barrier metal allows oversized vias.
  • Second metal can likewise be made smaller. This means that
  • Figs, la and lb show in plan and side views a first
  • FIG. 2 shows the structure of Fig. lb with the addition
  • FIG. 3 shows the structure of Fig. 2 with the addition
  • Fig. 4a shows the structure of Fig. 3 planarized to the
  • Fig. 4b shows the structure of Fig. 4a with a dielectric
  • Figs. 5a and 5b show plan and cross-sectional views of
  • Fig. 6 shows the structure of Fig. 5b with the addition
  • Fig. 7 shows the structure of Fig. 6 to which a custom
  • FIGs. 8a and 8b show the structure of Fig. 7 in which
  • FIG. 9 shows the structure of Fig. 8b to which a final
  • Fig. 10 shows the side view of a structure similar to
  • Figs, lla-lle show plan view layouts of vias
  • Figs, la and lb show respectively a top view and a cross sectional view, the cross section of Fig. lb taken along line A-A of Fig. la, which shows a first metallization layer deposited on a gate array substrate.
  • the same numerical designations represent the same elements throughout the description and figures.
  • the layout shown in Fig. la is commonly used for forming CMOS structures having groups of four transistors useful for implementing AND, OR, NAND, NOR and other logic functions.
  • Fig. lb shows P-type substrate 51, which has formed therein N-type well 51a. Before formation of metallization layer 53, an oxide insulation layer 52 will have been formed on the surface of the substrate, and gates such as gate 24 (Fig.
  • metallization layer 53 first metal
  • Source and drain region contacts at locations such as 53a, 53b, 53c, and 53d, and has been patterned to produce metal interconnects. Oxide regions 52a and 52c are thus exposed.
  • a single gate, such as gate 24 shown in Fig. la controls adjacent N-channel and P-channel transistors.
  • the N-channel transistor has drain contacts 53c, 53d.
  • the P-channel transistor has drain contacts 53a, 53b.
  • polycrystalline silicon gate 24 controls electron flow through two substrate channels, for example between the source region located beneath contact 53e and the drain region located beneath contact 53d.
  • Each source, drain, channel and gate comprise one MOS transistor.
  • the particular logic function depends upon the patterning of first and second metal connections. According to the present invention, custom patterning of both first and second metal to achieve a wide variety of logic functions can be performed in a single step, as will be described. 1 Next, ' in order to planarize metallization layer 53, a
  • photoresist layer 55 and insulation layer 54 are etched by a process which removes photoresist 55
  • Etching is continued until upper portion 54a of 0 insulation layer 54 is removed and first metallization layer 1 53 is exposed. The etch may be ended at an earlier point
  • polyimide will absorb moisture if left
  • insulation layer 54 can produce leveling.
  • spin-on glass allows insulation layer 54 to be planarized directly.
  • Fig. 5a shows a plan view and Fig. 5b shows a cross- sectional view in which insulation layer 56 has been deposited and vias 56a, 56b, 56c, 56d and 56e have been formed at all locations where it may later be desirable to connect second metal to first metal or to break contact in the earlier formed first metal.
  • Fig. 5b is a cross-sectional view of Fig. 5a taken along the line A-A. As shown in Fig.
  • insulation layer 56 is deposited onto the top of the planarized layer comprising metallization layer 53 and insulation layer 54. Passivation layer 56 is then patterned to form vias such as 56a, 56b, 56c, 56d and 56e.
  • second metallization layer 57 is deposited onto the top surface of the semiconductor wafer forming contact regions 57a, 57b, 57c, 57d and 57e in the vias which were formed in insulation layer 56. All these steps are part of forming a universal semi- conductor structure which can be used for multiple custom circuits, depending upon the mask used for patterning of second metal layer 57. Figs.
  • photoresist layer 58 is deposited onto second metal layer 57 and patterned into regions 58a, 58b, 58c, and 58d using the single custom mask which can be used with this invention. This patterning exposes locations at which second and also some first metal are to be removed. As shown in Fig. 8b, these exposed portions are removed. The remaining photoresist is also removed. A plasma or reactive ion etching process can be selected to avoid undercutting of first and second metal. n Fig. 8b, portions of second metal 57, some of the second metal contacts, and portions of the first metal have been removed.
  • the resulting circuit is shown in plan view in Fig. 8a. " As shown in Fig. 9, after removal of unwanted portions of first and second metal, a final passivation layer 59 is formed. As shown in Fig. 8b, the patterning step has resulted in the removal of second metal region 57g (shown in Fig. 7), thereby severing the connection between second metal regions 57f and 57e. The patterning has also resulted in removal of second metal contact regions 57c part of second metal contact regions 57b and 57d, plus the further removal of first metal regions 53h, 53 , and 53 ⁇ (see Fig. 8b). Therefore connections have been severed between second metal region 57a and first metal region 53i.
  • first metal lines can be made narrower than under prior art design rules while maintaining sufficient alignment error tolerance for vias.
  • a prior art device which does not planarize the insulation layer above first metal must keep the vias from overlapping first metal because without planarizing an etch step would etch or at least expose the silicon substrate.
  • Design rules may require above the first metal lines a 1-micron space on each side of a via to allow for alignment error and avoid having the vias overhang the first-metal line.
  • the prior art line width must be 5 microns. Eliminating the prior art requirement that vias not overhang first metal allows the first metal to be at least 2 microns smaller, and if vias are permitted (or desired) to overhang first metal, the first metal lines can be shrunk, in our example, from a 5-micron width to a one- or two-micron width.
  • the design rules can be remarkably shrunk and the overall device made remarkably smaller. This same principle will apply if in the future tolerances become tighter and line widths can e further reduced. i some cases it may be desirable to provide contact between first and second metals through a via, but to allow the contact between first and second metal to be broken without allowing the first metal line to be broken. in this case, after forming and patterning the first metal layer, and forming and patterning the insulation layer above it, a thin layer of a barrier metal is deposited and patterned before the second metal layer is deposited. The barrier metal formation increases the number of steps needed to form the structure, however these extra steps occur during formation of the universal structure and do not lengthen the customization process. The number of custom masks needed remains one.
  • the barrier metal is selected to be resistant to an etchant used to etch the first and second metal lines.
  • the barrier metal is patterned to be located above vias in the insulation layer where it is desirable not to break, the first metal layer beneath the vias.
  • Fig. 10 shows a side view of a structure in which a barrier metal has been used. As shown in Fig. 10, two regions 61 and 62 of first metal have been formed. Planarization oxide layer 63 has been followed by the formation and patterning of oxide layer 64. After formation of these oxide layers, a layer 65 of barrier metal was formed and patterned. As shown in Fig. 10, barrier metal region 65 is larger than the first metal regions 61a and 61b it must protect. Thus, alignment is not critical. In customizing the structure of Fig.
  • the goal is to leave region 66b of second metal connecting first metal region 61a to first metal region 62a, also to sever the connection from second metal region 66a to first metal regions 61a or 61b and to sever the connection between first metal regions 62a and 62b but "not to sever the connection between regions 61a and 61b.
  • barrier metal 65 has been patterned to cover first metal regions 61a and 61b but not to cover first metal regions 62a and 62b.
  • the second metal layer contacts first metal regions 61a and 61b through barrier metal 65 and via 68a.
  • the second metal layer contacts regions 62a and 62b through via 68b.
  • the single custom mask patterns the photoresist to cause openings to be etched in second metal at regions 69a and 69b» Etching of opening 69a is stopped by barrier metal 65 while etching of opening 69b proceeds in region 69c until regions 62a and 62b are separated. At this point in the process, barrier metal layer 65 connects second metal region 66a to first metal regions 61a and 61b. A subsequent etch of this barrier metal (not requiring further masking and patterning) removes the exposed portions of barrier metal 65, thus severing connection from second metal region 66a to first metal regions 61a and 61b. Tolerance in alignment of the barrier metal is not critical because the barrier metal region may be made sufficiently larger than the via it is to cover.
  • barrier metal does not further restrict alignment tolerances for the custom mask. Opening 69a between second metal regions 66a and 66b need be only wide enough to assure separation between these adjacent second metal regions. Alignment between the custom mask and the cell to be customized must only be sufficient that region 66b contacts region 61a and 62a, that the first metal gap between regions 62a and 62b is sufficient for reliable separation, and that region 66a is separated from region 61b.
  • a barrier metal which has been successfully used with a silicon substrate, silicon oxide insulation, and aluminum first and second metal is titanium-tungsten.
  • first metal layer 11 was patterned after deposition to leave a cross-shaped pattern as indicated by outline 11-3. After forming an insulation layer above the patterned first metal cross-shaped pattern, via 12 is patterned into the insulation layer, thus exposing the center of first metal cross 11-3.
  • Fig. lib shows the remaining structure after patterning of second metal 13, in which only an L-shaped portion of second metal 13 remains.
  • region 12-1 the removal of second metal 13 where via 12 is located has resulted in removal of first metal 11 from the original cross-shaped first metal pattern 11-3, thus severing electrical connection between first metal region 11-1 and first metal regions 11-2 and 11-4.
  • the presence of the insulation layer above first metal regions 11-1 and 11-2 prevents the subsequent removal of second metal 13 from also removing first metal regions 11-1 and 11-2.
  • second metal remains above but separated by insulation layer 12 from first metal.
  • second metal 13 is in contact with first metal 11.
  • the second metal pattern selected in Fig. lib has resulted in retaining the electrical connection between first metal regions 11-4 and 11-5 while severing connections to first metal regions 11-1 and 11-2.
  • Other patterns are shown in Figs. 11a, lie, lid, and lie.
  • Fig. lid a first metal line over which a via is located has been severed during second metal patterning.
  • Fig. lie first metal region 15-2 has been severed from first metal region 15-3 while remaining connected to second metal region 15-1.
  • second metal region 17-1 connects regions 16-1 and 16-3 to each other but leaves region 16-2 disconnected.
  • Second metal can also pass above first metal regions covered by an insulation layer and provide a jumper between remote portions of first metal or remote portions of the semiconductor substrate.
  • Second metal can also pass above first metal regions covered by an insulation layer and provide a jumper between remote portions of first metal or remote portions of the semiconductor substrate.

Abstract

A structure and method for forming a semicustom integrated circuit in which customization can be performed using only a single masking step. Vias (12) in an insulation layer between first and second metal are made larger than first metal lines (11-1, 11-2, 11-3, 11-4) so that after deposition of second metal (13), a final patterning etch can remove not only portions of the second metal (13) to leave interconnect lines (13-1, 13-2, 13-3, 13-4) but can also remove second metal within any exposed vias and additionally remove first metal (11-3) in order to disconnect selected portions (11-2, 11-4) of first metal lines. In order for the final etch step not to remove portions of the substrate, an extra step of planarizing the insulation layer between first and second metal is provided. The large vias provided by the structure and method also allow for shrinking the size of first and second metal lines and thus shrinking the design rules for the entire semiconductor structure.

Description

1 GATE ARRAY STRUCTURE AND PROCESS TO ALLOW
2 OPTIONING AT SECOND METAL MASK ONLY
3 4
5 Field of the Invention
6 This invention relates to a process and structure for
7 forming metallization in a semiconductor structure. More
8 particularly, it relates to forming metallization above
9 semiconductor gate arrays so that custom circuits can be 10 completed in less time.
11
12 Background
-13 Gate arrays are arrays of semiconductor circuit elements
14 formed in the substrate of a semiconductor device according
15 to several standard designs usually up to the point where
16 electrical interconnects are fabricated. The electrical
17 interconnects are applied according to a custom pattern to
18 cause the resulting integrated circuit to perform a particu- 1-) lar desired function. The electrical interconnects usually
20 comprise two layers of metal (or sometimes metal suicide
21 for the first layer) lines, with vias formed between the two
22 layers to connect the two layers at selected locations.
23 The formation of the gate arrays in a semiconductor
24 substrate as a standard on-the-shelf item greatly reduces
25 the time required to produce a finished semicustom inte-
26 grated circuit after it has been ordered by the customer.
27 However, in current semicustom integrated circuit processing 8 techniques, three custom masking steps remain to be
29 performed after a custom integrated circuit is ordered.
30 These three steps are to deposit and pattern the first layer
31 of metal, to deposit a layer of insulation and pattern the
32 vias (openings in the insulation above the first layer of
33 metal), and to deposit and pattern a second layer of metal,
34 thus completing the interconnections to form the integrated 5 circuit. A final passivation layer is usually applied and 6 patterned for protection from the elements. 7 8 SUMMARY The structure and process of this invention allow for applying the first layer of metal, and patterning it with a universal (usable for many custom circuits) first layer mask, depositing the dielectric and patterning this with a universal via mask, and depositing the second layer of metal, all as part of the standard portion of producing a gate array integrated circuit. Custom masking steps to complete a circuit are then required only for patterning the second layer of metal. As a novel feature of this invention, the step of patterning the second layer of metal also selectively opens connections in the first layer of metal, thus producing the intended circuit function. The structure and method of this invention decrease the time and number of custom steps remaining to complete the integrated circuit after it is ordered in comparison to a standard gate array metallization process. The cost of manufacture is also significantly reduced because only one custom mask is required. The structure and process of this invention also have a larger tolerance for alignment error in the relative locations of the first metal layer lines, the vias and the second metal layer lines. in contrast to the prior art, by making vias wider than the lines which they will connect, and by planarizing the insulation layer deposited on the first metal before forming the vias, the step of etching after patterning and depositing second metal removes not only the second metal from unwanted areas but also removes second metal extending into vias located beneath exposed second metal and further removes the first metal located beneath these exposed vias. It is necessary that the vias be wider than the first layer metal lines in order for etching of second metal after patterning to result in also cleanly cutting the first layer metal lines beneath the exposed vias. However, when forming vias larger than the metal lines beneath them, extra precautions must be taken to avoid etching the silicon substrate adjacent to the metal lines and beneath the vias 1 when these large vias are being etched. Planarizing the
2 dielectric layer deposited on the first metal layer allows
3 for a controlled via etch down to the first metal without
4 exposing the substrate. With this invention, a standard -> first metal pattern having excess interconnections can be *■"* manufactured, and unnecessary first metal interconnections cut during the second metal patterning step to form a
8 circuit performing the desired logic function.
9 A preferred standard layout provides first layer metal 1*-) everywhere it is likely to be needed in any of many possible H circuit designs. A preferred standard layout also provides •-•2 oversized vias above first layer metal everywhere it is
■-■3 likely that first metal lines will have to be cut for any of
14 many circuit designs. Then a single custom mask can pattern
15 second metal and also provide for cutting first metal where --■6 necessary.
17 As another feature of this invention, first and second
18 metal are of the same material or of materials which can be
19 etched with the same etchant. A preferred embodiment uses
20 aluminum or an aluminum alloy. Alternatively two different
21 materials can be used for first and second layer
22 interconnects and the two materials etched sequentially with
2 sequential etchants.
24 As another feature of this invention, if it is desirable
2 to protect certain portions of first layer metal over which
26 vias will be placed for second layer contact, but where it 27 is not desired that first layer lines be cut, a layer of a 28 barrier metal which responds differently to the etchant used 29 for etching first layer metal can be placed over these 30 portions of first layer metal so that etching the second
31 layer metal will not also etch the first layer metal beneath
32 the barrier metal. Providing this barrier metal allows oversized vias.
34 This has the advantage that the lines of first layer metal *-*••-■ can be made smaller because alignment error tolerance can be
36 provided by the vias instead of the first metal lines.
37 Second metal can likewise be made smaller. This means that
38 the entire device can be scaled smaller. Thus the structure - A -
1 and method of this invention result not only in faster turn-
2 around time between order and shipment, but a more compact
3 device allowing for a more complex integrated circuit on a
4 die of a given size. 5
6 BRIEF DESCRIPTION OF THE DRAWINGS
7 Figs, la and lb show in plan and side views a first
8 metal interconnect pattern above a gate array substrate
9 formed using the teachings of this invention.
10 Fig. 2 shows the structure of Fig. lb with the addition
I--- of an insulation layer.
12 Fig. 3 shows the structure of Fig. 2 with the addition
■--3 of a layer of photoresist.
14 Fig. 4a shows the structure of Fig. 3 planarized to the
15 level of first metal.
■-•6 Fig. 4b shows the structure of Fig. 4a with a dielectric
17 layer added.
18 Figs. 5a and 5b show plan and cross-sectional views of
1 the structure of Fig. 4 in which the dielectric layer of
20 Fig. 4b has been patterned to form vias.
21 Fig. 6 shows the structure of Fig. 5b with the addition
22 of a second layer of metal.
23 Fig. 7 shows the structure of Fig. 6 to which a custom
2 layer of photoresist has been applied and patterned.
25 Figs. 8a and 8b show the structure of Fig. 7 in which
26 layers of first and second metal are removed where not
27 covered by photoresist.
28 Fig. 9 shows the structure of Fig. 8b to which a final
29 insulation layer has been applied.
30 Fig. 10 shows the side view of a structure similar to
31 that of Fig. 9 in which a layer of barrier metal has been
32 applied and patterned over the insulation and the exposed
33 first layer metal.
34 Figs, lla-lle show plan view layouts of vias and
35 interconnects which can be made using the teachings of this
36 invention. 37
38 DETAILED DESCRIPTION Figs, la and lb show respectively a top view and a cross sectional view, the cross section of Fig. lb taken along line A-A of Fig. la, which shows a first metallization layer deposited on a gate array substrate. The same numerical designations represent the same elements throughout the description and figures. The layout shown in Fig. la is commonly used for forming CMOS structures having groups of four transistors useful for implementing AND, OR, NAND, NOR and other logic functions. Fig. lb shows P-type substrate 51, which has formed therein N-type well 51a. Before formation of metallization layer 53, an oxide insulation layer 52 will have been formed on the surface of the substrate, and gates such as gate 24 (Fig. la) will have been formed, patterned, and used to form self- aligned source regions (not shown in the Fig. lb cross section), P+ drain region 51b in well 51a and N+ drain region 51c in substrate 51. At the point in the process represented by Fig. lb, metallization layer 53 (first metal) has been deposited on this patterned oxidation layer, making source and drain region contacts at locations such as 53a, 53b, 53c, and 53d, and has been patterned to produce metal interconnects. Oxide regions 52a and 52c are thus exposed. A single gate, such as gate 24 shown in Fig. la controls adjacent N-channel and P-channel transistors. The N-channel transistor has drain contacts 53c, 53d. The P-channel transistor has drain contacts 53a, 53b. In the example of Fig. la, polycrystalline silicon gate 24 controls electron flow through two substrate channels, for example between the source region located beneath contact 53e and the drain region located beneath contact 53d. Each source, drain, channel and gate comprise one MOS transistor. The particular logic function depends upon the patterning of first and second metal connections. According to the present invention, custom patterning of both first and second metal to achieve a wide variety of logic functions can be performed in a single step, as will be described. 1 Next,' in order to planarize metallization layer 53, a
2 layer of insulation 54' is applied (see Fig. 2), to the
3 surface of the structure shown in Figure lb. Then, a layer
4 of photoresist 55 is applied to insulation layer 54 as shown
5 in Fig. 3.
"->* As shown in Fig. 4, photoresist layer 55 and insulation layer 54 are etched by a process which removes photoresist 55
8 at substantially the same rate as it removes insulation layer
9 54. Etching is continued until upper portion 54a of 0 insulation layer 54 is removed and first metallization layer 1 53 is exposed. The etch may be ended at an earlier point
12 when all photoresist is removed, thus producing a flat top
13 layer, or, preferably ended at this later point when first
14 metallization layer 53 is exposed. Stopping when first metal
15 is exposed is advantageous because it allows for redepositing *5 a layer of dielectric to a predictable thickness above first 17 metal. In either case the upper surface is flat. i8 Importantly, as Fig. 4a shows, substrate 51 is nowhere
19 exposed. Then, as shown in Fig. 4b, dielectric is again
20 deposited over the entire surface as layer 56. 1 Alternatively, to achieve planarization of insulation
22 layer 54 a layer of polyimide may be applied to insulation
23 layer 54 instead of applying photoresist 55. Polyimide is
24 self-leveling and avoids the step of having to remove
2 photoresist plus plasma oxide and then redeposit plasma
26 oxide. However, polyimide will absorb moisture if left
27 exposed and thus may need to be passivated with a layer of
28 plasma oxide.
29 As a further alternative, using spin-on glass to form 30 insulation layer 54 can produce leveling. Thus spin-on glass allows insulation layer 54 to be planarized directly. In the
32 past, spin-on glass has not been preferred because the
33 impurity level in available spin-on glass has not been
34 sufficiently high.
35 Because of the planarization step the dielectric at
36 locations 54a and 54b below the top of first metal 53 is 7 etched away very little. 38 This planarization step is an important feature of the invention. Without it, providing the oversized vias of this invention would result in etching the silicon substrate 51 at roughly the same time as the top surface of first metal 53 becomes exposed during via etch. Fig. 5a shows a plan view and Fig. 5b shows a cross- sectional view in which insulation layer 56 has been deposited and vias 56a, 56b, 56c, 56d and 56e have been formed at all locations where it may later be desirable to connect second metal to first metal or to break contact in the earlier formed first metal. Fig. 5b is a cross-sectional view of Fig. 5a taken along the line A-A. As shown in Fig. 5b, insulation layer 56 is deposited onto the top of the planarized layer comprising metallization layer 53 and insulation layer 54. Passivation layer 56 is then patterned to form vias such as 56a, 56b, 56c, 56d and 56e. Next, as shown in Fig. 6, second metallization layer 57 is deposited onto the top surface of the semiconductor wafer forming contact regions 57a, 57b, 57c, 57d and 57e in the vias which were formed in insulation layer 56. All these steps are part of forming a universal semi- conductor structure which can be used for multiple custom circuits, depending upon the mask used for patterning of second metal layer 57. Figs. 7, 8a, 8b, and 9 show the final customization steps necessary to produce the circuit specified by a customer. As shown in Fig. 7, photoresist layer 58 is deposited onto second metal layer 57 and patterned into regions 58a, 58b, 58c, and 58d using the single custom mask which can be used with this invention. This patterning exposes locations at which second and also some first metal are to be removed. As shown in Fig. 8b, these exposed portions are removed. The remaining photoresist is also removed. A plasma or reactive ion etching process can be selected to avoid undercutting of first and second metal. n Fig. 8b, portions of second metal 57, some of the second metal contacts, and portions of the first metal have been removed. The resulting circuit is shown in plan view in Fig. 8a. " As shown in Fig. 9, after removal of unwanted portions of first and second metal, a final passivation layer 59 is formed. As shown in Fig. 8b, the patterning step has resulted in the removal of second metal region 57g (shown in Fig. 7), thereby severing the connection between second metal regions 57f and 57e. The patterning has also resulted in removal of second metal contact regions 57c part of second metal contact regions 57b and 57d, plus the further removal of first metal regions 53h, 53 , and 53ι (see Fig. 8b). Therefore connections have been severed between second metal region 57a and first metal region 53i. Connections have not been severed between second metal region 57a and first metal region 53a, in spite of the fact that no photoresist protected second metal above first metal region 53a. This is because vias in insulation layer 56 were not formed above first metal region 53a. Thus the structure and method of this invention allow for both flexibility in the design of a semicustom circuit and the speed and low cost of a single custom masking step, resulting in low cost and fast delivery to the customer. The single masking and patterning step shown in Fig. 7 thus results in the customization of an entire circuit. In the prior art, typically three custom masking/patterning steps were required for producing a semicustom circuit, one for patterning first metal, one for patterning vias, and one for patterning second metal. By contrast, with the method of this invention, only the single custom patterning step after depositing second metal is required to form a semicustom circuit. The planarization step applied after patterning of first metal and insulation of the patterned regions (for example, regions 54a and 54b) means that vias for second metal contact need not be smaller than the surrounding metal lines. Therefore vias can serve the dual function of allowing for contact between first and second metal and of breaking the contact between adjacent first metal regions. As another feature of this invention, given there is no requirement that vias be contained within the bounds of the first metal lines, first metal lines can be made narrower than under prior art design rules while maintaining sufficient alignment error tolerance for vias. A prior art device which does not planarize the insulation layer above first metal must keep the vias from overlapping first metal because without planarizing an etch step would etch or at least expose the silicon substrate. Design rules may require above the first metal lines a 1-micron space on each side of a via to allow for alignment error and avoid having the vias overhang the first-metal line. Thus for a 3-micron via the prior art line width must be 5 microns. Eliminating the prior art requirement that vias not overhang first metal allows the first metal to be at least 2 microns smaller, and if vias are permitted (or desired) to overhang first metal, the first metal lines can be shrunk, in our example, from a 5-micron width to a one- or two-micron width. Thus the design rules can be remarkably shrunk and the overall device made remarkably smaller. This same principle will apply if in the future tolerances become tighter and line widths can e further reduced. i some cases it may be desirable to provide contact between first and second metals through a via, but to allow the contact between first and second metal to be broken without allowing the first metal line to be broken. in this case, after forming and patterning the first metal layer, and forming and patterning the insulation layer above it, a thin layer of a barrier metal is deposited and patterned before the second metal layer is deposited. The barrier metal formation increases the number of steps needed to form the structure, however these extra steps occur during formation of the universal structure and do not lengthen the customization process. The number of custom masks needed remains one. The barrier metal is selected to be resistant to an etchant used to etch the first and second metal lines. The barrier metal is patterned to be located above vias in the insulation layer where it is desirable not to break, the first metal layer beneath the vias. Fig. 10 shows a side view of a structure in which a barrier metal has been used. As shown in Fig. 10, two regions 61 and 62 of first metal have been formed. Planarization oxide layer 63 has been followed by the formation and patterning of oxide layer 64. After formation of these oxide layers, a layer 65 of barrier metal was formed and patterned. As shown in Fig. 10, barrier metal region 65 is larger than the first metal regions 61a and 61b it must protect. Thus, alignment is not critical. In customizing the structure of Fig. 10, the goal is to leave region 66b of second metal connecting first metal region 61a to first metal region 62a, also to sever the connection from second metal region 66a to first metal regions 61a or 61b and to sever the connection between first metal regions 62a and 62b but "not to sever the connection between regions 61a and 61b. As shown in Fig. 10, barrier metal 65 has been patterned to cover first metal regions 61a and 61b but not to cover first metal regions 62a and 62b. Before custom patterning, the second metal layer contacts first metal regions 61a and 61b through barrier metal 65 and via 68a. The second metal layer contacts regions 62a and 62b through via 68b. The single custom mask patterns the photoresist to cause openings to be etched in second metal at regions 69a and 69b» Etching of opening 69a is stopped by barrier metal 65 while etching of opening 69b proceeds in region 69c until regions 62a and 62b are separated. At this point in the process, barrier metal layer 65 connects second metal region 66a to first metal regions 61a and 61b. A subsequent etch of this barrier metal (not requiring further masking and patterning) removes the exposed portions of barrier metal 65, thus severing connection from second metal region 66a to first metal regions 61a and 61b. Tolerance in alignment of the barrier metal is not critical because the barrier metal region may be made sufficiently larger than the via it is to cover. Also, providing the barrier metal does not further restrict alignment tolerances for the custom mask. Opening 69a between second metal regions 66a and 66b need be only wide enough to assure separation between these adjacent second metal regions. Alignment between the custom mask and the cell to be customized must only be sufficient that region 66b contacts region 61a and 62a, that the first metal gap between regions 62a and 62b is sufficient for reliable separation, and that region 66a is separated from region 61b. A barrier metal which has been successfully used with a silicon substrate, silicon oxide insulation, and aluminum first and second metal is titanium-tungsten. When this combination of materials is used, the titanium-tungsten barrier is placed above rather than below the insulation layer because the fluorine based etchants preferably used to form vias in the oxide would also remove the titanium- tungsten. Figs, lla-lle show some geometries of first metal, via, and second metal patterning to achieve various connection patterns with the single custom mask of this invention. In Fig. lib, first metal layer 11 was patterned after deposition to leave a cross-shaped pattern as indicated by outline 11-3. After forming an insulation layer above the patterned first metal cross-shaped pattern, via 12 is patterned into the insulation layer, thus exposing the center of first metal cross 11-3. Deposition of second metal 13 onto the upper surface of the wafer causes second metal 13 to contact first metal cross 11-3 within the outline of via 12. Fig. lib shows the remaining structure after patterning of second metal 13, in which only an L-shaped portion of second metal 13 remains. In region 12-1, the removal of second metal 13 where via 12 is located has resulted in removal of first metal 11 from the original cross-shaped first metal pattern 11-3, thus severing electrical connection between first metal region 11-1 and first metal regions 11-2 and 11-4. The presence of the insulation layer above first metal regions 11-1 and 11-2 prevents the subsequent removal of second metal 13 from also removing first metal regions 11-1 and 11-2. In region 13-1, second metal remains above but separated by insulation layer 12 from first metal. In region 13-2, which is within via 12, second metal 13 is in contact with first metal 11. Thus, it can be seen that the second metal pattern selected in Fig. lib has resulted in retaining the electrical connection between first metal regions 11-4 and 11-5 while severing connections to first metal regions 11-1 and 11-2. Other patterns are shown in Figs. 11a, lie, lid, and lie. In Fig. lid, a first metal line over which a via is located has been severed during second metal patterning. In Fig. lie, first metal region 15-2 has been severed from first metal region 15-3 while remaining connected to second metal region 15-1. In Fig. 11a, second metal region 17-1 connects regions 16-1 and 16-3 to each other but leaves region 16-2 disconnected. Of course many other geometries will be obvious to those skilled in the art. Second metal, as used with this invention, can also pass above first metal regions covered by an insulation layer and provide a jumper between remote portions of first metal or remote portions of the semiconductor substrate. Thus it is clear that great flexibility in customizing circuits can be achieved through the single patterning step used with this invention. This provides a full and complete disclosure of the invention. Additional embodiments incorporating the teachings of this invention will become obvious to those skilled in the art in light of this disclosure. In particular, it will be obvious that an embodiment including a third layer of metal can be formed so that a single patterning step performed after deposition of the third layer of metal can result in a semicustom circuit having three metal layers. It will also be obvious that subsequent custom steps can be performed after performing the single custom step which removes portions of more than one layer of metal. Such variations are intended to fall within the scope of this invention.

Claims

1. A semiconductor structure comprising: a semiconductor substrate having semiconductive structures formed therein; a first insulation layer formed on said substrate and patterned to expose portions of said substrate; a first conductive layer formed on said first insulation layer and said exposed portions of said substrate, and patterned to remove portions of said firs conductive layer leaving first conductive lines having a first line width; a second insulation layer formed above said first conductive layer and patterned to form vias, at least some of which are at least as wide as said first line width, thereby exposing the full width of portions of said first conductive lines; and a second conductive layer formed on said second insulation layer; whereby subsequent patterning of said second conductive layer may remove portions of both said second conductive layer and said first conductive layer, thereby patterning said second conductive layer, breaking selected connections between said second conductive layer and said first conductive layer, and breaking connections between selected portions of said first conductive layer.
2. A semiconductor structure as in Claim 1 in which said vias are wider than said first conductive lines, thereby allowing tolerance in alignment between said vias and said first conductive lines.
3. A semiconductor structure as in Claim 1 further comprising a barrier conductive layer formed above said first conductive layer.
4. A semiconductor structure as in Claim 3 in which said barrier conductive layer is patterned to cause said subsequent patterning of said second conductive layer to leave intact portions of said first metal located beneath said barrier metal.
5. A semiconductor structure as in Claim 3 in which said barrier conductive layer is formed above said second insulation layer.
6. A semiconductor structure as in Claim 5 in which said substrate is silicon, said insulation layers are silicon oxide, said first and second conductive layers are aluminum and said barrier conductive layer is titanium-tungsten.
7. A method for forming a semiconductor structure comprising: forming a semiconductor substrate having semiconductive structures formed therein; forming on said semiconductor substrate a first insulation layer; patterning said first insulation layer to expose portions of said substrate; forming on said first insulation layer and said exposed portions of said substrate a first conductive layer; patterning said first conductive layer to leave first conductive lines having a first line width and leaving contacts contacting said substrate; forming a second insulation layer above said first conductive lines and said first insulation layer; planarizing said second insulation layer to prevent dips above regions where said first conductive layer has been removed; patterning said second insulation layer to form vias, at least some of which are at least as wide as said first line width, thereby exposing the full width of portions of said first conductive lines; and forming a second conductive layer on said second insulation layer and said exposed portions of said first conductive lines; whereby subsequent patterning of said second conductive layer may remove portions of both said second conductive layer and said first conductive layer, thereb breaking electrical connection between selected portions of said second conductive layer, selected connections between said second and first conductive layers, and selected connections between selected portions of said first conductive layer.
8. A method for forming a semiconductor structure as i Claim 7 further comprising the step after forming said secon conductive layer of patterning said semiconductor structure to remove portions of said first and second conductive layers, thereby forming a semicustom integrated circuit.
9. A method for forming a semiconductor structure as i Claim 7 in which said vias are wider than said first conductive lines, thereby allowing tolerance in alignment between said vias and said first conductive lines.
10. A method for forming a semiconductor structure as i Claim 7 further comprising the step of forming a barrier metal layer between said second conductive layer and said second insulation layer.
11. A method for forming a semiconductor structure as i Claim 10 further comprising the step of patterning said barrier metal layer to expose portions of said first conductive layer.
12. A semiconductor gate array structure for forming a semicustom circuit comprising: a semiconductor substrate; a first metal layer formed above said semiconductor substrate, contacting said substrate in selected locations, and patterned to form first metal lines in all locations where one portion of said first metal layer must be able to be connected to another portion of said first metal layer in any semicustom circuit; a second metal layer formed above said first metal layer; and an insulation layer between said first metal layer and said second metal layer having vias patterned above all portions of said first metal lines which must be able to be disconnected to form any semicustom circuit and all portions of first layer metal which must be connected to second layer metal, said vias being large enough that a process for r-emoving metal in said second metal layer located within said vias also results in severing said first metal lines at locations beneath said vias; whereby a single mask can serve to pattern both said first metal and said second metal layers in order to produce said semicustom circuit.
13. A semiconductor gate array structure as in Claim 12 further comprising a planarizing insulation layer located adjacent said patterned^first metal layer such that the top surface of said patterned first metal layer and the top surface of said planarizing insulation layer are approximately coplanar.
14. A semiconductor gate array structure for forming a semicustom circuit comprising; a semiconductor substrate; a first metal layer formed above said semiconductor substrate, contacting said substrate in selected locations, and patterned in a selected pattern; a second metal layer formed above said first metal layer and patterned to form second metal lines in all locations where one portion of said second metal layer must be able to be connected to another portion of said second metal layer in any semicustom circuit; a first insulation layer between said first metal layer and said second metal layer having vias patterned to connect portions of said first metal layer to said second metal layer; a third metal layer formed above said second metal layer; and a second insulation layer between said second metal layer and said third metal layer having vias above all portions of said second metal lines which must be able t be disconnected to form any semicustom circuit, said via being large enough that a process for removing metal fro said third metal layer at locations within said vias als results in severing said second metal lines at locations beneath said vias; whereby a single mask can serve to pattern both sai second and third metal layers in order to produce said semicustom circuit.
15. A semiconductor gate array structure as in Claim 14 further comprising: a first planarizing insulation layer located adjacent said patterned first metal layer such that the top surface of said patterned first metal layer and the top surface of said first planarizing insulation layer are approximately coplanar, and a second planarizing insulation layer located adjacent said patterned second metal layer such that the top surface of said patterned second metal layer and the top surface of said second planarizing insulation layer are approximately coplanar.
EP19890904937 1988-03-31 1989-03-29 Gate array structure and process to allow optioning at second metal mask only Withdrawn EP0403571A4 (en)

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US3877051A (en) * 1972-10-18 1975-04-08 Ibm Multilayer insulation integrated circuit structure
JPS6018143B2 (en) * 1976-12-23 1985-05-09 富士通株式会社 Manufacturing method of semiconductor integrated circuit
US4172004A (en) * 1977-10-20 1979-10-23 International Business Machines Corporation Method for forming dense dry etched multi-level metallurgy with non-overlapped vias
DE3066941D1 (en) * 1979-05-24 1984-04-19 Fujitsu Ltd Masterslice semiconductor device and method of producing it
JPS57177553A (en) * 1981-04-24 1982-11-01 Toshiba Corp Semiconductor
JPS5837933A (en) * 1981-08-31 1983-03-05 Hitachi Ltd Semiconductor integrated circuit device
IL82113A (en) * 1987-04-05 1992-08-18 Zvi Orbach Fabrication of customized integrated circuits

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