JP3074603B2 - Fading simulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulated propagation signal obtained by performing delay processing, fading addition processing and attenuation processing on a predetermined signal, and transmitting the processed signal through a propagation path whose propagation characteristic changes. The present invention relates to a technique for preventing instantaneous interruption of a signal when a delay characteristic or a fading characteristic is changed in a fading simulator that outputs a signal.

[0002]

2. Description of the Related Art In a system for performing communication by radio waves, it is necessary to check the operation of a wireless device such as a terminal, a base station, or a test device for testing them, assuming various propagation paths.

[0003] In particular, in the case of a mobile station, the propagation characteristics of a propagation path vary greatly with time. The factors of the fluctuation of the propagation characteristics are multipath propagation time difference, fading fluctuation, Doppler shift fluctuation, and attenuation fluctuation due to a shield or the like.To check the operation of the wireless device, delay processing, addition of fading to a predetermined signal are required. It is necessary to perform the processing and the attenuation processing, and to provide the signal subjected to these processings to the wireless device as a simulated propagation signal.

FIG. 6 shows a multipath type fading simulator 10 generally used for such a purpose.
Is shown.

The fading simulator 10 receives a predetermined signal (stable analog signal used for communication) output from the signal generator 1 through an input terminal 10a, branches the signal, and branches the signal into two propagation paths. Simulation circuits 11 and 12
To enter.

The propagation path simulating circuits 11 and 12 are provided with a delay circuit 13 for delaying a predetermined signal, a fading addition circuit 17 for giving a fading variation and a Doppler shift to the signal output from the delay circuit 13, and a signal output from the fading addition circuit 17. It comprises an attenuation circuit 21 for attenuating a signal.

The delay circuit 13 includes an A / D converter 14 for converting an input signal into a digital signal, and a shift register 15 for receiving an output of the A / D converter 14 and generating a predetermined delay.
And a D / A converter 16 that converts an output from the shift register 15 into an analog signal. The D / A converter 16 changes the number of stages of the shift register 15 by a control signal from a control unit (not shown) to delay a predetermined signal. Change the time.

The fading addition circuit 17 comprises a noise generator 18, a D / A converter 19 and a quadrature modulator 20, and converts a digital white noise signal output from the noise generator 18 into a D / A converter. The signal is converted into an analog noise signal by 19 and output to the quadrature modulator 20.

The quadrature modulator 20 modulates the amplitude and phase of a predetermined signal with the noise signal output from the D / A converter 19 to perform fading fluctuation and Doppler shift.

The fading addition circuit 17 changes a fading fluctuation amount and a Doppler shift amount with respect to a predetermined signal by changing a program of the noise generator 18 according to a control signal from the control unit.

The attenuation circuit 21 changes the amount of attenuation with respect to the signal output from the fading addition circuit 17 in accordance with a control signal from the control unit.

The outputs of the two propagation path simulating circuits 11 and 12 configured as described above are equivalent to radio waves emitted from the same transmitter and passing through two different propagation paths. By inputting the synthesized signal from the output terminal 10b to the wireless device 2 to be evaluated, the operation of the wireless device 2 can be checked in an actual use state.

[0013]

However, in the above-described conventional fading simulator, the program of the noise generator must be changed every time the amount of fading fluctuation or the like is changed. Will occur.

[0014]

An object of the present invention is to provide a fading simulator which solves these problems.

[0016]

To achieve the above object, a fading simulator according to claim 1 of the present invention comprises:
A delay circuit that delays the input predetermined signal, a fading addition circuit that receives the output of the delay circuit and adds a fading variation, and an attenuation circuit that attenuates the output of the fading addition circuit. A fading simulator that outputs a signal subjected to each of these processes as a simulated propagation signal propagated through a propagation path whose propagation characteristic changes, wherein the fading addition circuit includes a noise generator (41) that generates a digital noise signal. An oversampling means (42) for oversampling the noise signal to shift an image component of the noise signal to a higher frequency side; a variable frequency clock generator (44) for outputting a clock signal; The processed noise signal is analogized in synchronization with the clock signal from the clock generator. D / A converter for converting the No. (4
3) a low-pass filter (45) for removing the image component from the noise signal converted into an analog signal by the D / A converter; and an output signal of the delay circuit based on an output signal of the low-pass filter. (47) that modulates the signal to give fading fluctuation and Doppler shift
Control means (6) for variably controlling the clock frequency of the clock generator to arbitrarily vary the amount of fading fluctuation and the amount of Doppler shift with respect to the output signal of the delay circuit.
0).

According to a second aspect of the present invention, in the fading simulator according to the first aspect, the attenuating circuit performs an attenuating process on an output signal of the oversampling means, thereby providing a delay circuit. Is indirectly attenuated.

A fading simulator according to a third aspect of the present invention includes a delay circuit that performs a delay process on an input predetermined signal, a fading addition circuit that receives an output of the delay circuit and adds a fading variation, An attenuating circuit for attenuating the output of the fading addition circuit, wherein the fading simulator outputs the signal subjected to each of these processes as a simulated propagation signal propagated on a propagation path whose propagation characteristic changes. Is a noise generator (4) that generates a digital noise signal.
1) a variable frequency clock generator (44) for outputting a clock signal; and a D / A converter (43) for converting the noise signal into an analog signal in synchronization with the clock signal from the clock generator. The high-frequency cutoff frequency changes according to the frequency of the clock signal from the clock generator,
A band variable filter (71) for removing an image component contained in the noise signal output from the D / A converter, and modulating an output signal of the delay circuit with an output signal of the band variable filter to reduce fading fluctuation. A modulator (47) for giving a Doppler shift, and a control means (60) for variably controlling a clock frequency of the clock generator to arbitrarily change a fading fluctuation amount and a Doppler shift amount with respect to an output signal of the delay circuit. Have.

A fading simulator according to a fourth aspect of the present invention is the fading simulator according to the third aspect, wherein the attenuation circuit performs an attenuation process on a noise signal output from the noise generator. The output signal of the delay circuit is indirectly attenuated.

[0020]

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows Embodiment 2 of the present invention.
1 shows a configuration of a path-type fading simulator 30.

The present invention also operates with a one-pass fading simulator. In the case of the two-pass type, for example, it is possible to test two routes, that is, the direct propagation route between the stations and the route of the reflected wave. Become. As a two-pass type, two propagation routes of a reflected wave and another reflected wave can be tested. Further, the test can be performed by increasing the number of passes to three passes, four passes,.... Since the principle is the same in each case, here 2
Explanation will be given using a path type.

In FIG. 1, a predetermined signal output from a signal generator 1 is input to an A / D converter 31 via an input terminal 30a of a fading simulator 30.

The A / D converter 31 samples a predetermined signal at a cycle synchronized with the clock signal Ck and converts it into a digital signal.

The predetermined signal converted into a digital signal by the A / D converter 31 is branched and input to two propagation path simulation circuits 32 and 33.

The propagation path simulating circuits 32 and 33 have the same configuration, and include a delay circuit 35 and a fading addition circuit 4 respectively.
0, a D / A converter 50 and an attenuation circuit 51.

The delay circuit 35 constitutes a delay circuit of this embodiment together with a control unit 60 to be described later, and comprises a memory 36, a write circuit 37 and a read circuit 38. The memory 36 is formed by a dual port RAM having independent input / output ports, which can independently designate a write address and a read address.

The write circuit 37 specifies a write address Aw for the memory 36 in a predetermined order in synchronization with the clock signal Ck, and stores the digital signal output from the A / D converter 31 in the memory 36.

The read circuit 38 sequentially specifies the read address Ar for the memory in synchronization with the clock signal Ck and reads the digital signal stored in the memory 36.

Therefore, the digital signal written in the memory 36 is composed of a write address Aw and a read address Ar.
And is read out with a delay of a time obtained by multiplying the difference ΔA from the period by the cycle of the clock signal Ck. Note that the read circuit 38 varies the read address Ar so that ΔA changes according to a delay control signal from the control unit 60 described later.

The fading addition circuit 40 constitutes a fading addition circuit of this embodiment together with a control section 60 described later, and oversamples a digital white noise signal output from a noise generator 41 constituted by a DSP. Input to the circuit 42.

The oversampling circuit 42 determines that the noise signal sequence output from the noise generator 41 is [N ₁ , N
_2, ..., N _k, if ...], this [N _1, 0,
_{..., 0, N 2, 0} , ..., 0, ..., N k, 0, ..., 0,
..], Each signal is interpolated with a plurality of (M-1) 0 data and passed through a digital filter, thereby increasing only the image component without changing the signal component itself of the noise signal. Shift to the area. In this manner, a method of interpolating and filtering between signals with M-1 0 data is referred to as M-times oversampling.

More specifically, the noise generator 41
When the D / A conversion is performed on the noise signal output from at the speed of the frequency fs of the clock generator 44 without performing the oversampling process, as shown in FIG.
The image component I ₁ whose frequency is closest to the frequency f
It occurs around s. Therefore, this image component I
A low-pass filter for removing ₁ is required.

The high-frequency cutoff frequency f of the low-pass filter
a is usually set to approximately 1/2 of the frequency fs, as shown by the characteristic F in FIG. 2, so that the maximum value of the frequency fs is set to fsm.
Then, the band of the fundamental component R of the noise signal when the frequency is fsm and the high cutoff frequency fa of the filter are set to fsm / 2.
If set, when narrowing the bandwidth of the basic component R by varying the frequency fs, the image component I ₁ will pass through the low-pass filter.

On the other hand, if the noise signal output from the noise generator 41 is subjected to M-times oversampling processing as in this embodiment, the basic component R of the noise signal is obtained as shown in FIG. image component I ₂ is generated around the frequency M · fs most frequency is close relative. Accordingly, even when the high-frequency cutoff frequency of the low-pass filter 45 described later is fixed, the band of the fundamental component R of the noise signal can be substantially changed from fa / 2 to fsm by varying the frequency fs.
/ 2.

The oversampled noise signal is converted into an analog signal by the D / A converter 43. The D / A converter 43 converts the noise signal into an analog signal in synchronization with the clock signal Cv from the clock generator 44, and outputs the analog signal to the low-pass filter 45.

The clock generator 44 includes a control unit 6 described later.
The frequency of the clock signal Cv is varied according to the noise control signal from 0 to vary the band of the basic component of the noise signal,
Change the noise signal waveform.

The output signal of the low-pass filter 45 is A /
The signal is converted into a digital signal by the D converter 46 and output to the quadrature modulator 47. The A / D converter 46 performs digital conversion in synchronization with the clock signal Ck.

The quadrature modulator 47 converts the digital signal read from the memory 36 of the delay circuit 35 into an A / D converter 4
The signal is modulated by the digital noise signal output from 6 to add fading fluctuation and Doppler shift.

The signal output from the quadrature modulator 47 is D
The signal is converted into an analog signal by the / A converter 50 and input to the attenuation circuit 51.

The attenuation circuit 51 changes the amount of attenuation with respect to the signal output from the quadrature modulator 47 according to the attenuation control signal from the control unit 60.

Each attenuation circuit 5 of the propagation path simulation circuits 32 and 33
The signal output from 1 is input to the synthesis circuit 52 and synthesized, and the synthesized signal is output from the output terminal 30b to the wireless device 2 to be evaluated.

The control unit 60 includes the propagation path simulation circuits 32 and 33
The delay control signal, the noise control signal, and the attenuation control signal for the delay circuit 35, the fading addition circuit 40, and the attenuation circuit 51 are continuously changed according to a preset variation pattern. In the case of a mobile station, a composite signal that fluctuates in the same manner as a received signal when a radio wave from a base station is received while moving is output to the wireless device 2.

As described above, the delay processing of the fading simulator 30 of the embodiment is performed by converting the predetermined signal converted into a digital signal by the A / D converter 31 into the memory 36 which can independently designate a write address and a read address. The addresses are stored in the order of addresses, which are sequentially read in a state where there is an address difference, and the difference between the read address and the write address is varied to vary the signal delay time.

Therefore, when the delay time changes, an accurate delay time corresponding to the address difference can be immediately provided.

The fading addition process of the fading simulator 30 is performed by oversampling a band-fixed noise signal at a fixed sampling rate output from the noise generator 41 by the DSP, and
A signal is converted into an analog signal, the image component is removed from the signal by a fixed low-pass filter 45, and the signal is input to a quadrature modulator 47. The signal output from the delay circuit 35 is subjected to fading fluctuation. And the Doppler shift, the clock frequency for the D / A converter 43 is changed, and the band of the noise signal is changed to change the fading fluctuation amount and the Doppler shift amount.

Therefore, a highly accurate noise signal can be obtained,
High-precision fading fluctuation and Doppler shift can be provided, and the band of the noise signal can be varied without changing the DSP program, so that instantaneous interruption of the signal does not occur.

[0048]

[Other Embodiments] In the fading addition processing of the above embodiment, the image frequency of a noise signal generated at the time of D / A conversion is shifted to a higher frequency side by performing oversampling processing on the noise signal. Although the image frequency is removed by a fixed low-pass filter, the noise signal output from the noise generator 41 is converted to a D / A converter 4 like a fading addition circuit 70 shown in FIG.
3 may be converted into an analog noise signal, and an image component included in the noise signal may be removed by a switched capacitor filter (hereinafter, referred to as SCF) 71.

The low-pass filter (LPF) 72 provided after the SCF 71 is for removing the clock signal Cv component from the output of the SCF 71.

The SCF 71 is a band variable filter element that limits the band of an input signal at a cutoff frequency corresponding to the frequency of the clock signal Cv. When used as a low-pass filter, the SCF 71 responds as the frequency of the clock signal Cv increases. The higher cutoff frequency shifts to the higher side.

Therefore, if the high-frequency cutoff frequency fb of the SCF 71 is set to a frequency slightly higher than the band of the fundamental component R of the noise signal, as shown by the characteristic G in FIG. When the frequency of the clock signal Cv is varied as shown in FIG. 4B, the high-frequency cutoff frequency fb of the SCF 71 also changes in the same direction, thereby removing the image component I of the noise signal and passing only its basic component R. Without interrupting the signal,
The fading fluctuation amount and the Doppler shift amount can be changed.

Although the SCF 71 is used here as a band variable filter, another band variable filter can be used as long as the high cutoff frequency can be varied according to the frequency of the clock signal of the D / A converter 43. Can also be used.

In the above embodiment, the present invention is applied to a two-pass type fading simulator having two propagation path simulating circuits. However, the present invention is applied to a three-path fading simulator or a propagation path simulating circuit. Can be similarly applied to a one-pass type fading simulator having only one.

In the above embodiment, the attenuation processing is directly performed on the signal on which the delay processing and the fading addition processing have been performed. For example, as shown in FIG. The oversampled noise signal is oversampled by an oversampling circuit 42, the oversampled noise signal is input to a digital type attenuating circuit 76 to be attenuated, and the attenuated signal is processed by a D / A converter 43. You may comprise so that it may convert into an analog signal.

When the attenuation circuit 76 is provided between the noise generator 41 and the oversampling circuit 42, the attenuation circuit operates in synchronization with the clock of the D / A converter 43. When the attenuating circuit 76 is provided between the oversampling circuit 42 and the D / A converter 43, the attenuation control and the variable control of the clock of the D / A converter 43 can be performed independently, and the attenuation process is performed. Can be performed without delay.

When an attenuating circuit is provided in the fading adding circuit as shown in FIG. 5, the output of the D / A converter 50 is synthesized by the synthesizing circuit 52 and given to the radio equipment 2.

[0057]

As described above, according to the first aspect of the present invention,
In the fading simulator, the digital noise signal output from the noise generator is oversampled, then D / A converted to an analog signal, and the image component is converted from this signal by a fixed-frequency low-pass filter. A predetermined signal is modulated by the noise signal from which the image component has been removed, and the frequency of the noise signal is varied by changing the clock frequency for the D / A converter to give fading fluctuation and Doppler shift to the predetermined signal. ing.

For this reason, fading fluctuation and Doppler shift with high precision can be given, and the band of the noise signal can be varied without changing the program, so that instantaneous interruption of the signal does not occur.

Further, in the fading simulator according to the third aspect of the present invention, the digital noise signal output from the noise generator is D / A converted and converted into an analog signal, and the image component is converted from this signal by a band variable filter. A predetermined signal is modulated by the noise signal from which the image component has been removed, and the frequency of the noise signal is varied by changing the clock frequency for the D / A converter to give fading fluctuation and Doppler shift to the predetermined signal. ing.

For this reason, a high-precision fading fluctuation and Doppler shift can be given, and the band of the noise signal can be varied without changing the program, so that instantaneous interruption of the signal does not occur.

[0060]

[0061]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram for explaining an operation of the embodiment;

FIG. 3 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a diagram for explaining the operation of another embodiment.

FIG. 5 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 6 is a block diagram showing the configuration of a conventional device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 30 fading simulator 31 A / D converter 32, 33 propagation path simulation circuit 35 delay circuit 36 memory 37 writing circuit 38 reading circuit 40 fading addition circuit 41 noise generator 42 oversampling circuit 43 D / A converter 44 clock generator 45 Low-pass filter 46 A / D converter 47 Quadrature modulator 50 D / A converter 51 Attenuation circuit 52 Synthesis circuit 60 Control unit

Continuation of the front page (56) References JP-A 1-254026 (JP, A) JP-A 57-14228 (JP, A) JP-A 8-265187 (JP, A) JP-A 58-75315 (JP JP-A-61-262313 (JP, A) JP-A-62-245717 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 31/00 G01R 29/00 H04B 3/04 H04B 7/005 H04B 3/46 H04B 17/00

Claims (4)

(57) [Claims] A delay circuit for delaying an input predetermined signal; a fading circuit for adding a fading variation in response to an output of the delay circuit; and an attenuation circuit for attenuating an output of the fading circuit. A fading simulator that outputs a signal subjected to each of these processes as a simulated propagation signal propagated on a propagation path whose propagation characteristic changes, wherein the fading addition circuit generates a digital noise signal. Tableware (41)
Oversampling means (42) for oversampling the noise signal to shift the image component of the noise signal to a higher frequency side; a variable frequency clock generator (44) for outputting a clock signal; A D / A converter (43) for converting the sampled noise signal into an analog signal in synchronization with the clock signal from the clock generator; and converting the noise signal converted into an analog signal by the D / A converter from the noise signal. A low-pass filter (45) for removing the image component; a modulator (47) for modulating an output signal of the delay circuit with an output signal of the low-pass filter to provide fading fluctuation and Doppler shift; By variably controlling the clock frequency of the clock generator,
A fading simulator comprising a control means (60) for arbitrarily varying a fading fluctuation amount and a Doppler shift amount with respect to an output signal of the delay circuit. 2. The apparatus according to claim 1, wherein said attenuation circuit indirectly attenuates an output signal of said delay circuit by performing an attenuation process on an output signal of said oversampling means. Fading simulator. 3. A delay circuit for delaying an input predetermined signal, a fading addition circuit for receiving an output of the delay circuit and adding a fading variation, and an attenuation for attenuating an output of the fading addition circuit. A fading simulator that outputs a signal subjected to each of these processes as a simulated propagation signal propagated on a propagation path whose propagation characteristic changes, wherein the fading addition circuit generates a digital noise signal. Tableware (41)
A variable frequency clock generator (44) that outputs a clock signal; and a D / A converter (4) that converts the noise signal into an analog signal in synchronization with the clock signal from the clock generator.
3) and a band variable filter (71) whose high cut-off frequency changes in accordance with the frequency of the clock signal from the clock generator and removes image components contained in the noise signal output from the D / A converter. ), A modulator (47) for modulating an output signal of the delay circuit with an output signal of the band variable filter to provide fading fluctuation and Doppler shift, and variably controlling a clock frequency of the clock generator.
A fading simulator comprising a control means (60) for arbitrarily varying a fading fluctuation amount and a Doppler shift amount with respect to an output signal of the delay circuit. 4. The attenuating circuit indirectly attenuates an output signal of the delay circuit by performing an attenuating process on a noise signal output from the noise generator. 3. The fading simulator according to 3.