CN106502309B - DA return-to-zero retention function-based time domain interleaving arbitrary waveform synthesis device and method - Google Patents

DA return-to-zero retention function-based time domain interleaving arbitrary waveform synthesis device and method Download PDF

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CN106502309B
CN106502309B CN201611034781.1A CN201611034781A CN106502309B CN 106502309 B CN106502309 B CN 106502309B CN 201611034781 A CN201611034781 A CN 201611034781A CN 106502309 B CN106502309 B CN 106502309B
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逄锦昊
刘宇
滕友伟
罗阳
董立志
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Abstract

The invention discloses a time domain interweaving arbitrary waveform synthesis device and method based on a DA return-to-zero retention function, which generates arbitrary waveform data according to waveform parameter setting of a user, obtains data reading speed through sampling rate and vertical resolution calculation, and reads the waveform data according to the reading speed to obtain DDS waveform data; even number sampling point data of DDS waveform data are transmitted to a first DA chip adopting a return-to-zero retention function, odd number sampling point data are transmitted to a second DA chip adopting the return-to-zero retention function, and analog signals output by the two DA chips are subjected to impedance matching, precise delay adjustment and signal superposition to realize vector addition of the two analog signals; and filtering the added analog signals and controlling the signal amplitude to obtain an output waveform. The invention adopts the signal superposition of two paths of DA return-to-zero hold function outputs, is equivalent to the output signal of DA zero order hold function with twice sampling rate, does not introduce other amplitude and phase variables, does not need compensation and improves the sampling rate.

Description

DA return-to-zero retention function-based time domain interleaving arbitrary waveform synthesis device and method
Technical Field
The invention relates to a time domain interweaving arbitrary waveform synthesis device and method based on a DA return-to-zero retention function.
Background
The high-speed arbitrary waveform generation technology is a signal generation technology based on digital, analog and computer technologies, and is widely applied to the fields of radar, satellite communication, electronic countermeasure, radio frequency test, integrated circuit test and the like, and becomes a research hotspot in the field of modern electronic technologies. The high-speed arbitrary waveform generator using the technology as the core has the advantages of high output frequency stability and resolution, high frequency switching speed, continuous output waveform phase during switching and the like, and the rich signal excitation capability of the generator comprises a high-speed waveform generator, a function generator, a pulse/sequence generator, a sweep generator, a trigger generator, a broadband white noise signal generator, an amplitude modulation source and the like. Meanwhile, the device has a sequence address control function, and can generate digital modulation signals, simulate various complex signals, even defects in the signals, transient signals and the like. With the development of electronic technology, high-speed arbitrary waveform generators may play an important role in a variety of applications such as broadband communication, radar systems, high-speed pulse simulation, high-speed digital design, field environment simulation, and playback.
The sampling rate and bandwidth at which high-speed arbitrary waveforms occur is limited by the sampling rate and bandwidth of the DA. Due to the design level of the DA chip and the restriction of the processing technology, the sampling rate and the bandwidth of the single-path DA cannot meet the requirement of high-speed arbitrary waveform generation. At present, the DA parallel mode is the main approach to solve the problem, and mainly includes an interpolation waveform synthesis method and a time domain interleaving waveform synthesis method based on a DA zeroth order hold function. Taking the synthesis of 2 paths of DA signals as an example, the interpolation waveform synthesis method adopts a switch circuit to realize the interpolation of 2 paths of DA analog signals. Even dots of the waveform data are output to DA-1, and odd dots of the waveform data are output to DA-2. In the following step 2: the outputs of DA-1 and DA-2 are alternately transmitted to the output terminal by the action of the 1 selection switch. The waveform sampling rate is twice of the DA sampling rate and the clock of the switch circuit, and the sampling rate is effectively improved. The method has high requirements on the switch circuit. The time domain interweaving waveform synthesis method based on the DA zeroth order hold function outputs even points of waveform data to DA-1 and outputs odd points of the waveform data to DA-2. The clock frequency of the two DA paths is half of the waveform sampling rate, and the phase difference is 180 degrees. And the addition of the DA analog signals is realized through an adder. The superposed output signals can break through the limitation of a single-path DA sampling rate and bandwidth, improve the sampling rate, and change the amplitude and the initial phase of waveform data.
Some existing high-speed arbitrary waveform generators adopt an interpolation waveform synthesis method, which has high requirements on switching time, jitter noise and service life of a switching circuit and has large limitation in high-frequency application. Other high-speed arbitrary waveform generators adopt a time domain interleaving waveform synthesis method based on DA zeroth order hold function, amplitude and phase correction factors need to be added in waveform data, and operation is complex. Meanwhile, the DA zero-order retention function has a high attenuation speed on the spectrum envelope of the output signal, and the waveform sampling rate cannot reach 40% under the uncompensated condition. In addition, the two methods have no measures for reducing the offset of the DA analog signal, and the quality of the output signal cannot be ensured.
Disclosure of Invention
The invention provides a time domain interweaving arbitrary waveform synthesis device and a method based on a DA return-to-zero retention function, which aim to solve the problems.
In order to achieve the purpose, the invention adopts the following technical scheme:
a time domain interweaving arbitrary waveform synthesis device based on a DA return-to-zero retention function comprises a controller, a parallel signal generation module, a time domain interweaving module and a channel conditioning module, wherein the time domain interweaving module comprises two DA chips adopting the return-to-zero retention function, and the DA chips adopt the return-to-zero retention function:
the controller transmits waveform data to the parallel signal generating module, the parallel signal generating module simultaneously generates a plurality of output phases of a waveform on the rising edge of a sampling clock, addresses a waveform lookup table through a plurality of output phase values simultaneously to obtain corresponding DDS data, transmits even-numbered sampling point data of the DDS waveform data to a first DA chip adopting a return-to-zero retention function, transmits odd-numbered sampling point data to a second DA chip adopting the return-to-zero retention function, vector addition of two analog signals is realized by impedance matching, precise delay adjustment and signal superposition of analog signals output by the two DA chips, and the channel conditioning module conditions the added analog signals to form a final synthetic result.
The DA chip adopting the return-to-zero retention function has the advantage that the output envelope frequency spectrum has the gentle roll-off characteristic.
The sampling clock frequencies of the two DA paths are half of the sampling rate, and the phase difference is 180 degrees.
Signals of even number sampling points of DDS data output by a first DA chip are arranged on the rising edge of a sampling clock, and the signal of a second DA chip is 0; and the falling edge is provided with the signal output of odd sampling points of DDS data output by the second DA chip, and the signal of the first DA chip is 0 and is equivalent to the output signal of a DA zero-order holding function with twice sampling rate.
The controller is connected with the parallel signal generation module through the storage management module, the storage management module receives the waveform data and stores the waveform data in the high-capacity storage, and after the waveform data are stored in the high-capacity storage, the waveform data are transmitted to the parallel signal generation module through the high-speed serial bus according to the effective data transmission rate.
The effective data transmission rate is the product of the sampling rate of the waveform data and the vertical resolution of the DA chip.
The controller is provided with a human-computer interaction module, waveform data are obtained by editing the waveform through the human-computer interaction module, the waveform data are stored as a data format file, and then the waveform data are transmitted in a quantization mode according to quantization digits.
The quantization bit number is determined by the vertical resolution D of the DA chip.
The parallel signal generation module comprises a phase accumulator, the phase accumulator is connected with a plurality of phase adders, each phase adder is provided with a waveform lookup table for addressing to obtain corresponding DDS data, and all the DDS data are transmitted to the parallel-serial conversion module; the phase accumulator is also connected to a clock unit that provides a clock frequency.
The parallel paths of the phase accumulator are more than or equal to the quotient of the waveform data sampling rate and the clock frequency.
The time domain interweaving module comprises two paths of DA chips, an impedance matching network, a precise time delay module and a vector superposition module, digital-to-analog conversion is carried out on even number sampling points and odd number sampling points of the DDS data respectively, amplitude imbalance between output signals of the two paths of DA chips is reduced by the impedance matching network, the precise time delay module is used for adjusting time sequence imbalance between the output signals of the two paths of DA chips, and the vector superposition module is used for superposition synthesis of the two paths of DA output signals.
The superposed signals have signal output on both rising edges and falling edges of sampling clocks, the superposed signals are equivalent to signal output of a path of zero-order holding function DA, and the sampling rate of the superposed signals is twice of that of a first DA chip and a second DA chip.
The channel conditioning module comprises a low-pass filtering module and an amplitude control module, wherein the low-pass filtering module filters stray signals outside a bandwidth, and the amplitude control module performs attenuation, amplification and direct-current offset processing to enable output signals to meet the requirements of amplitude and offset.
A DA return-to-zero retention function-based time domain interleaving arbitrary waveform synthesis method comprises the following steps:
(1) generating arbitrary waveform data according to waveform parameter settings of a user;
(2) calculating to obtain a data reading speed through the sampling rate and the vertical resolution, and reading waveform data according to the reading speed to obtain DDS waveform data;
(3) even number sampling point data of DDS waveform data are transmitted to a first DA chip adopting a return-to-zero retention function, odd number sampling point data are transmitted to a second DA chip adopting the return-to-zero retention function, and analog signals output by the two DA chips are subjected to impedance matching, precise delay adjustment and signal superposition to realize vector addition of the two analog signals;
(4) and filtering the added analog signals and controlling the signal amplitude to obtain an output waveform.
The invention has the beneficial effects that:
(1) according to the invention, two paths of signals output by the DA return-to-zero retention function are superposed, the signal is equivalent to an output signal of a DA zero order retention function with twice sampling rate, other amplitude and phase variables are not introduced, compensation is not needed, the operation is simpler, and the sampling rate is improved;
(2) the DA return-to-zero retention function has a gentle roll-off characteristic on the output signal spectrum envelope attenuation, and has a larger bandwidth at the same sampling rate;
(3) the invention adopts the impedance matching network to reduce amplitude imbalance during time domain interleaving, reduces time sequence imbalance through precise time delay adjustment and has the advantage of small signal distortion.
Drawings
FIG. 1 is a functional block diagram of the present invention;
FIG. 2 is an overall workflow diagram of the present invention;
FIG. 3 is a block diagram of a parallel signal generation module implementation of the present invention;
FIG. 4 is a block diagram of a time domain interleaving module implementation of the present invention;
FIG. 5 is a timing diagram of the DA return to zero hold function of the present invention;
FIG. 6 is a graph of the output spectral envelope of the DA return to zero hold function of the present invention;
FIG. 7 is a timing diagram for signal superposition according to the present invention;
fig. 8 is a graph of the output envelope spectrum after superposition in accordance with the invention.
The specific implementation mode is as follows:
the invention is further described with reference to the following figures and examples.
The invention provides a time domain interweaving arbitrary waveform synthesis device based on a DA return-to-zero retention function, which is suitable for high-speed arbitrary waveform generation. According to the waveform parameter setting of the user, arbitrary waveform data is generated at the host and transmitted to the mass storage. And calculating the reading speed of the large-capacity memory through the sampling rate and the vertical resolution, reading the waveform data from the large-capacity memory according to the reading speed, and generating parallel DDS signals to obtain DDS waveform data. Even-numbered sampling point data of DDS waveform data are transmitted to a first DA chip adopting a return-to-zero retention function, odd-numbered sampling point data are transmitted to a second DA chip adopting the return-to-zero retention function, the sampling clock frequencies of the two DA chips are half of the sampling rate, and the phase difference is 180 degrees. And the vector addition of the two analog signals is realized by the impedance matching, the precise delay adjustment and the signal superposition of the two analog signals output by the two DA circuits. Finally, the added analog signals are conditioned, which mainly comprises filtering and signal amplitude control. The sampling rate of the output waveform of the device is twice of the sampling rate of the sampling clock and the DA sampling rate, the bandwidth can reach 40 percent of the sampling rate of the waveform, and the device has the advantages of high sampling rate, large bandwidth and the like.
The arbitrary waveform synthesis device mainly comprises a host, a storage management module, a high-speed large-capacity memory, a parallel signal generation module, a time domain interweaving module, a channel conditioning module and a clock module. The schematic block diagram is shown in fig. 1. The host computer provides a man-machine interaction function to realize the editing of the waveform by the user, and waveform data is obtained. The host then stores the waveform data as a data format file. And finally, the host carries out quantization transmission on the waveform data according to the quantization bits. The number of quantization bits is determined by the vertical resolution D of the DA. The overall workflow diagram is shown in fig. 2.
The storage management module mainly comprises a high-speed serial bus module, a data cache module and a storage control module, and is realized by FPGA logic. Firstly, storing the waveform data of the host computer into a high-speed large-capacity memory, wherein the capacity of the memory is larger than the data volume of the waveform data. After the storage is finished, the storage management module transmits the waveform data to the parallel signal generation module through the high-speed serial bus according to the effective data transmission rate S.
S＝fs×D (1)
Wherein f issIs the sampling rate of the waveform data and D is the vertical resolution.
The parallel signal generation module completes the parallel DDS signal generation of the waveform data and is realized by FPGA logic. The sampling rate of the waveform data reaches several GHz level, and the working speed of a phase accumulator and a waveform memory in the FPGA is only hundreds of MHz level. In order to break through the limitation of the working speed, during the hardware implementation, the waveform data is stored and sampled in parallel, a plurality of output phases of the waveform are generated at the same time on the rising edge of a sampling clock, and the waveform lookup table is addressed at the same time through a plurality of output phase values to obtain corresponding DDS data. The implementation block diagram is shown in fig. 3. Assuming that the frequency control word is K, the bit number of the phase accumulator is N, the number of parallel DDS paths is m, and the sampling rate of the waveform data is mfaThen the frequency of the output signal can be expressed as:
Figure BDA0001152817400000051
wherein f iss＝mfa，0≤K≤2N-1。
The frequency resolution is:
Figure BDA0001152817400000052
the value of m is:
Figure BDA0001152817400000053
wherein f isFAnd the clock frequency for stable work of the FPGA.
The parallel signal generation module stores and samples waveform data in parallel, a plurality of output phases of the waveform are generated at the same time on the rising edge of a sampling clock, and the waveform lookup table is addressed at the same time through a plurality of output phase values to acquire corresponding DDS data. The parallel paths are more than or equal to the quotient of the sampling rate of the waveform data and the clock frequency of the FPGA for stable work.
As can be seen from equation (2), the sampling rate is faThe m-path parallel DDS signal output is equivalent to the sampling frequency of mfaThe output effect of a single DDS. From equation (3), the m-channel parallel DDS signal generation does not change the frequency resolution of the output signal, but generates m phase values and m waveform data points simultaneously within one sampling clock period. Thereby reducing the operating speed of the phase accumulator and the waveform memory by a factor of m. And finally, respectively transmitting the generated even sampling points and odd sampling points of the DDS data to a time domain interweaving module.
The time domain interweaving module comprises two paths of DA, an impedance matching network, a precise time delay module and a vector superposition module. The implementation block diagram is shown in fig. 4. The two paths of DA comprise a first DA chip and a second DA chip, and carry out digital-to-analog conversion on even sampling points and odd sampling points of the DDS data respectively. Two DA circuits adopt a return-to-zero retention function mode, signals are output at the rising edge of the DA clock, the output is 0 at the falling edge of the DA clock, and a timing chart is shown in FIG. 5. The fourier transform of the return-to-zero hold function to obtain the spectral envelope function of the output signal is:
wherein T is the sampling period of the single DA. The Return-to-zero preservation function output envelope spectrogram is shown in FIG. 6, where fbIs the sampling rate of the single DA. It can be seen from the graph that the output envelope spectrum of the return-to-zero hold function has a flat roll-off characteristic and a sampling rate fbLess than 3dB in the 80% bandwidth. The signal is 0 during half the clock period, so the initial value is attenuated to-6 dB.
The phase difference of the two DA clocks is 180 degrees, the sampling clock is fanned out into two paths, one path is input to the first DA chip, the other path is input to the second DA chip after phase inversion, namely, the rising edge of the clock of the first DA chip corresponds to the falling edge of the clock of the second DA chip, and the sampling clock is generated by the clock module. In this case, a signal of even sampling points of the DDS data output by the first DA chip is present on the rising edge of the sampling clock, and a signal of the second DA chip is 0; and the falling edge is provided with the signal output of odd sampling points of DDS data output by the second DA chip, and the signal of the first DA chip is 0. The impedance matching network is used for reducing amplitude imbalance between the two paths of DA output signals, and the precise time delay module is used for adjusting time sequence imbalance between the two paths of DA output signals. And the vector superposition module is used for superposition synthesis of the two paths of DA output signals. As shown in fig. 7, the superimposed signal has signal outputs on both rising and falling edges of the sampling clock, which is equivalent to a signal output of a path of zero-order hold function DA, and the sampling rate of the signal output is twice that of the first DA chip and the second DA chip. The fourier transform is performed on the superimposed retention function to obtain a spectrum envelope function of the output signal, which is:
Figure BDA0001152817400000062
wherein, TsIs the sampling period of the waveform data. The superimposed output envelope spectrum is shown in FIG. 8, where the-6 dB attenuation of the initial value is seenAnd the 2-way superposition can compensate to 0 dB. Sampling rate f of time domain interleaving module output signalsFor a single DA sampling rate fbTwice of, i.e. fb＝fs/2. Based on the principle of image signal and nonlinear harmonic cancellation, at 2fbThe image signal and the nonlinear harmonic wave in the bandwidth are offset, only the effective signal is available, and the bandwidth of the output signal can reach the sampling rate f of the output signal s40% of the total.
And the DA chip adopting the return-to-zero retention function is adopted, and the output envelope frequency spectrum has a gentle roll-off characteristic. Superposing two paths of output signals of DA return-to-zero hold functions, wherein the phase difference of two paths of DA clocks is 180 degrees, the signal of a DDS data even number sampling point output by a first DA chip is arranged on the rising edge of a sampling clock, and the signal of a second DA chip is 0; and the falling edge is provided with the signal output of odd sampling points of DDS data output by the second DA chip, and the signal of the first DA chip is 0 and is equivalent to the output signal of a DA zero-order holding function with twice sampling rate.
The channel conditioning module comprises two parts of low-pass filtering and amplitude control. Low pass filtering filters out spurious signals outside the bandwidth. The amplitude control comprises attenuation, amplification and direct current bias, so that the output signal meets the requirements of amplitude and bias. And finally, outputting the signal to the outside of the device.
The clock module provides a clock for the storage management module, the parallel signal generation module and the time domain interweaving module.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.

Claims (7)

1. A time domain interweaving arbitrary waveform synthesis device based on DA return-to-zero retention function is characterized in that: the device comprises a controller, a parallel signal generation module, a time domain interleaving module and a channel conditioning module, wherein the time domain interleaving module comprises two DA chips adopting return-to-zero retention functions, and the device comprises:
the controller transmits waveform data to a parallel signal generating module, the parallel signal generating module simultaneously generates a plurality of output phases of a waveform on the rising edge of a sampling clock, addresses a waveform lookup table through a plurality of output phase values simultaneously to obtain corresponding DDS data, transmits even-numbered sampling point data of the DDS waveform data to a first DA chip adopting a return-to-zero retention function, transmits odd-numbered sampling point data to a second DA chip adopting the return-to-zero retention function, vector addition of two analog signals is realized by impedance matching, precise delay adjustment and signal superposition of analog signals output by the two DA chips, and a channel conditioning module conditions the added analog signals to form a final synthetic result;
the DA chip adopting the return-to-zero retention function has the advantages that the output envelope frequency spectrum has the gentle roll-off characteristic;
signals of even number sampling points of DDS data output by a first DA chip are arranged on the rising edge of a sampling clock, and the signal of a second DA chip is 0; the falling edge is provided with the signal output of odd sampling points of DDS data output by a second DA chip, the signal of the first DA chip is 0, and the signal is equivalent to the output signal of a DA zero-order holding function with twice sampling rate;
the fourier transform is performed on the superimposed retention function to obtain a spectrum envelope function of the output signal, which is:
Figure FDA0002163712710000011
wherein, TsIs the sampling period of the waveform data;
the time domain interweaving module comprises two paths of DA chips, an impedance matching network, a precise time delay module and a vector superposition module, digital-to-analog conversion is carried out on even-numbered sampling points and odd-numbered sampling points of the DDS data respectively, amplitude imbalance between output signals of the two paths of DA chips is reduced by the impedance matching network, the precise time delay module is used for adjusting time sequence imbalance between the output signals of the two paths of DA chips, and the vector superposition module is used for superposition synthesis of the two paths of DA output signals;
the channel conditioning module comprises a low-pass filtering module and an amplitude control module, wherein the low-pass filtering module filters stray signals outside a bandwidth, and the amplitude control module performs attenuation, amplification and direct-current offset processing to enable output signals to meet the requirements of amplitude and offset.
2. The apparatus of claim 1, wherein the time-domain interleaved arbitrary waveform synthesis apparatus based on the DA return-to-zero hold function comprises: the sampling clock frequencies of the two DA paths are half of the sampling rate, and the phase difference is 180 degrees.
3. The apparatus of claim 1, wherein the time-domain interleaved arbitrary waveform synthesis apparatus based on the DA return-to-zero hold function comprises: the controller is connected with the parallel signal generation module through the storage management module, the storage management module receives the waveform data and stores the waveform data in the high-capacity storage, and after the waveform data are stored in the high-capacity storage, the waveform data are transmitted to the parallel signal generation module through the high-speed serial bus according to the effective data transmission rate.
4. The apparatus of claim 3, wherein the DA return-to-zero hold function based time-domain interleaved arbitrary waveform synthesis apparatus comprises: the effective data transmission rate is the product of the sampling rate of the waveform data and the vertical resolution of the DA chip.
5. The apparatus of claim 1, wherein the time-domain interleaved arbitrary waveform synthesis apparatus based on the DA return-to-zero hold function comprises: the parallel signal generation module comprises a phase accumulator, the phase accumulator is connected with a plurality of phase adders, each phase adder is provided with a waveform lookup table for addressing to obtain corresponding DDS data, and all the DDS data are transmitted to the parallel-serial conversion module; the phase accumulator is also connected to a clock unit that provides a clock frequency.
6. The apparatus of claim 1, wherein the time-domain interleaved arbitrary waveform synthesis apparatus based on the DA return-to-zero hold function comprises: the superposed signals have signal output on both rising edges and falling edges of sampling clocks, the superposed signals are equivalent to signal output of a path of zero-order holding function DA, and the sampling rate of the superposed signals is twice of that of a first DA chip and a second DA chip.
7. A waveform synthesis method using the DA return-to-zero hold function-based time-domain interleaved arbitrary waveform synthesis apparatus according to any one of claims 1 to 6, characterized by: the method comprises the following steps:
(1) generating arbitrary waveform data according to waveform parameter settings of a user;
(2) calculating to obtain a data reading speed through the sampling rate and the vertical resolution, and reading waveform data according to the reading speed to obtain DDS waveform data;
(3) even number sampling point data of DDS waveform data are transmitted to a first DA chip adopting a return-to-zero retention function, odd number sampling point data are transmitted to a second DA chip adopting the return-to-zero retention function, and analog signals output by the two DA chips are subjected to impedance matching, precise delay adjustment and signal superposition to realize vector addition of the two analog signals;
(4) and filtering the added analog signals and controlling the signal amplitude to obtain an output waveform.
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