CN106502309B - DA return-to-zero retention function-based time domain interleaving arbitrary waveform synthesis device and method - Google Patents

Abstract

The invention discloses a time-domain interleaving arbitrary waveform synthesis device and method based on a DA return-to-zero hold function to generate arbitrary waveform data according to user's waveform parameter settings, calculate the data reading speed through sampling rate and vertical resolution, Take the speed to read the waveform data to obtain the DDS waveform data; transfer the even sampling point data of the DDS waveform data to the first DA chip using the return-to-zero hold function, and transmit the odd-numbered sampling point data to the second DA using the return-to-zero hold function The chip, the analog signals output by the two DA chips are subjected to impedance matching, precise delay adjustment and signal superposition to realize the vector addition of the two analog signals; the added analog signals are filtered and the signal amplitude is controlled to obtain the output waveform. The invention adopts the superposition of the signals output by two DA return-to-zero hold functions, which is equivalent to the output signal of the DA zero-order hold function with twice the sampling rate, does not introduce other amplitude and phase variables, does not need compensation, and increases the sampling rate.

Description

Time-domain interleaved arbitrary waveform synthesis device and method based on DA return-to-zero hold function

technical field

The invention relates to a time-domain interleaving arbitrary waveform synthesis device and method based on a DA return-to-zero hold function.

Background technique

High-speed arbitrary waveform generation technology is a signal generation technology based on digital, analog and computer technology, and is widely used in radar, satellite communication, electronic countermeasures, radio frequency testing, integrated circuit testing and other fields. Research hotspots in the field of technology. The high-speed arbitrary waveform generator with this technology as the core has the advantages of high output frequency stability and resolution, fast frequency switching speed, and continuous output waveform phase during switching. Its rich signal excitation capabilities include high-speed waveform generator, function generation and so on. generators, pulse/sequence generators, sweep frequency generators, trigger generators, broadband white noise signal generators and amplitude modulation sources, etc. At the same time, it has the function of serial address control, which can generate digital modulation signals, simulate various complex signals, and even defects in the signals and transient signals. With the development of electronic technology, high-speed arbitrary waveform generator can play an important role in various applications such as broadband communication, radar system, high-speed pulse simulation, high-speed digital design, field environment simulation and playback.

The sampling rate and bandwidth of high-speed arbitrary waveform generation are limited by the sampling rate and bandwidth of the DA. Due to the constraints of the DA chip design level and processing technology, the sampling rate and bandwidth of a single-channel DA cannot meet the needs of high-speed arbitrary waveform generation. At present, DA parallel mode is the mainstream way to solve this problem, mainly including interpolation waveform synthesis method and time-domain interleaved waveform synthesis method based on DA zero-order hold function. Taking the 2-channel DA signal synthesis as an example, the interpolation waveform synthesis method adopts a switch circuit to realize the interpolation of the 2-channel DA analog signal. Outputs even-numbered points of waveform data to DA-1, and outputs odd-numbered points of waveform data to DA-2. Under the action of the 2:1 selector switch, the outputs of DA-1 and DA-2 are alternately sent to the output terminals. The waveform sampling rate is twice the DA sampling rate and the switching circuit clock, effectively increasing the sampling rate. This method has higher requirements on the switching circuit. The time-domain interleaving waveform synthesis method based on the DA zero-order hold function outputs the even-numbered points of the waveform data to DA-1, and outputs the odd-numbered points of the waveform data to DA-2. The clock frequency of the two DAs is half of the waveform sampling rate, and the phase difference is 180 degrees. The superposition of DA analog signals is realized by the adder. The superimposed output signal can break through the limitation of the sampling rate and bandwidth of the single-channel DA, and realize the improvement of the sampling rate, but also change the amplitude and initial phase of the waveform data.

Some existing high-speed arbitrary waveform generators use the interpolation waveform synthesis method, which has higher requirements on the switching time, jitter noise and service life of the switching circuit, and has great restrictions in high-frequency applications. Some other high-speed arbitrary waveform generators use the time-domain interleaving waveform synthesis method based on the DA zero-order hold function. This method needs to add amplitude and phase correction factors to the waveform data, and the operation is complicated. At the same time, the DA zero-order hold function attenuates the spectral envelope of the output signal faster, and cannot reach 40% of the waveform sampling rate without compensation. In addition, the above two methods have no measures to reduce the offset of the DA analog signal, and cannot guarantee the quality of the output signal.

SUMMARY OF THE INVENTION

In order to solve the above problems, the present invention proposes a time-domain interleaved arbitrary waveform synthesis device and method based on the DA return-to-zero hold function. The invention does not need to add a correction factor to the waveform data during the time-domain interleaved waveform synthesis, and the DA return-to-zero hold function The function has a gentle roll-off characteristic of the spectral envelope attenuation of the output signal, and has a large bandwidth. At the same time, adding an impedance matching network and precise delay adjustment to reduce the signal offset, it has the advantages of simple operation, low implementation difficulty and small signal distortion.

In order to achieve the above object, the present invention adopts the following technical solutions:

A time-domain interleaving arbitrary waveform synthesis device based on a DA return-to-zero hold function, comprising a controller, a parallel signal generation module, a time-domain interleaving module and a channel conditioning module, the time-domain interleaving module includes two using the return-to-zero hold function. DA chip, where:

The controller transmits the waveform data to the parallel signal generation module, and the parallel signal generation module simultaneously generates multiple output phases of the waveform at the rising edge of a sampling clock, and searches the waveform look-up table simultaneously through the output multiple phase values. address, obtain the corresponding DDS data, transmit the data of the even sampling points of the DDS waveform data to the first DA chip using the return-to-zero hold function, and transmit the odd-numbered sampling point data to the second DA chip using the return-to-zero hold function. The analog signal output by the DA chip is subjected to impedance matching, precise delay adjustment and signal superposition to realize the vector addition of the two analog signals. The channel conditioning module adjusts the added analog signal to form the final synthesis result.

In the DA chip using the return-to-zero hold function, the output envelope spectrum has a gentle roll-off characteristic.

The sampling clock frequencies of the two DAs are half of the sampling rate, and the phases differ by 180 degrees.

On the rising edge of the sampling clock, the signal of the even sampling point of DDS data output by the first DA chip is output, and the signal of the second DA chip is 0; The signal of the DA chip is 0, which is equivalent to the output signal of the DA zero-order hold function with twice the sampling rate.

The controller is connected to the parallel signal generation module through the storage management module, the storage management module receives the waveform data, and stores the waveform data in the large-capacity memory. transmitted to the parallel signal generation module.

The effective data transmission rate is the product of the sampling rate of the waveform data and the vertical resolution of the DA chip.

The controller is configured with a human-computer interaction module, which edits the waveform through the human-computer interaction module to obtain waveform data, stores the waveform data as a file in the .data format, and then quantizes and transmits the waveform data according to the quantization bits.

The quantization bits are determined by the vertical resolution D of the DA chip.

The parallel signal generation module includes a phase accumulator, the phase accumulator is connected to a multi-channel phase adder, each phase adder is equipped with a waveform look-up table for addressing, and obtains corresponding DDS data, and all DDS data are transmitted to the A parallel-serial conversion module; the phase accumulator is also connected with a clock unit that provides a clock frequency.

The number of parallel paths of the phase accumulator is greater than or equal to the quotient of the waveform data sampling rate and the clock frequency.

The time-domain interleaving module includes two DA chips, an impedance matching network, a precision delay module and a vector superposition module, which respectively perform digital-to-analog conversion on the data of the even sampling points and odd sampling points of the DDS data, and the impedance matching network reduces the two-way DA chips. The amplitude imbalance between the output signals, the precision delay module is used to adjust the timing imbalance between the output signals of the two DA chips, and the vector superposition module is used for the superposition and synthesis of the two DA output signals.

The superimposed signal has signal output on the rising edge and falling edge of the sampling clock, which is equivalent to the signal output of a zero-order hold function DA, and its sampling rate is twice that of the first DA chip and the second DA chip.

The channel conditioning module includes a low-pass filter module and an amplitude control module, the low-pass filter module filters out spurious signals outside the bandwidth, and the amplitude control module performs attenuation, amplification and DC bias processing to make the output signal meet the amplitude and bias. set requirements.

A time-domain interleaving arbitrary waveform synthesis method based on DA return-to-zero hold function, comprising the following steps:

(1) Generate arbitrary waveform data according to the user's waveform parameter settings;

(2) The data reading speed is obtained by calculating the sampling rate and vertical resolution, and the waveform data is read according to the reading speed to obtain the DDS waveform data;

(3) The even sampling point data of the DDS waveform data is transmitted to the first DA chip using the return-to-zero hold function, the odd-numbered sampling point data is transmitted to the second DA chip using the return-to-zero hold function, and the analog output of the two DA chips The signal is subjected to impedance matching, precise delay adjustment and signal superposition to realize the vector addition of two analog signals;

(4) Filter and control the amplitude of the added analog signal to obtain an output waveform.

The beneficial effects of the present invention are:

(1) The present invention adopts the superposition of the signals output by the two-way DA return-to-zero hold function, which is equivalent to the output signal of the DA zero-order hold function with twice the sampling rate, without introducing other amplitude and phase variables, without compensation, and the operation is relatively simple. Simple, increase the sampling rate;

(2) The DA return-to-zero hold function of the present invention has a gentle roll-off characteristic to the attenuation of the spectral envelope of the output signal, and has a larger bandwidth at the same sampling rate;

(3) The present invention adopts an impedance matching network to reduce amplitude misalignment during time-domain interleaving, and reduces timing misalignment through precise delay adjustment, which has the advantage of less signal distortion.

Description of drawings

Fig. 1 is the principle block diagram of the present invention;

Fig. 2 is the overall work flow chart of the present invention;

Fig. 3 is the realization block diagram of the parallel signal generation module of the present invention;

Fig. 4 is the time domain interleaving module realization block diagram of the present invention;

Fig. 5 is the DA return-to-zero hold function timing chart of the present invention;

Fig. 6 is the output spectrum envelope curve figure of the DA return-to-zero hold function of the present invention;

Fig. 7 is the signal superposition timing chart of the present invention;

FIG. 8 is an output envelope spectrogram after superposition of the present invention.

Detailed ways:

The present invention will be further described below with reference to the accompanying drawings and embodiments.

The invention proposes a time-domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function suitable for high-speed arbitrary waveform generation, which uses the DA time-domain interleaving of two-way return-to-zero hold functions. According to the user's waveform parameter settings, arbitrary waveform data is generated on the host and transferred to the mass storage. The reading speed from the large-capacity memory is obtained by calculating the sampling rate and vertical resolution, and the waveform data is read from the large-capacity memory according to the reading speed for parallel DDS signal generation to obtain DDS waveform data. The data of the even sampling points of the DDS waveform data is transmitted to the first DA chip using the return-to-zero hold function, and the odd-numbered sampling point data is transmitted to the second DA chip using the return-to-zero hold function. The sampling clock frequencies of the two DAs are sampling half the rate and 180 degrees out of phase. The analog signals output by the two channels of DA are subjected to impedance matching, precise delay adjustment and signal superposition to realize the vector addition of the two channels of analog signals. Finally, the added analog signal is conditioned, mainly including filtering and controlling the amplitude of the signal. The output waveform sampling rate of the device is twice that of the sampling clock and DA sampling rate, and the bandwidth can reach 40% of the waveform sampling rate, and has the advantages of high sampling rate and large bandwidth.

The arbitrary waveform synthesis device mainly includes a host computer, a storage management module, a high-speed large-capacity memory, a parallel signal generation module, a time-domain interleaving module, a channel conditioning module and a clock module. The principle block diagram is shown in Figure 1. The host provides human-computer interaction function to realize user's editing of waveform and obtain waveform data. The host then stores the waveform data as a file in .data format. Finally, the host quantizes and transmits the waveform data according to the quantization bits. The number of bits of quantization is determined by the vertical resolution D of the DA. The overall work flow chart is shown in Figure 2.

The storage management module mainly includes a high-speed serial bus module, a data cache module and a storage control module, which are implemented by FPGA logic. First, the waveform data of the host is stored in the high-speed large-capacity memory, and the capacity of the memory is larger than the data volume of the waveform data. After the storage is completed, the storage management module transmits the waveform data to the parallel signal generation module through the high-speed serial bus according to the effective data transmission rate S.

S=f _s ×D (1)

where f _s is the sampling rate of the waveform data and D is the vertical resolution.

The parallel signal generation module completes the parallel DDS signal generation of the waveform data, which is realized by the FPGA logic. The sampling rate of waveform data reaches several GHz, and the operating speed of phase accumulator and waveform memory in FPGA is only hundreds of MHz. In order to break through the limitation of working speed, in the hardware implementation, the waveform data is stored and sampled in parallel, multiple output phases of the waveform are generated at the same time on the rising edge of a sampling clock, and the waveform look-up table is addressed simultaneously through the output multiple phase values. to obtain the corresponding DDS data. The implementation block diagram is shown in Figure 3. Assuming that the frequency control word is K, the number of bits of the phase accumulator is N, the number of parallel DDS channels is m, and the sampling rate of the waveform data is mf _a , the frequency of the output signal can be expressed as:

Wherein, f _{s =} mfa , 0≤K≤2 ^N-1 .

The frequency resolution is:

The value of m is:

Among them, f _F is the clock frequency that the FPGA works stably.

The parallel signal generation module stores and samples the waveform data in parallel, generates multiple output phases of the waveform at the rising edge of a sampling clock, and simultaneously addresses the waveform look-up table through the output multiple phase values to obtain the corresponding DDS data. Among them, the number of parallel channels is greater than or equal to the quotient of the waveform data sampling rate and the clock frequency that the FPGA works stably.

It can be seen from the formula (2) that the output of m-channel parallel DDS signals with a sampling rate of f _a is equivalent to the output effect of a single DDS with a sampling frequency of mf _a . From equation (3), the generation of m parallel DDS signals does not change the frequency resolution of the output signal, but only generates m phase values and m waveform data points in one sampling clock cycle. Thus, the working speed of the phase accumulator and the waveform memory is reduced by m times. Finally, the generated DDS data even-numbered sampling points and odd-numbered sampling points are respectively transmitted to the time-domain interleaving module.

The time domain interleaving module includes two-way DA, impedance matching network, precision delay module and vector superposition module. The implementation block diagram is shown in Figure 4. The two-way DA includes a first DA chip and a second DA chip, which respectively perform digital-to-analog conversion on the data of the even sampling point and the odd sampling point of the DDS data. The two-way DA adopts the return-to-zero hold function mode, and outputs the signal on the rising edge of the DA clock, and outputs 0 on the falling edge of the DA clock. The timing diagram is shown in Figure 5. The spectral envelope function of the output signal obtained by Fourier transform of the zero-holding function is:

Among them, T is the sampling period of the single-channel DA. The output envelope spectrogram of the return-to-zero hold function is shown in Figure 6, where f _b is the sampling rate of the single-channel DA. It can be seen from the figure that the output envelope spectrum of the zero-hold function has a gentle roll-off characteristic, and the amplitude compensation within 80% of the bandwidth of the sampling rate f _b is less than 3dB. The signal is 0 for half the clock period, so the initial value is attenuated by -6dB.

The phase difference of the two DA clocks is 180 degrees, and the sampling clock fan-out is two channels, one input to the first DA chip, the other input to the second DA chip after inversion, that is, the rising edge of the first DA chip clock corresponds to the second DA chip The falling edge of the chip clock, where the sampling clock is generated by the clock module. In this case, on the rising edge of the sampling clock, there is a signal of the even sampling point of DDS data output by the first DA chip, and the signal of the second DA chip is 0; Signal output, the signal of the first DA chip is 0. The impedance matching network is used to reduce the amplitude offset between the two DA output signals, and the precision delay module is used to adjust the timing offset between the two DA output signals. The vector superposition module is used for superposition synthesis of two DA output signals. The signal superposition timing diagram is shown in Figure 7. The superimposed signal has signal output on the rising edge and falling edge of the sampling clock, which is equivalent to the signal output of a zero-order hold function DA. Its sampling rate is the same as that of the first DA chip. and twice the second DA chip. The spectral envelope function of the output signal is obtained by performing Fourier transform on the superimposed holding function:

Among them, T _s is the sampling period of the waveform data. The spectrum of the output envelope after superposition is shown in Figure 8. It can be seen from the figure that the -6dB attenuation of the initial value can be compensated to 0dB by 2-way superposition. The sampling rate f _s of the output signal of the time-domain interleaving module is twice the sampling rate f _b of the single-channel DA, that is, f _b =f _s /2. According to the principle of image signal and nonlinear harmonic cancellation, the image signal and nonlinear harmonics within the 2f _b bandwidth are canceled, only the effective signal, the output signal bandwidth can reach 40% of the output signal sampling rate f _s .

Using a DA chip with a return-to-zero hold function, the output envelope spectrum has a gentle roll-off characteristic. The output signals of the two-way DA return-to-zero hold function are used to superimpose the two-way DA clock phase difference by 180 degrees. On the rising edge of the sampling clock, there is the signal of the even sampling point of the DDS data output by the first DA chip, and the signal of the second DA chip. is 0; the falling edge has the signal output of the odd sampling point of DDS data output by the second DA chip, and the signal of the first DA chip is 0, which is equivalent to the output signal of the DA zero-order hold function with twice the sampling rate.

The channel conditioning module includes low-pass filtering and amplitude control. Low-pass filtering filters out spurious signals outside the bandwidth. Amplitude control includes attenuation, amplification and DC offset, so that the output signal meets the requirements of amplitude and offset. Finally, the signal is output to the outside of the device.

The clock module provides clocks for the storage management module, the parallel signal generation module and the time domain interleaving module.

Although the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, they do not limit the scope of protection of the present invention. Those skilled in the art should understand that on the basis of the technical solutions of the present invention, those skilled in the art do not need to pay creative efforts. Various modifications or deformations that can be made are still within the protection scope of the present invention.

Claims (7)

1. a time domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function, is characterized in that: comprise controller, parallel signal generation module, time domain interleaving module and channel conditioning module, and described time domain interleaving module comprises two A DA chip with a return-to-zero hold function, where: The controller transmits the waveform data to the parallel signal generation module, and the parallel signal generation module simultaneously generates multiple output phases of the waveform at the rising edge of a sampling clock, and searches the waveform look-up table simultaneously through the output multiple phase values. address, obtain the corresponding DDS data, transmit the data of the even sampling points of the DDS waveform data to the first DA chip using the return-to-zero hold function, and transmit the odd-numbered sampling point data to the second DA chip using the return-to-zero hold function. The analog signal output by the DA chip realizes the vector addition of two analog signals after impedance matching, precise delay adjustment and signal superposition, and the channel conditioning module adjusts the added analog signal to form the final synthesis result; The DA chip using the return-to-zero hold function has a gentle roll-off characteristic of the output envelope spectrum; On the rising edge of the sampling clock, the signal of the even sampling point of DDS data output by the first DA chip is output, and the signal of the second DA chip is 0; The signal of the DA chip is 0, which is equivalent to the output signal of the DA zero-order hold function with twice the sampling rate; The spectral envelope function of the output signal is obtained by performing Fourier transform on the superimposed holding function:

Among them, T _s is the sampling period of waveform data; The time-domain interleaving module includes two DA chips, an impedance matching network, a precision delay module and a vector superposition module, which respectively perform digital-to-analog conversion on the data of the even sampling points and odd sampling points of the DDS data, and the impedance matching network reduces the two-way DA chips. The amplitude imbalance between the output signals, the precision delay module is used to adjust the timing imbalance between the output signals of the two DA chips, and the vector superposition module is used for the superposition and synthesis of the two DA output signals; The channel conditioning module includes a low-pass filter module and an amplitude control module, the low-pass filter module filters out spurious signals outside the bandwidth, and the amplitude control module performs attenuation, amplification and DC bias processing to make the output signal meet the amplitude and bias. set requirements. 2. a kind of time-domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function as claimed in claim 1, it is characterized in that: the sampling clock frequency of described two-way DA is half of the sampling rate, and the phase difference is 180 Spend. 3. a kind of time-domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function as claimed in claim 1, is characterized in that: described controller connects parallel signal generation module by storage management module, and described storage management module receives The waveform data is stored in the large-capacity memory. After the storage is completed, the waveform data is transmitted to the parallel signal generation module through the high-speed serial bus according to the effective data transmission rate. 4. a kind of time-domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function as claimed in claim 3, it is characterized in that: described effective data transmission rate is the sampling rate of waveform data and the vertical resolution of DA chip product. 5. a kind of time-domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function as claimed in claim 1, is characterized in that: described parallel signal generation module, comprises phase accumulator, and described phase accumulator is connected with multiplex Phase adder, each phase adder is equipped with a waveform look-up table for addressing, obtains corresponding DDS data, and all DDS data are transmitted to the parallel-serial conversion module; the phase accumulator is also connected with a clock unit that provides a clock frequency. 6. a kind of time-domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function as claimed in claim 1, it is characterized in that: the signal after the superposition has signal output at sampling clock rising edge and falling edge, equivalent It is a signal output of a DA of a zero-order hold function, and its sampling rate is twice that of the first DA chip and the second DA chip. 7. a waveform synthesis method utilizing the time domain interleaving arbitrary waveform synthesis device based on the DA return-to-zero hold function according to any one of claims 1-6, is characterized in that: comprise the following steps: (1) Generate arbitrary waveform data according to the user's waveform parameter settings; (2) The data reading speed is obtained by calculating the sampling rate and vertical resolution, and the waveform data is read according to the reading speed to obtain the DDS waveform data; (3) The even sampling point data of the DDS waveform data is transmitted to the first DA chip using the return-to-zero hold function, the odd-numbered sampling point data is transmitted to the second DA chip using the return-to-zero hold function, and the analog output of the two DA chips The signal is subjected to impedance matching, precise delay adjustment and signal superposition to realize the vector addition of two analog signals; (4) Filter and control the amplitude of the added analog signal to obtain an output waveform.

Images