CN106502309B - DA return-to-zero retention function-based time domain interleaving arbitrary waveform synthesis device and method - Google Patents

DA return-to-zero retention function-based time domain interleaving arbitrary waveform synthesis device and method Download PDF

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CN106502309B
CN106502309B CN201611034781.1A CN201611034781A CN106502309B CN 106502309 B CN106502309 B CN 106502309B CN 201611034781 A CN201611034781 A CN 201611034781A CN 106502309 B CN106502309 B CN 106502309B
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逄锦昊
刘宇
滕友伟
罗阳
董立志
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Abstract

本发明公开了一种基于DA归零保持函数的时域交织任意波形合成装置及方法根据用户的波形参数设置,产生任意波形数据,通过采样率和垂直分辨率计算得到数据读取速度,根据读取速度读取波形数据,得到DDS波形数据;将DDS波形数据的偶数采样点数据传输到采用归零保持函数的第一DA芯片,将奇数采样点数据传输到采用归零保持函数的第二DA芯片,两路DA芯片输出的模拟信号经过阻抗匹配、精密延时调整和信号叠加实现两路模拟信号的矢量相加;对相加后的模拟信号进行滤波和控制信号幅度,得到输出波形。本发明采用两路DA归零保持函数输出的信号叠加,等效于两倍采样率的DA零阶保持函数的输出信号,不会引入其它的幅度和相位变量,无需补偿,提高采样率。

Figure 201611034781

The invention discloses a time-domain interleaving arbitrary waveform synthesis device and method based on a DA return-to-zero hold function to generate arbitrary waveform data according to user's waveform parameter settings, calculate the data reading speed through sampling rate and vertical resolution, Take the speed to read the waveform data to obtain the DDS waveform data; transfer the even sampling point data of the DDS waveform data to the first DA chip using the return-to-zero hold function, and transmit the odd-numbered sampling point data to the second DA using the return-to-zero hold function The chip, the analog signals output by the two DA chips are subjected to impedance matching, precise delay adjustment and signal superposition to realize the vector addition of the two analog signals; the added analog signals are filtered and the signal amplitude is controlled to obtain the output waveform. The invention adopts the superposition of the signals output by two DA return-to-zero hold functions, which is equivalent to the output signal of the DA zero-order hold function with twice the sampling rate, does not introduce other amplitude and phase variables, does not need compensation, and increases the sampling rate.

Figure 201611034781

Description

基于DA归零保持函数的时域交织任意波形合成装置及方法Time-domain interleaved arbitrary waveform synthesis device and method based on DA return-to-zero hold function

技术领域technical field

本发明涉及一种基于DA归零保持函数的时域交织任意波形合成装置及方法。The invention relates to a time-domain interleaving arbitrary waveform synthesis device and method based on a DA return-to-zero hold function.

背景技术Background technique

高速任意波形发生技术是以数字、模拟和计算机技术为基础的信号发生技术,广泛应用于雷达、卫星通信、电子对抗、射频测试、集成电路测试等领域中,高速任意波形发生技术已经成为现代电子技术领域的研究热点。以该技术为核心的高速任意波形发生器具有输出频率稳定度和分辨率高,频率切换速度快,并且切换时输出波形相位连续等优点,其丰富的信号激励能力包括高速波形发生器、函数发生器、脉冲/序列发生器、扫频发生器、触发发生器、宽带白噪声信号发生器和幅度调制源等。同时具有序列地址控制功能,能产生数字调制信号、模拟各种复杂信号,甚至信号中的缺陷以及瞬变信号等。随着电子技术的发展,高速任意波形发生器可以在宽带通信、雷达系统、高速脉冲模拟、高速数字设计、现场环境模拟和重放等多种应用具有重要作用。High-speed arbitrary waveform generation technology is a signal generation technology based on digital, analog and computer technology, and is widely used in radar, satellite communication, electronic countermeasures, radio frequency testing, integrated circuit testing and other fields. Research hotspots in the field of technology. The high-speed arbitrary waveform generator with this technology as the core has the advantages of high output frequency stability and resolution, fast frequency switching speed, and continuous output waveform phase during switching. Its rich signal excitation capabilities include high-speed waveform generator, function generation and so on. generators, pulse/sequence generators, sweep frequency generators, trigger generators, broadband white noise signal generators and amplitude modulation sources, etc. At the same time, it has the function of serial address control, which can generate digital modulation signals, simulate various complex signals, and even defects in the signals and transient signals. With the development of electronic technology, high-speed arbitrary waveform generator can play an important role in various applications such as broadband communication, radar system, high-speed pulse simulation, high-speed digital design, field environment simulation and playback.

高速任意波形发生的采样率和带宽受限于DA的采样率和带宽。由于受到DA芯片设计水平和加工工艺的制约,单路DA的采样率及带宽无法满足高速任意波形发生的需求。目前,DA并行模式是解决该问题的主流途径,主要包括插值波形合成方法和基于DA零阶保持函数的时域交织波形合成方法。以2路DA信号合成为例,插值波形合成方法采用开关电路实现2路DA模拟信号的插值。将波形数据的偶数点输出到DA-1,将波形数据的奇数点输出到DA-2。在2:1选择开关的作用下DA-1和DA-2的输出交替地被传送到输出端。波形采样率是DA采样率和开关电路时钟的两倍,有效提高采样率。该方法对开关电路要求较高。基于DA零阶保持函数的时域交织波形合成方法将波形数据的偶数点输出到DA-1,将波形数据的奇数点输出到DA-2。两路DA的时钟频率均为波形采样率的一半,相位相差180度。通过加法器实现DA模拟信号的叠加。叠加的输出信号能够突破单路DA采样率和带宽的限制,实现采样率的提高,但也改变波形数据的幅度和初始相位。The sampling rate and bandwidth of high-speed arbitrary waveform generation are limited by the sampling rate and bandwidth of the DA. Due to the constraints of the DA chip design level and processing technology, the sampling rate and bandwidth of a single-channel DA cannot meet the needs of high-speed arbitrary waveform generation. At present, DA parallel mode is the mainstream way to solve this problem, mainly including interpolation waveform synthesis method and time-domain interleaved waveform synthesis method based on DA zero-order hold function. Taking the 2-channel DA signal synthesis as an example, the interpolation waveform synthesis method adopts a switch circuit to realize the interpolation of the 2-channel DA analog signal. Outputs even-numbered points of waveform data to DA-1, and outputs odd-numbered points of waveform data to DA-2. Under the action of the 2:1 selector switch, the outputs of DA-1 and DA-2 are alternately sent to the output terminals. The waveform sampling rate is twice the DA sampling rate and the switching circuit clock, effectively increasing the sampling rate. This method has higher requirements on the switching circuit. The time-domain interleaving waveform synthesis method based on the DA zero-order hold function outputs the even-numbered points of the waveform data to DA-1, and outputs the odd-numbered points of the waveform data to DA-2. The clock frequency of the two DAs is half of the waveform sampling rate, and the phase difference is 180 degrees. The superposition of DA analog signals is realized by the adder. The superimposed output signal can break through the limitation of the sampling rate and bandwidth of the single-channel DA, and realize the improvement of the sampling rate, but also change the amplitude and initial phase of the waveform data.

现有的一些高速任意波形发生器采用插值波形合成方法,这种方法对开关电路的切换时间,抖动噪声和使用寿命要求较高,在高频应用中限制较大。其它一些高速任意波形发生器采用基于DA零阶保持函数的时域交织波形合成方法,该方法需在波形数据中添加幅度和相位校正因子,操作复杂。同时,DA零阶保持函数对输出信号频谱包络衰减速度较快,在无补偿条件下不能达到波形采样率的40%。此外,上述两种方法没有降低DA模拟信号失调的措施,不能保证输出信号的质量。Some existing high-speed arbitrary waveform generators use the interpolation waveform synthesis method, which has higher requirements on the switching time, jitter noise and service life of the switching circuit, and has great restrictions in high-frequency applications. Some other high-speed arbitrary waveform generators use the time-domain interleaving waveform synthesis method based on the DA zero-order hold function. This method needs to add amplitude and phase correction factors to the waveform data, and the operation is complicated. At the same time, the DA zero-order hold function attenuates the spectral envelope of the output signal faster, and cannot reach 40% of the waveform sampling rate without compensation. In addition, the above two methods have no measures to reduce the offset of the DA analog signal, and cannot guarantee the quality of the output signal.

发明内容SUMMARY OF THE INVENTION

本发明为了解决上述问题,提出了一种基于DA归零保持函数的时域交织任意波形合成装置及方法,该发明在时域交织波形合成时无需在波形数据内添加校正因子,DA归零保持函数对输出信号频谱包络衰减具有平缓的滚降特性,具有较大的带宽,同时添加阻抗匹配网络和精密延时调整降低信号的失调,具有操作简单,实现难度低,信号失真小的优点。In order to solve the above problems, the present invention proposes a time-domain interleaved arbitrary waveform synthesis device and method based on the DA return-to-zero hold function. The invention does not need to add a correction factor to the waveform data during the time-domain interleaved waveform synthesis, and the DA return-to-zero hold function The function has a gentle roll-off characteristic of the spectral envelope attenuation of the output signal, and has a large bandwidth. At the same time, adding an impedance matching network and precise delay adjustment to reduce the signal offset, it has the advantages of simple operation, low implementation difficulty and small signal distortion.

为了实现上述目的,本发明采用如下技术方案:In order to achieve the above object, the present invention adopts the following technical solutions:

一种基于DA归零保持函数的时域交织任意波形合成装置,包括控制器、并行信号发生模块、时域交织模块和通道调理模块,所述时域交织模块包括两个采用归零保持函数的DA芯片,其中:A time-domain interleaving arbitrary waveform synthesis device based on a DA return-to-zero hold function, comprising a controller, a parallel signal generation module, a time-domain interleaving module and a channel conditioning module, the time-domain interleaving module includes two using the return-to-zero hold function. DA chip, where:

所述控制器将波形数据传输到并行信号发生模块,所述并行信号发生模块,在一个采样时钟的上升沿同时产生波形的多个输出相位,通过输出的多个相位值同时对波形查找表寻址,获取相应的DDS数据,将DDS波形数据的偶数采样点数据传输到采用归零保持函数的第一DA芯片,将奇数采样点数据传输到采用归零保持函数的第二DA芯片,两路DA芯片输出的模拟信号经过阻抗匹配、精密延时调整和信号叠加实现两路模拟信号的矢量相加,通道调理模块对相加后的模拟信号进行调理,形成最终的合成结果。The controller transmits the waveform data to the parallel signal generation module, and the parallel signal generation module simultaneously generates multiple output phases of the waveform at the rising edge of a sampling clock, and searches the waveform look-up table simultaneously through the output multiple phase values. address, obtain the corresponding DDS data, transmit the data of the even sampling points of the DDS waveform data to the first DA chip using the return-to-zero hold function, and transmit the odd-numbered sampling point data to the second DA chip using the return-to-zero hold function. The analog signal output by the DA chip is subjected to impedance matching, precise delay adjustment and signal superposition to realize the vector addition of the two analog signals. The channel conditioning module adjusts the added analog signal to form the final synthesis result.

所述采用归零保持函数的DA芯片,输出包络频谱具有平缓的滚降特性。In the DA chip using the return-to-zero hold function, the output envelope spectrum has a gentle roll-off characteristic.

所述的两路DA的采样时钟频率均为采样率的一半,相位相差180度。The sampling clock frequencies of the two DAs are half of the sampling rate, and the phases differ by 180 degrees.

在采样时钟的上升沿有第一DA芯片输出的DDS数据偶数采样点的信号,第二DA芯片的信号为0;下降沿有第二DA芯片输出的DDS数据奇数采样点的信号输出,第一DA芯片的信号为0,等效于两倍采样率的DA零阶保持函数的输出信号。On the rising edge of the sampling clock, the signal of the even sampling point of DDS data output by the first DA chip is output, and the signal of the second DA chip is 0; The signal of the DA chip is 0, which is equivalent to the output signal of the DA zero-order hold function with twice the sampling rate.

所述控制器通过存储管理模块连接并行信号发生模块,所述存储管理模块接收波形数据,并将其存储值大容量存储器中,存储完毕后,按照有效数据传输速率通过高速串行总线将波形数据传输到并行信号发生模块。The controller is connected to the parallel signal generation module through the storage management module, the storage management module receives the waveform data, and stores the waveform data in the large-capacity memory. transmitted to the parallel signal generation module.

所述有效数据传输速率为波形数据的采样率与DA芯片的垂直分辨率的乘积。The effective data transmission rate is the product of the sampling rate of the waveform data and the vertical resolution of the DA chip.

所述控制器配置有人机交互模块,通过人机交互模块对波形进行编辑,得到波形数据,将波形数据存储为.data格式的文件,再根据量化位数对波形数据量化传输。The controller is configured with a human-computer interaction module, which edits the waveform through the human-computer interaction module to obtain waveform data, stores the waveform data as a file in the .data format, and then quantizes and transmits the waveform data according to the quantization bits.

所述量化位数由DA芯片的垂直分辨率D确定。The quantization bits are determined by the vertical resolution D of the DA chip.

所述并行信号发生模块,包括相位累加器,所述相位累加器连接多路相位加法器,每个相位加法器配备有波形查找表进行寻址,获取相应的DDS数据,所有DDS数据均传输给并串转换模块;所述相位累加器还连接有提供时钟频率的时钟单元。The parallel signal generation module includes a phase accumulator, the phase accumulator is connected to a multi-channel phase adder, each phase adder is equipped with a waveform look-up table for addressing, and obtains corresponding DDS data, and all DDS data are transmitted to the A parallel-serial conversion module; the phase accumulator is also connected with a clock unit that provides a clock frequency.

所述相位累加器并行的路数大于等于波形数据采样率和时钟频率的商。The number of parallel paths of the phase accumulator is greater than or equal to the quotient of the waveform data sampling rate and the clock frequency.

所述时域交织模块包括两路DA芯片、阻抗匹配网络、精密延时模块和矢量叠加模块,分别对DDS数据偶数采样点和奇数采样点数据进行数模转换,阻抗匹配网络降低两路DA芯片输出信号之间的幅度失调,精密延时模块用于调整两路DA芯片输出信号之间的时序失调,矢量叠加模块用于两路DA输出信号的叠加合成。The time-domain interleaving module includes two DA chips, an impedance matching network, a precision delay module and a vector superposition module, which respectively perform digital-to-analog conversion on the data of the even sampling points and odd sampling points of the DDS data, and the impedance matching network reduces the two-way DA chips. The amplitude imbalance between the output signals, the precision delay module is used to adjust the timing imbalance between the output signals of the two DA chips, and the vector superposition module is used for the superposition and synthesis of the two DA output signals.

叠加后的信号在采样时钟上升沿的和下降沿均有信号输出,等效为一路零阶保持函数的DA的信号输出,其采样率是第一DA芯片和第二DA芯片的两倍。The superimposed signal has signal output on the rising edge and falling edge of the sampling clock, which is equivalent to the signal output of a zero-order hold function DA, and its sampling rate is twice that of the first DA chip and the second DA chip.

所述通道调理模块包括低通滤波模块和幅度控制模块,所述低通滤波模块滤除带宽外的杂散信号,幅度控制模块进行衰减、放大和直流偏置处理,使输出信号满足幅度和偏置的要求。The channel conditioning module includes a low-pass filter module and an amplitude control module, the low-pass filter module filters out spurious signals outside the bandwidth, and the amplitude control module performs attenuation, amplification and DC bias processing to make the output signal meet the amplitude and bias. set requirements.

一种基于DA归零保持函数的时域交织任意波形合成方法,包括以下步骤:A time-domain interleaving arbitrary waveform synthesis method based on DA return-to-zero hold function, comprising the following steps:

(1)根据用户的波形参数设置,产生任意波形数据;(1) Generate arbitrary waveform data according to the user's waveform parameter settings;

(2)通过采样率和垂直分辨率计算得到数据读取速度,根据读取速度读取波形数据,得到DDS波形数据;(2) The data reading speed is obtained by calculating the sampling rate and vertical resolution, and the waveform data is read according to the reading speed to obtain the DDS waveform data;

(3)将DDS波形数据的偶数采样点数据传输到采用归零保持函数的第一DA芯片,将奇数采样点数据传输到采用归零保持函数的第二DA芯片,两路DA芯片输出的模拟信号经过阻抗匹配、精密延时调整和信号叠加实现两路模拟信号的矢量相加;(3) The even sampling point data of the DDS waveform data is transmitted to the first DA chip using the return-to-zero hold function, the odd-numbered sampling point data is transmitted to the second DA chip using the return-to-zero hold function, and the analog output of the two DA chips The signal is subjected to impedance matching, precise delay adjustment and signal superposition to realize the vector addition of two analog signals;

(4)对相加后的模拟信号进行滤波和控制信号幅度,得到输出波形。(4) Filter and control the amplitude of the added analog signal to obtain an output waveform.

本发明的有益效果为:The beneficial effects of the present invention are:

(1)本发明采用两路DA归零保持函数输出的信号叠加,等效于两倍采样率的DA零阶保持函数的输出信号,不会引入其它的幅度和相位变量,无需补偿,操作较为简单,提高采样率;(1) The present invention adopts the superposition of the signals output by the two-way DA return-to-zero hold function, which is equivalent to the output signal of the DA zero-order hold function with twice the sampling rate, without introducing other amplitude and phase variables, without compensation, and the operation is relatively simple. Simple, increase the sampling rate;

(2)本发明DA归零保持函数对输出信号频谱包络衰减具有平缓的滚降特性,在相同采样率时具有较大的带宽;(2) The DA return-to-zero hold function of the present invention has a gentle roll-off characteristic to the attenuation of the spectral envelope of the output signal, and has a larger bandwidth at the same sampling rate;

(3)本发明在时域交织时采用阻抗匹配网络降低幅度失调,通过精密延时调整降低时序失调,具有信号失真小的优点。(3) The present invention adopts an impedance matching network to reduce amplitude misalignment during time-domain interleaving, and reduces timing misalignment through precise delay adjustment, which has the advantage of less signal distortion.

附图说明Description of drawings

图1是本发明的原理框图;Fig. 1 is the principle block diagram of the present invention;

图2是本发明的总体工作流程图;Fig. 2 is the overall work flow chart of the present invention;

图3是本发明的并行信号发生模块实现框图;Fig. 3 is the realization block diagram of the parallel signal generation module of the present invention;

图4是本发明的时域交织模块实现框图;Fig. 4 is the time domain interleaving module realization block diagram of the present invention;

图5是本发明的DA归零保持函数时序图;Fig. 5 is the DA return-to-zero hold function timing chart of the present invention;

图6是本发明的DA归零保持函数的输出频谱包络曲线图;Fig. 6 is the output spectrum envelope curve figure of the DA return-to-zero hold function of the present invention;

图7是本发明的信号叠加时序图;Fig. 7 is the signal superposition timing chart of the present invention;

图8是本发明的叠加后的输出包络频谱图。FIG. 8 is an output envelope spectrogram after superposition of the present invention.

具体实施方式:Detailed ways:

下面结合附图与实施例对本发明作进一步说明。The present invention will be further described below with reference to the accompanying drawings and embodiments.

本发明提出了一种适用于高速任意波形发生的基于DA归零保持函数的时域交织任意波形合成装置,它通过两路归零保持函数的DA时域交织。根据用户的波形参数设置,在主机产生任意波形数据并传输到大容量存储器。通过采样率和垂直分辨率计算得到从大容量存储器读取速度,根据读取速度从大容量存储器中读取波形数据进行并行DDS信号发生,得到DDS波形数据。将DDS波形数据的偶数采样点数据传输到采用归零保持函数的第一DA芯片,将奇数采样点数据传输到采用归零保持函数的第二DA芯片,两路DA的采样时钟频率均为采样率的一半,相位相差180度。两路DA输出的模拟信号经过阻抗匹配、精密延时调整和信号叠加实现两路模拟信号的矢量相加。最后对相加后的模拟信号进行调理,主要包括滤波和控制信号幅度。该装置输出波形采样率是采样时钟和DA采样率的两倍,带宽可达到波形采样率的40%,具有采样率高和带宽大等优点。The invention proposes a time-domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function suitable for high-speed arbitrary waveform generation, which uses the DA time-domain interleaving of two-way return-to-zero hold functions. According to the user's waveform parameter settings, arbitrary waveform data is generated on the host and transferred to the mass storage. The reading speed from the large-capacity memory is obtained by calculating the sampling rate and vertical resolution, and the waveform data is read from the large-capacity memory according to the reading speed for parallel DDS signal generation to obtain DDS waveform data. The data of the even sampling points of the DDS waveform data is transmitted to the first DA chip using the return-to-zero hold function, and the odd-numbered sampling point data is transmitted to the second DA chip using the return-to-zero hold function. The sampling clock frequencies of the two DAs are sampling half the rate and 180 degrees out of phase. The analog signals output by the two channels of DA are subjected to impedance matching, precise delay adjustment and signal superposition to realize the vector addition of the two channels of analog signals. Finally, the added analog signal is conditioned, mainly including filtering and controlling the amplitude of the signal. The output waveform sampling rate of the device is twice that of the sampling clock and DA sampling rate, and the bandwidth can reach 40% of the waveform sampling rate, and has the advantages of high sampling rate and large bandwidth.

任意波形合成装置主要包括主机,存储管理模块,高速大容量存储器,并行信号发生模块,时域交织模块,通道调理模块和时钟模块。原理框图如图1所示。主机提供人机交互功能实现用户对波形的编辑,得到波形数据。然后主机将波形数据存储为.data格式的文件。最后主机根据量化位数对波形数据量化传输。量化位数由DA的垂直分辨率D确定。总体工作流程图如图2所示。The arbitrary waveform synthesis device mainly includes a host computer, a storage management module, a high-speed large-capacity memory, a parallel signal generation module, a time-domain interleaving module, a channel conditioning module and a clock module. The principle block diagram is shown in Figure 1. The host provides human-computer interaction function to realize user's editing of waveform and obtain waveform data. The host then stores the waveform data as a file in .data format. Finally, the host quantizes and transmits the waveform data according to the quantization bits. The number of bits of quantization is determined by the vertical resolution D of the DA. The overall work flow chart is shown in Figure 2.

存储管理模块主要包括高速串行总线模块、数据缓存模块和存储控制模块,由FPGA逻辑实现。首先将主机的波形数据存储到高速大容量存储器,存储器的容量大于波形数据的数据量。在存储完毕后,存储管理模块按有效数据传输速率S通过高速串行总线将波形数据传输到并行信号发生模块。The storage management module mainly includes a high-speed serial bus module, a data cache module and a storage control module, which are implemented by FPGA logic. First, the waveform data of the host is stored in the high-speed large-capacity memory, and the capacity of the memory is larger than the data volume of the waveform data. After the storage is completed, the storage management module transmits the waveform data to the parallel signal generation module through the high-speed serial bus according to the effective data transmission rate S.

S=fs×D (1)S=f s ×D (1)

其中fs为波形数据的采样率,D为垂直分辨率。where f s is the sampling rate of the waveform data and D is the vertical resolution.

并行信号发生模块完成波形数据的并行DDS信号发生,由FPGA逻辑实现。波形数据的采样率达到数GHz级,在FPGA内的相位累加器和波形存储器工作速度仅为数百MHz级。为了突破工作速度的限制,在硬件实现时,将波形数据并行存储和取样,在一个采样时钟的上升沿同时产生波形的多个输出相位,通过输出的多个相位值同时对波形查找表寻址,获取相应的DDS数据。实现框图如图3所示。假设频率控制字为K,相位累加器的位数为N,并行DDS的路数为m,波形数据的采样率为mfa,则输出信号的频率可表示为:The parallel signal generation module completes the parallel DDS signal generation of the waveform data, which is realized by the FPGA logic. The sampling rate of waveform data reaches several GHz, and the operating speed of phase accumulator and waveform memory in FPGA is only hundreds of MHz. In order to break through the limitation of working speed, in the hardware implementation, the waveform data is stored and sampled in parallel, multiple output phases of the waveform are generated at the same time on the rising edge of a sampling clock, and the waveform look-up table is addressed simultaneously through the output multiple phase values. to obtain the corresponding DDS data. The implementation block diagram is shown in Figure 3. Assuming that the frequency control word is K, the number of bits of the phase accumulator is N, the number of parallel DDS channels is m, and the sampling rate of the waveform data is mf a , the frequency of the output signal can be expressed as:

Figure BDA0001152817400000051
Figure BDA0001152817400000051

其中,fs=mfa,0≤K≤2N-1Wherein, f s = mfa , 0≤K≤2 N-1 .

频率分辨率为:The frequency resolution is:

Figure BDA0001152817400000052
Figure BDA0001152817400000052

m的取值为:The value of m is:

Figure BDA0001152817400000053
Figure BDA0001152817400000053

其中,fF为FPGA稳定工作的时钟频率。Among them, f F is the clock frequency that the FPGA works stably.

并行信号发生模块将波形数据并行存储和取样,在一个采样时钟的上升沿同时产生波形的多个输出相位,通过输出的多个相位值同时对波形查找表寻址,获取相应的DDS数据。其中,并行的路数大于等于波形数据采样率和FPGA稳定工作的时钟频率的商。The parallel signal generation module stores and samples the waveform data in parallel, generates multiple output phases of the waveform at the rising edge of a sampling clock, and simultaneously addresses the waveform look-up table through the output multiple phase values to obtain the corresponding DDS data. Among them, the number of parallel channels is greater than or equal to the quotient of the waveform data sampling rate and the clock frequency that the FPGA works stably.

由式(2)可以看出,采样率为fa的m路并行DDS信号输出等效于采样频率为mfa的单DDS的输出效果。从式(3)可得,m路并行DDS信号发生并不改变输出信号的频率分辨率,仅仅是在一个采样时钟周期内,同时生成m个相位值和m个波形数据点。从而将相位累加器和波形存储器的工作速度降低m倍。最后将产生的DDS数据偶数采样点和奇数采样点分别传输到时域交织模块。It can be seen from the formula (2) that the output of m-channel parallel DDS signals with a sampling rate of f a is equivalent to the output effect of a single DDS with a sampling frequency of mf a . From equation (3), the generation of m parallel DDS signals does not change the frequency resolution of the output signal, but only generates m phase values and m waveform data points in one sampling clock cycle. Thus, the working speed of the phase accumulator and the waveform memory is reduced by m times. Finally, the generated DDS data even-numbered sampling points and odd-numbered sampling points are respectively transmitted to the time-domain interleaving module.

时域交织模块包括两路DA,阻抗匹配网络,精密延时模块和矢量叠加模块。实现框图如图4所示。两路DA包括第一DA芯片和第二DA芯片,分别对DDS数据偶数采样点和奇数采样点数据进行数模转换。两路DA采用归零保持函数模式,在DA时钟的上升沿输出信号,在DA时钟的下降沿输出为0,时序图如图5所示。对归零保持函数进行傅里叶变换得到输出信号的频谱包络函数为:The time domain interleaving module includes two-way DA, impedance matching network, precision delay module and vector superposition module. The implementation block diagram is shown in Figure 4. The two-way DA includes a first DA chip and a second DA chip, which respectively perform digital-to-analog conversion on the data of the even sampling point and the odd sampling point of the DDS data. The two-way DA adopts the return-to-zero hold function mode, and outputs the signal on the rising edge of the DA clock, and outputs 0 on the falling edge of the DA clock. The timing diagram is shown in Figure 5. The spectral envelope function of the output signal obtained by Fourier transform of the zero-holding function is:

其中,T为单路DA的采样周期。归零保持函数输出包络频谱图如图6所示,其中fb为单路DA的采样率。从图中可以看出归零保持函数输出包络频谱具有平缓的滚降特性,采样率fb的80%带宽内的幅度补偿小于3dB。在时钟周期的一半时间里信号为0,所以初始值衰减为-6dB。Among them, T is the sampling period of the single-channel DA. The output envelope spectrogram of the return-to-zero hold function is shown in Figure 6, where f b is the sampling rate of the single-channel DA. It can be seen from the figure that the output envelope spectrum of the zero-hold function has a gentle roll-off characteristic, and the amplitude compensation within 80% of the bandwidth of the sampling rate f b is less than 3dB. The signal is 0 for half the clock period, so the initial value is attenuated by -6dB.

两路DA时钟相位相差180度,采样时钟扇出为两路,一路输入到第一DA芯片,另一路反相后输入到第二DA芯片,即第一DA芯片时钟的上升沿对应第二DA芯片时钟的下降沿,其中采样时钟由时钟模块产生。这种情况下,在采样时钟的上升沿有第一DA芯片输出的DDS数据偶数采样点的信号,第二DA芯片的信号为0;下降沿有第二DA芯片输出的DDS数据奇数采样点的信号输出,第一DA芯片的信号为0。阻抗匹配网络用于降低两路DA输出信号之间的幅度失调,精密延时模块用于调整两路DA输出信号之间的时序失调。矢量叠加模块用于两路DA输出信号的叠加合成。信号叠加时序图如图7所示,叠加后的信号在采样时钟上升沿的和下降沿均有信号输出,等效为一路零阶保持函数的DA的信号输出,其采样率是第一DA芯片和第二DA芯片的两倍。对叠加后的保持函数进行傅里叶变换得到输出信号的频谱包络函数为:The phase difference of the two DA clocks is 180 degrees, and the sampling clock fan-out is two channels, one input to the first DA chip, the other input to the second DA chip after inversion, that is, the rising edge of the first DA chip clock corresponds to the second DA chip The falling edge of the chip clock, where the sampling clock is generated by the clock module. In this case, on the rising edge of the sampling clock, there is a signal of the even sampling point of DDS data output by the first DA chip, and the signal of the second DA chip is 0; Signal output, the signal of the first DA chip is 0. The impedance matching network is used to reduce the amplitude offset between the two DA output signals, and the precision delay module is used to adjust the timing offset between the two DA output signals. The vector superposition module is used for superposition synthesis of two DA output signals. The signal superposition timing diagram is shown in Figure 7. The superimposed signal has signal output on the rising edge and falling edge of the sampling clock, which is equivalent to the signal output of a zero-order hold function DA. Its sampling rate is the same as that of the first DA chip. and twice the second DA chip. The spectral envelope function of the output signal is obtained by performing Fourier transform on the superimposed holding function:

Figure BDA0001152817400000062
Figure BDA0001152817400000062

其中,Ts为波形数据的采样周期。叠加后的输出包络频谱图如图8所示,从图中可以看出,初始值的-6dB衰减,通过2路叠加可以补偿为0dB。时域交织模块输出信号的采样率fs为单路DA采样率fb的两倍,即fb=fs/2。根据镜像信号和非线性谐波抵消原理,在2fb带宽内的镜像信号和非线性谐波均被抵消,只有有效信号,输出信号带宽可以达到输出信号采样率fs的40%。Among them, T s is the sampling period of the waveform data. The spectrum of the output envelope after superposition is shown in Figure 8. It can be seen from the figure that the -6dB attenuation of the initial value can be compensated to 0dB by 2-way superposition. The sampling rate f s of the output signal of the time-domain interleaving module is twice the sampling rate f b of the single-channel DA, that is, f b =f s /2. According to the principle of image signal and nonlinear harmonic cancellation, the image signal and nonlinear harmonics within the 2f b bandwidth are canceled, only the effective signal, the output signal bandwidth can reach 40% of the output signal sampling rate f s .

采用归零保持函数的DA芯片,输出包络频谱具有平缓的滚降特性。采用两路DA归零保持函数的输出信号进行叠加,两路DA时钟相位相差180度,在采样时钟的上升沿有第一DA芯片输出的DDS数据偶数采样点的信号,第二DA芯片的信号为0;下降沿有第二DA芯片输出的DDS数据奇数采样点的信号输出,第一DA芯片的信号为0,等效于两倍采样率的DA零阶保持函数的输出信号。Using a DA chip with a return-to-zero hold function, the output envelope spectrum has a gentle roll-off characteristic. The output signals of the two-way DA return-to-zero hold function are used to superimpose the two-way DA clock phase difference by 180 degrees. On the rising edge of the sampling clock, there is the signal of the even sampling point of the DDS data output by the first DA chip, and the signal of the second DA chip. is 0; the falling edge has the signal output of the odd sampling point of DDS data output by the second DA chip, and the signal of the first DA chip is 0, which is equivalent to the output signal of the DA zero-order hold function with twice the sampling rate.

通道调理模块包括低通滤波和幅度控制两部分。低通滤波滤除带宽外的杂散信号。幅度控制包括衰减、放大和直流偏置,使输出信号满足幅度和偏置的要求。最后将信号输出到装置外。The channel conditioning module includes low-pass filtering and amplitude control. Low-pass filtering filters out spurious signals outside the bandwidth. Amplitude control includes attenuation, amplification and DC offset, so that the output signal meets the requirements of amplitude and offset. Finally, the signal is output to the outside of the device.

时钟模块为存储管理模块、并行信号发生模块和时域交织模块提供时钟。The clock module provides clocks for the storage management module, the parallel signal generation module and the time domain interleaving module.

上述虽然结合附图对本发明的具体实施方式进行了描述,但并非对本发明保护范围的限制,所属领域技术人员应该明白,在本发明的技术方案的基础上,本领域技术人员不需要付出创造性劳动即可做出的各种修改或变形仍在本发明的保护范围以内。Although the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, they do not limit the scope of protection of the present invention. Those skilled in the art should understand that on the basis of the technical solutions of the present invention, those skilled in the art do not need to pay creative efforts. Various modifications or deformations that can be made are still within the protection scope of the present invention.

Claims (7)

1.一种基于DA归零保持函数的时域交织任意波形合成装置,其特征是:包括控制器、并行信号发生模块、时域交织模块和通道调理模块,所述时域交织模块包括两个采用归零保持函数的DA芯片,其中:1. a time domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function, is characterized in that: comprise controller, parallel signal generation module, time domain interleaving module and channel conditioning module, and described time domain interleaving module comprises two A DA chip with a return-to-zero hold function, where: 所述控制器将波形数据传输到并行信号发生模块,所述并行信号发生模块,在一个采样时钟的上升沿同时产生波形的多个输出相位,通过输出的多个相位值同时对波形查找表寻址,获取相应的DDS数据,将DDS波形数据的偶数采样点数据传输到采用归零保持函数的第一DA芯片,将奇数采样点数据传输到采用归零保持函数的第二DA芯片,两路DA芯片输出的模拟信号经过阻抗匹配、精密延时调整和信号叠加实现两路模拟信号的矢量相加,通道调理模块对相加后的模拟信号进行调理,形成最终的合成结果;The controller transmits the waveform data to the parallel signal generation module, and the parallel signal generation module simultaneously generates multiple output phases of the waveform at the rising edge of a sampling clock, and searches the waveform look-up table simultaneously through the output multiple phase values. address, obtain the corresponding DDS data, transmit the data of the even sampling points of the DDS waveform data to the first DA chip using the return-to-zero hold function, and transmit the odd-numbered sampling point data to the second DA chip using the return-to-zero hold function. The analog signal output by the DA chip realizes the vector addition of two analog signals after impedance matching, precise delay adjustment and signal superposition, and the channel conditioning module adjusts the added analog signal to form the final synthesis result; 所述采用归零保持函数的DA芯片,输出包络频谱具有平缓的滚降特性;The DA chip using the return-to-zero hold function has a gentle roll-off characteristic of the output envelope spectrum; 在采样时钟的上升沿有第一DA芯片输出的DDS数据偶数采样点的信号,第二DA芯片的信号为0;下降沿有第二DA芯片输出的DDS数据奇数采样点的信号输出,第一DA芯片的信号为0,等效于两倍采样率的DA零阶保持函数的输出信号;On the rising edge of the sampling clock, the signal of the even sampling point of DDS data output by the first DA chip is output, and the signal of the second DA chip is 0; The signal of the DA chip is 0, which is equivalent to the output signal of the DA zero-order hold function with twice the sampling rate; 对叠加后的保持函数进行傅里叶变换得到输出信号的频谱包络函数为:The spectral envelope function of the output signal is obtained by performing Fourier transform on the superimposed holding function:
Figure FDA0002163712710000011
Figure FDA0002163712710000011
其中,Ts为波形数据的采样周期;Among them, T s is the sampling period of waveform data; 所述时域交织模块包括两路DA芯片、阻抗匹配网络、精密延时模块和矢量叠加模块,分别对DDS数据偶数采样点和奇数采样点数据进行数模转换,阻抗匹配网络降低两路DA芯片输出信号之间的幅度失调,精密延时模块用于调整两路DA芯片输出信号之间的时序失调,矢量叠加模块用于两路DA输出信号的叠加合成;The time-domain interleaving module includes two DA chips, an impedance matching network, a precision delay module and a vector superposition module, which respectively perform digital-to-analog conversion on the data of the even sampling points and odd sampling points of the DDS data, and the impedance matching network reduces the two-way DA chips. The amplitude imbalance between the output signals, the precision delay module is used to adjust the timing imbalance between the output signals of the two DA chips, and the vector superposition module is used for the superposition and synthesis of the two DA output signals; 所述通道调理模块包括低通滤波模块和幅度控制模块,所述低通滤波模块滤除带宽外的杂散信号,幅度控制模块进行衰减、放大和直流偏置处理,使输出信号满足幅度和偏置的要求。The channel conditioning module includes a low-pass filter module and an amplitude control module, the low-pass filter module filters out spurious signals outside the bandwidth, and the amplitude control module performs attenuation, amplification and DC bias processing to make the output signal meet the amplitude and bias. set requirements.
2.如权利要求1所述的一种基于DA归零保持函数的时域交织任意波形合成装置,其特征是:所述的两路DA的采样时钟频率均为采样率的一半,相位相差180度。2. a kind of time-domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function as claimed in claim 1, it is characterized in that: the sampling clock frequency of described two-way DA is half of the sampling rate, and the phase difference is 180 Spend. 3.如权利要求1所述的一种基于DA归零保持函数的时域交织任意波形合成装置,其特征是:所述控制器通过存储管理模块连接并行信号发生模块,所述存储管理模块接收波形数据,并将其存储值大容量存储器中,存储完毕后,按照有效数据传输速率通过高速串行总线将波形数据传输到并行信号发生模块。3. a kind of time-domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function as claimed in claim 1, is characterized in that: described controller connects parallel signal generation module by storage management module, and described storage management module receives The waveform data is stored in the large-capacity memory. After the storage is completed, the waveform data is transmitted to the parallel signal generation module through the high-speed serial bus according to the effective data transmission rate. 4.如权利要求3所述的一种基于DA归零保持函数的时域交织任意波形合成装置,其特征是:所述有效数据传输速率为波形数据的采样率与DA芯片的垂直分辨率的乘积。4. a kind of time-domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function as claimed in claim 3, it is characterized in that: described effective data transmission rate is the sampling rate of waveform data and the vertical resolution of DA chip product. 5.如权利要求1所述的一种基于DA归零保持函数的时域交织任意波形合成装置,其特征是:所述并行信号发生模块,包括相位累加器,所述相位累加器连接多路相位加法器,每个相位加法器配备有波形查找表进行寻址,获取相应的DDS数据,所有DDS数据均传输给并串转换模块;所述相位累加器还连接有提供时钟频率的时钟单元。5. a kind of time-domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function as claimed in claim 1, is characterized in that: described parallel signal generation module, comprises phase accumulator, and described phase accumulator is connected with multiplex Phase adder, each phase adder is equipped with a waveform look-up table for addressing, obtains corresponding DDS data, and all DDS data are transmitted to the parallel-serial conversion module; the phase accumulator is also connected with a clock unit that provides a clock frequency. 6.如权利要求1所述的一种基于DA归零保持函数的时域交织任意波形合成装置,其特征是:叠加后的信号在采样时钟上升沿的和下降沿均有信号输出,等效为一路零阶保持函数的DA的信号输出,其采样率是第一DA芯片和第二DA芯片的两倍。6. a kind of time-domain interleaving arbitrary waveform synthesis device based on DA return-to-zero hold function as claimed in claim 1, it is characterized in that: the signal after the superposition has signal output at sampling clock rising edge and falling edge, equivalent It is a signal output of a DA of a zero-order hold function, and its sampling rate is twice that of the first DA chip and the second DA chip. 7.一种利用权利要求1-6任一项所述的基于DA归零保持函数的时域交织任意波形合成装置的波形合成方法,其特征是:包括以下步骤:7. a waveform synthesis method utilizing the time domain interleaving arbitrary waveform synthesis device based on the DA return-to-zero hold function according to any one of claims 1-6, is characterized in that: comprise the following steps: (1)根据用户的波形参数设置,产生任意波形数据;(1) Generate arbitrary waveform data according to the user's waveform parameter settings; (2)通过采样率和垂直分辨率计算得到数据读取速度,根据读取速度读取波形数据,得到DDS波形数据;(2) The data reading speed is obtained by calculating the sampling rate and vertical resolution, and the waveform data is read according to the reading speed to obtain the DDS waveform data; (3)将DDS波形数据的偶数采样点数据传输到采用归零保持函数的第一DA芯片,将奇数采样点数据传输到采用归零保持函数的第二DA芯片,两路DA芯片输出的模拟信号经过阻抗匹配、精密延时调整和信号叠加实现两路模拟信号的矢量相加;(3) The even sampling point data of the DDS waveform data is transmitted to the first DA chip using the return-to-zero hold function, the odd-numbered sampling point data is transmitted to the second DA chip using the return-to-zero hold function, and the analog output of the two DA chips The signal is subjected to impedance matching, precise delay adjustment and signal superposition to realize the vector addition of two analog signals; (4)对相加后的模拟信号进行滤波和控制信号幅度,得到输出波形。(4) Filter and control the amplitude of the added analog signal to obtain an output waveform.
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