CN217135473U - Audio digital-to-analog conversion circuit - Google Patents

Abstract

The utility model discloses an audio digital-to-analog conversion circuit, the circuit adopts new audio DAC framework, has optimized a large amount of multiplication and addition operations, combinational logic and register in traditional framework, has reduced hardware area and design complexity greatly; meanwhile, the limitation of strict requirements on the working clock frequency of the audio DAC circuit is solved, the audio with different sampling rates can be supported, and the application and design are more flexible.

Description

Audio digital-to-analog conversion circuit

Technical Field

The utility model relates to a DAC digital circuit design field, concretely relates to audio frequency digital analog conversion circuit.

Background

The typical audio DAC circuit is large in area and power consumption, only supports sampling rates which are based on three fundamental frequencies of 32k, 44.1k and 48k, and cannot support other sampling rates well. Due to this specific sampling rate, the operating clock of this typical design must be a clock source that can separate the three fundamental frequencies or the power of 2 frequency values thereof, such as a clock source with typical values of 24.576M (for separating 48K and 32K) and 22.5792MHz (for separating 44.1K). The typical audio DAC circuit has too strict requirements on the clock source and poor compatibility.

SUMMERY OF THE UTILITY MODEL

In order to solve the problem, the utility model provides an audio frequency digital-to-analog conversion circuit has solved the restriction to the strict requirement of audio frequency DAC circuit working clock frequency to can support the audio frequency of different sampling rates, it is more nimble in the application and the design. The utility model discloses a concrete technical scheme as follows:

an audio digital-to-analog conversion circuit, the circuit comprising: the read-write control module is used for receiving the APB bus signal and outputting a write enable signal and a first frequency division parameter of the asynchronous FIFO module; the clock frequency division module is connected with the read-write control module and used for receiving a working clock of the audio digital-to-analog conversion circuit and a first frequency division parameter output by the read-write control module and outputting a read enabling signal of the asynchronous FIFO module with synchronous phases and a data processing enabling signal of the CIC filter; the asynchronous FIFO module is respectively connected with the read-write control module and the clock frequency division module and is used for performing data interaction processing between two different clock domains of a clock for writing data and a clock for reading data; and the CIC filter is respectively connected with the clock frequency division module and the asynchronous FIFO module and is used for reading out data from the asynchronous FIFO module according to the read enabling signal of the asynchronous FIFO module with synchronous phase and the data processing enabling signal of the CIC filter and filtering the data. Compared with the prior art, the technical scheme adopts a new audio DAC architecture, optimizes a large amount of multiply-add operations, combinational logic and registers in the traditional architecture, and greatly reduces the hardware area and the design complexity; meanwhile, the limitation of strict requirements on the working clock frequency of the audio DAC circuit is solved, the audio with different sampling rates can be supported, and the application and design are more flexible.

Furthermore, the audio digital-to-analog conversion circuit further comprises a data transmission module and a digital-to-analog conversion module, wherein the data transmission module is used for transmitting data to the asynchronous FIFO module, and the digital-to-analog conversion module is used for receiving the data filtered by the CIC filter and converting the data into an analog signal.

Further, the data transmission module comprises a CPU controller, a DMA controller, and a data selector, wherein the CPU controller and the DMA controller are respectively connected to the data selector, and the data selector selects data of the CPU controller or the DMA controller to the asynchronous FIFO module through a data selection signal provided by the read-write control module.

Furthermore, the data selection signal provided by the read-write control module is an interrupt signal or a request signal of the audio digital-to-analog conversion circuit; when the selection signal is an interrupt signal, the data of the CPU controller is selected to the asynchronous FIFO module, and when the selection signal is a request signal, the data of the DMA controller is selected to the asynchronous FIFO module.

Further, the clock division module includes: the divider is connected with the read-write control module and used for receiving the first frequency division parameter and carrying out division operation to obtain a second frequency division parameter; wherein, the dividend is a preset value; the first counter is connected with the divider and used for counting the working clock according to the second frequency division parameter to obtain a first counting sequence; the first register is connected with the first counter and used for dividing the frequency of the working clock according to the first counting sequence to obtain a data processing enabling signal and a frequency value of the CIC filter; the second counter is connected with the first register and used for counting the data processing enabling signal of the CIC filter according to the preset value to obtain a second counting sequence; the second register is connected with the first register and used for delaying the data processing enabling signal of the CIC filter to obtain a delay enabling signal; the third register is respectively connected with the second counter and the second register and is used for carrying out frequency division on the working clock according to the second counting sequence and the delay enabling signal to obtain a reading enabling signal and a frequency value of the asynchronous FIFO module; wherein, the data processing enable signal of the CIC filter and the read enable signal of the asynchronous FIFO module are synchronous in phase. Compared with the prior art, the technical scheme can correctly generate the sampling rate of the original audio data by dividing the frequency of the working clock, thereby supporting various audio data sources with different sampling rates; the third register divides the frequency of the working clock according to the second counting sequence and the delay enabling signal, so that a data processing enabling signal of the CIC filter and a reading enabling signal of the asynchronous FIFO module can keep synchronous, phase deviation is avoided, and the CIC filter is ensured to correctly acquire data in the asynchronous FIFO module.

Further, the first counter counts the rising edges of the working clock, and the counter is reset to zero every time the counted number reaches the value of the second frequency dividing parameter.

Further, the second counter counts the rising edges of the data processing enable signals of the CIC filter, and the counter is reset to zero every time the counted number reaches a preset value.

Further, the first register sets the data processing enable signal of the CIC filter to be at a high level at each previous zero-reset value in the first counting sequence, and sets the data processing enable signal of the CIC filter to be at a low level in other cases, wherein the frequency value is a quotient of the operating clock and the second frequency-dividing parameter. And generating a data processing enabling signal of the CIC filter to perform oversampling on the data and improve the quality of the data.

Further, the third register is arranged at each zero resetting position in the second counting sequence, and when the delay enable signal is at a high level, the read enable signal of the asynchronous FIFO module is set to be at a high level, and otherwise, the read enable signal is set to be at a low level, and the frequency value of the third register is the quotient of the working clock and the first frequency-dividing parameter. The read enable signal of the asynchronous FIFO module is generated to ensure that data interaction processing is correctly carried out between two different clock domains of a clock for writing data and a clock for reading data.

Furthermore, the delay time of the second register to the data processing enable signal of the CIC filter is a preset number of working clock cycles. The data processing enable signal of the CIC filter and the read enable signal of the asynchronous FIFO module can be ensured to be synchronous without generating phase deviation.

Furthermore, the output of the read-write control module further includes an audio digital-to-analog conversion circuit enable signal and a reset signal, which are used as the input of the clock frequency division module.

Drawings

Fig. 1 is a schematic diagram of a typical audio DAC circuit.

Fig. 2 is a schematic diagram of an embodiment of the audio digital-to-analog conversion circuit of the present invention.

Fig. 3 is a schematic diagram of the clock divider module according to an embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the following description of specific embodiments is illustrative only and is not intended to limit the invention.

In the following description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood by those of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the embodiments.

A typical audio DAC circuit shown in fig. 1 has large area and large power consumption, and only supports sampling rates based on 3 fundamental frequencies (32 k, 44.1k, and 48 k), but cannot support other sampling rates well. Due to this particular sampling rate, the operating clock of this typical design must be a clock source that can tap the three fundamental frequencies or their 2-power frequency values, such as a clock source with typical values of 24.576M (for taps 48K and 32K) and 22.5792MHz (for taps 44.1K). The typical audio DAC circuit has too strict requirements on the clock source and poor compatibility.

Therefore, an embodiment of the present invention provides an audio digital-to-analog conversion circuit, as shown in fig. 2, the circuit includes:

and the read-write control module is used for receiving the APB bus signal, the APB bus is used for connecting peripheral equipment, and then the write enable signal and the first frequency division parameter of the asynchronous FIFO module are output. The first frequency-division parameter is configured by peripheral equipment, and the peripheral equipment obtains the first frequency-division parameter by quotient after obtaining a working clock of the audio digital-to-analog conversion circuit and a sampling rate of audio data, wherein the sampling rates of the working clock and the audio data are known parameters. The read-write control module is a module built by register read-write modules with different addresses, and register values of all the addresses are configured by operating APB bus signals. The APB bus is one of AMBA bus protocols, which is a commonly used bus protocol, and its usage method is roughly as follows: the APB bus has PCLK/PSEL/PENABLE/PWRITE/PADDR/PRDATA/PWDATA/PRESET and other signals, when PENABLE, PSEL and PWRITE are 1 at the same time, when PCLK rising edge arrives, PWDATA value is written into PADDR, namely WDATA value is written into the register read-write module with address as ADDR; conversely, when PENABLE, PSEL, PWRITE are 0 at the same time, the PRDATA value in PADDR is read, i.e., the value in the register read-write module with address ADDR is read, when PCLK rising edge arrives. The data input and output in the read-write control module are realized in the mode.

And the clock frequency division module is connected with the read-write control module and used for receiving the working clock of the audio digital-to-analog conversion circuit and the first frequency division parameter output by the read-write control module and outputting a read enabling signal of the asynchronous FIFO module with synchronous phase and a data processing enabling signal of the CIC filter. As shown in fig. 3, the clock division module includes:

and the divider is connected with the read-write control module and used for receiving the first frequency division parameter and carrying out division operation to obtain a second frequency division parameter. The dividend is a preset value, and specifically refers to an oversampling rate of the CIC filter. Preferably, the oversampling ratio is set to 8.

And the first counter is connected with the divider and used for counting the working clock according to the second frequency division parameter to obtain a first counting sequence. The first counter starts counting from 0, 1 is added when the rising edge of the working clock, and the counter is reset to zero when the counted number reaches the value of the second frequency dividing parameter.

And the first register is connected with the first counter and is used for dividing the frequency of the working clock according to the first counting sequence to obtain a data processing enabling signal and a frequency value of the CIC filter. And setting the data processing enabling signal of the CIC filter to be high level 1 at each previous zero-reset value in the first counting sequence, and setting the data processing enabling signal of the CIC filter to be low level 0 in other cases, wherein the frequency value is the quotient of the working clock and the second frequency dividing parameter. It should be noted that, when the reset signal is 0 or the audio digital-to-analog conversion circuit enable signal is 0, the data processing enable signal of the CIC filter is also 0. The reset signal is 0, which indicates that the audio digital-to-analog conversion circuit is reset, and the enable signal of the audio digital-to-analog conversion circuit is 0, which indicates that the audio digital-to-analog conversion circuit is not in a working state. The reset signal and the audio digital-to-analog conversion circuit enable signal are used as the output of the read-write control module and are respectively transmitted to the first counter, the first register, the second counter and the third register.

And the second counter is connected with the first register and used for counting the data processing enabling signal of the CIC filter according to the preset value to obtain a second counting sequence. The second counter starts counting from 0, 1 is added when the rising edge of the working clock, and the counter is reset to zero when the counted number reaches a preset value.

And the second register is connected with the first register and used for delaying the data processing enabling signal of the CIC filter to obtain a delay enabling signal. And the delay time of the second register to the data processing enabling signal of the CIC filter is a preset number of working clock cycles. Preferably, delaying the data processing enable signal of the CIC filter by 1 cycle of the working clock can align the read enable signal of the asynchronous FIFO module output by the third register with the rising edge of the data processing enable signal of the CIC filter.

And the third register is respectively connected with the second counter and the second register and is used for carrying out frequency division on the working clock according to the second counting sequence and the delay enabling signal to obtain a read enabling signal and a frequency value of the asynchronous FIFO module. And at each zero resetting position in the second counting sequence, when the delay enable signal is at a high level, setting the read enable signal of the asynchronous FIFO module to be at a high level 1, and setting the read enable signal of the asynchronous FIFO module to be at a low level 0 in other cases, wherein the frequency value is the quotient of the working clock and the first frequency division parameter. Similarly, when the reset signal is 0 or the audio dac enable signal is 0, the read enable signal of the asynchronous FIFO module is also 0. It should be noted that the frequency value of the read enable signal of the asynchronous FIFO module is equal to the sampling rate of the audio data, so that the asynchronous FIFO module can accurately read the audio data in two different clock domains.

In addition, the design of the clock frequency division module also enables a data processing enabling signal of the CIC filter and a reading enabling signal of the asynchronous FIFO module to keep synchronous without phase deviation, otherwise, the CIC filter can make mistakes due to the fact that the data of the asynchronous FIFO module cannot be acquired. The design of the clock frequency division module ensures the synchronization of the two signals and supports data processing under a small range of sampling rate errors.

And the asynchronous FIFO module is respectively connected with the read-write control module and the clock frequency division module and is used for performing data interaction processing between two different clock domains of a clock for writing data and a clock for reading data. This module is a common module and is not described in detail.

And the CIC filter is respectively connected with the clock frequency division module and the asynchronous FIFO module and is used for reading out data from the asynchronous FIFO module according to the read enabling signal of the asynchronous FIFO module with synchronous phase and the data processing enabling signal of the CIC filter and filtering the data. The CIC filter is also called an integrating-cascading-comb filter, which is the most preferable one of FIR filters, and uses a cascading manner of integrating and comb filters. In the interpolation CIC filter, the input signal passes through a comb filter, oversampling, and the same number of integration elements as the comb in sequence. The oversampling ratio may be 8, 16, 32, 64, etc., and preferably, the oversampling ratio is set to 8. The CIC filter performs interpolation and integration on the read data in the asynchronous FIFO module, so that the finally output data is smoother on a time domain waveform, and the performances such as signal-to-noise ratio, total harmonic distortion and the like are improved.

Referring to fig. 2, the audio digital-to-analog conversion circuit further includes a data transmission module and a digital-to-analog conversion module.

The data transmission module is used for transmitting data to the asynchronous FIFO module and comprises a CPU controller, a DMA controller and a data selector. The CPU controller and the DMA controller are respectively connected with the data selector, and the data selector selects data of the CPU controller or the DMA controller to the asynchronous FIFO module through a data selection signal provided by the read-write control module, namely the asynchronous FIFO module has two data sources. The data selection signal provided by the read-write control module is an interrupt signal or a request signal of the audio digital-to-analog conversion circuit, when the selection signal is the interrupt signal, the data of the CPU controller is selected to the asynchronous FIFO module, and when the selection signal is the request signal, the data of the DMA controller is selected to the asynchronous FIFO module.

And the digital-to-analog conversion module is used for receiving the data filtered by the CIC filter and converting the data into an analog signal. Use audio frequency digital analog conversion circuit can be close to and play out source audio data lossless ground. Compared with the prior art, the embodiment of the utility model adopts a new audio DAC framework, optimizes a large amount of multiply-add operations, combinational logic and registers in the traditional framework, and greatly reduces the hardware area and the design complexity; meanwhile, the limitation of strict requirements on the working clock frequency of the audio DAC circuit is solved, the audio with different sampling rates can be supported, and the application and design are more flexible.

The audio digital-to-analog conversion circuit of the present invention will be further described with reference to specific examples.

The parameters of the original audio data received by the asynchronous FIFO module from the CPU controller or the DMA controller are Fin =1KHz, Fs =11.025K, and ENOB =12bit, where Fin represents the frequency of the audio data, Fs represents the sampling rate of the audio data, and ENOB represents the effective bit width of the signal.

First, the peripheral device calculates a first frequency-division parameter DAC _ D2A _ CLK _ SCAL from the operating clock DAC _ CLK and the audio data sampling rate Fs. The operating clock DAC CLK is an external clock source, and its frequency values are not limited to the typical values of 24.576M and 22.5792 MHz. It should be emphasized that the input clock source of the clock divider module can be changed, the design of the module does not depend on a specific clock frequency, i.e. the clock divider module can work normally no matter what kind of clock source is, and the whole audio digital-to-analog conversion circuit can also work normally. Preferably, the operating clock selects a clock source with a frequency greater than 20 MHz. Preferably, in this embodiment, the operating clock is a 48MHz clock source, and this relatively common clock frequency value has the advantage of sharing a clock with other modules in the SOC project, so as to save the resource occupation of the clock module without affecting the performance of the audio digital-to-analog conversion circuit. Thus, the first frequency-division parameter DAC _ D2A _ CLK _ SCAL = DAC _ CLK/Fs =48M/11.025K = 4353. The divider calculates a second frequency division parameter CIC _ CLK _ SCAL = DAC _ D2A _ CLK _ SCAL/OSR =4353/8=544 upon receiving the first frequency division parameter DAC _ D2A _ CLK _ SCAL, where OSR represents the oversampling ratio of the CIC filter.

Subsequently, the first counter counts the operating clock DAC _ CLK, counts from 0 to 543 and then from 0 every rising edge, and so on to obtain a first count sequence CIC _ CLK _ SCAL _ CNT. Every time the CIC _ CLK _ SCAL _ CNT counts to 543, the DATA processing enable signal CIC _ DATA _ EN of the CIC filter is set to high level 1, and the DATA processing enable signal CIC _ DATA _ EN = DAC _ CLK/CIC _ CLK _ SCAL =48M/544=88.2K of the CIC filter is obtained.

The DATA processing enable signal CIC _ DATA _ EN of the CIC filter is then counted, the second counter counts from 0 to 7 and then from 0, and so on to obtain a second count sequence CNT _ CIC _ EN. Meanwhile, the second register delays the DATA processing enable signal CIC _ DATA _ EN of the CIC filter by one cycle of the working clock DAC _ CLK to obtain a delayed enable signal CIC _ DATA _ EN _ 1T. Whenever CNT _ CIC _ EN =0 and CIC _ DATA _ EN _1T =1, the read enable signal AFIFO _ REN of the asynchronous FIFO module is set to high level 1, and the read enable signal AFIFO _ REN of the asynchronous FIFO module = DAC _ CLK/CIC _ CLK _ SCAL/8=48M/544/8=11.025K is obtained. It can be seen that the read enable signal AFIFO _ REN of the asynchronous FIFO module is consistent with the sampling rate Fs of the audio data, and the clock frequency division module restores Fs. Preferably, support for audio sampling rates in the 11.025K-1M continuous range is well achieved.

It should be emphasized that counting and delaying the DATA processing enable signal CIC _ DATA _ EN can keep the DATA processing enable signal CIC _ DATA _ EN of the CIC filter and the read enable signal AFIFO _ REN of the asynchronous FIFO module synchronized without phase deviation, otherwise the CIC filter will be in error due to not collecting DATA of the asynchronous FIFO module.

And finally, the CIC filter utilizes CIC _ DATA _ EN and AFIFO _ REN to perform interpolation and integration processing on the DATA of the asynchronous FIFO module, so that the quality of the audio DATA is improved, and the fidelity of the audio played by the digital-to-analog conversion module is higher.

Obviously, the embodiments described above are only a part of the embodiments of the present invention, and not all embodiments, and the technical solutions between the embodiments may be combined with each other. Furthermore, if terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear in the embodiments, their indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention. If the terms "first", "second", "third", etc. appear in the embodiments, they are for convenience of distinguishing between related features, and they are not to be construed as indicating or implying any relative importance, order or number of features.

In addition, in the description of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. These programs may be stored in a computer-readable storage medium (such as a ROM, a RAM, a magnetic or optical disk, or various other media that can store program codes). Which when executed performs steps comprising the method embodiments described above.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims (11)

1. Audio digital-to-analog conversion circuitry, said circuitry comprising:

the read-write control module is used for receiving the APB bus signal and outputting a write enable signal and a first frequency division parameter of the asynchronous FIFO module;

the clock frequency division module is connected with the read-write control module and used for receiving a working clock of the audio digital-to-analog conversion circuit and a first frequency division parameter output by the read-write control module and outputting a read enabling signal of the asynchronous FIFO module with synchronous phases and a data processing enabling signal of the CIC filter;

the asynchronous FIFO module is respectively connected with the read-write control module and the clock frequency division module and is used for performing data interaction processing between two different clock domains of a clock for writing data and a clock for reading data;

and the CIC filter is respectively connected with the clock frequency division module and the asynchronous FIFO module and is used for reading out data from the asynchronous FIFO module according to the read enabling signal of the asynchronous FIFO module with synchronous phase and the data processing enabling signal of the CIC filter and filtering the data.

2. The audio dac circuit of claim 1 further comprising a data transmission module and a digital-to-analog conversion module, wherein the data transmission module is configured to transmit data to the asynchronous FIFO module, and the digital-to-analog conversion module is configured to receive the data filtered by the CIC filter and convert the data into an analog signal.

3. The audio digital-to-analog conversion circuit according to claim 2, wherein the data transmission module comprises a CPU controller, a DMA controller, and a data selector, wherein the CPU controller and the DMA controller are respectively connected to the data selector, and the data selector selects data of the CPU controller or the DMA controller to the asynchronous FIFO module through a data selection signal provided by the read-write control module.

4. The audio DAC circuit of claim 3, wherein the data selection signal provided by the read/write control module is an interrupt signal or a request signal of the audio DAC circuit; when the selection signal is an interrupt signal, the data of the CPU controller is selected to the asynchronous FIFO module, and when the selection signal is a request signal, the data of the DMA controller is selected to the asynchronous FIFO module.

5. The audio digital-to-analog conversion circuit of claim 1, wherein the clock division module comprises:

the divider is connected with the read-write control module and used for receiving the first frequency division parameter and carrying out division operation to obtain a second frequency division parameter; wherein, the dividend is a preset value;

the first counter is connected with the divider and used for counting the working clock according to the second frequency division parameter to obtain a first counting sequence;

the first register is connected with the first counter and used for dividing the frequency of the working clock according to the first counting sequence to obtain a data processing enabling signal and a frequency value of the CIC filter;

the second counter is connected with the first register and used for counting the data processing enabling signal of the CIC filter according to the preset value to obtain a second counting sequence;

the second register is connected with the first register and used for delaying the data processing enabling signal of the CIC filter to obtain a delay enabling signal;

the third register is respectively connected with the second counter and the second register and is used for carrying out frequency division on the working clock according to the second counting sequence and the delay enabling signal to obtain a reading enabling signal and a frequency value of the asynchronous FIFO module;

wherein, the data processing enable signal of the CIC filter and the read enable signal of the asynchronous FIFO module are synchronous in phase.

6. The audio DAC circuit of claim 5 wherein the first counter counts the rising edges of the operating clock and resets to zero each time the count reaches the value of the second frequency-dividing parameter.

7. The audio DAC circuit of claim 5 wherein the second counter counts the rising edges of the CIC filter data processing enable signal and resets to zero each time the number of counts reaches a predetermined value.

8. The audio DAC circuit of claim 5 wherein the first register sets the CIC filter data processing enable signal high at each previous zero value in the first count sequence and low at the other times, the frequency value being the quotient of the operating clock and the second frequency-dividing parameter.

9. The audio DAC circuit of claim 5 wherein the third register is at each zero in the second count sequence, and wherein the read enable signal of the asynchronous FIFO module is set to high when the latency enable signal is high, and the read enable signal of the asynchronous FIFO module is set to low when the latency enable signal is high, and the frequency value is the quotient of the operating clock and the first frequency-division parameter.

10. The audio DAC circuit of claim 5, wherein the delay time of the second register for the data processing enable signal of the CIC filter is a preset number of working clock cycles.

11. The audio digital-to-analog conversion circuit of claim 1, wherein the output of the read-write control module further comprises an audio digital-to-analog conversion circuit enable signal and a reset signal for being input to the clock divider module.

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