CN115276704B - Up-conversion link system and device suitable for broadband digital TR chip - Google Patents
Up-conversion link system and device suitable for broadband digital TR chip Download PDFInfo
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- CN115276704B CN115276704B CN202210795541.2A CN202210795541A CN115276704B CN 115276704 B CN115276704 B CN 115276704B CN 202210795541 A CN202210795541 A CN 202210795541A CN 115276704 B CN115276704 B CN 115276704B
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
- H04B1/0096—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges where a full band is frequency converted into another full band
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The application provides an up-conversion link system and a device suitable for a broadband digital TR chip, wherein the system comprises: the control word analysis unit is used for carrying out data analysis on the control word information received from the external system; a waveform generation unit for generating a waveform signal according to the waveform type; an external waveform receiving and storing unit for receiving and storing external waveform data; the data processing unit is connected with the control word analysis unit and the waveform generation unit and is used for carrying out amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signals; and the DAC IP core unit is connected with the data processing unit and is used for carrying out digital-to-analog conversion on the waveform signals. The application solves the problem that the existing digital TR chip can not meet the generation requirement of broadband waveform data, and overcomes the defects of high cost and large area caused by the large-scale use of the FPGA chip.
Description
Technical Field
The application relates to the technical field of digital-analog hybrid chip design, in particular to an up-conversion link system and device suitable for a broadband digital TR chip.
Background
With the development of digital technology, the digital TR module (Transmitter and Receiver, transceiver module) is increasingly applied to radar, satellite communication and other systems, and plays an important role. With the continuous improvement of radar bandwidth and the development of high-speed signal processing technology, radar systems have higher demands on the speed and efficiency of mass data transmission, and due to the number of array units, the adoption of traditional digital components based on FPGA to complete digital array transceiving can bring about the problems of high cost and large volume.
Disclosure of Invention
The invention aims to overcome the technical defects, provide an up-conversion link system and device suitable for a broadband digital TR chip, and solve the technical problems of high cost and large volume caused by completing digital array transceiving by a traditional digital assembly based on an FPGA in the prior art.
To achieve the above technical object, in a first aspect, the present invention provides an up-conversion link system applicable to a wideband digital TR chip, including:
the control word analysis unit is used for carrying out data analysis on the control word information received from the external system to obtain the waveform type and the working mode information required by the up-conversion link operation;
The waveform generation unit is connected with the control word analysis unit and generates a waveform signal according to the waveform type;
the external waveform receiving and storing unit is connected with the control word analyzing unit and the waveform generating unit and is used for receiving and storing external waveform data;
the data processing unit is connected with the control word analysis unit and the waveform generation unit and is used for carrying out amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signals;
and the DAC IP core unit (Digital to analog converter, digital-to-analog converter) is connected with the data processing unit and is used for performing digital-to-analog conversion on the waveform signals.
Compared with the prior art, the invention has the beneficial effects that:
the up-conversion link system suitable for the broadband digital TR chip provided by the technical scheme of the invention can effectively reduce the system cost and the chip area under the condition of realizing 640Msps sampling rate by carrying out chip design on waveform generation and up-conversion and carrying out digital-analog hybrid integration on an analog DAC IP core, and has the advantages of low power consumption and high integration level. The invention solves the problem that the existing digital TR chip can not meet the generation requirement of broadband waveform data, and overcomes the defects of high cost and large area caused by the large-scale use of the FPGA chip.
According to some embodiments of the invention, the waveform generation unit includes:
the waveform code generation module is connected with the control word analysis unit and is used for generating the corresponding waveform signals according to the control word information analyzed by the control word analysis unit;
a Cordic (Coordinate Rotation Digital Computer, coordinate rotation digital computing method) waveform generation module connected to the waveform code generation module, the Cordic waveform generation module being configured to convert the waveform signal into an IQ quadrature signal (modulation signal for phase quadrature) of a corresponding frequency phase;
the NCO module (numerically controlled oscillator, digital control oscillator) is connected with the Cordic waveform generation module and is used for carrying out multiplication and addition operation on the IQ orthogonal signals to realize the frequency phase adjustment of waveforms;
and the amplitude adjusting module is used for adjusting the waveform amplitude of the IQ orthogonal signal and outputting the IQ orthogonal signal to the data processing unit.
According to some embodiments of the invention, the waveform generation unit further comprises:
The FIFO control module (First Input First Output, first-in first-out queue) is connected with the external waveform receiving and storing unit, and the waveform generating unit reads specified external waveform data from the external waveform receiving and storing unit according to the read-write control time sequence requirement of the FIFO control module;
the interpolation module is connected with the FIFO control module and the NCO module, and is used for carrying out interpolation processing on the external waveform data and outputting the external waveform data to the NCO module.
According to some embodiments of the invention, the waveform generation unit further comprises:
the sub-control word analysis module is connected with the control word analysis unit, the waveform code generation module, the interpolation module, the NCO module, the amplitude adjustment module and the FIFO control module, and is used for further analyzing the control word information analyzed by the control word analysis unit to obtain all configuration information required by final waveform generation.
According to some embodiments of the invention, the waveform code generation module includes at least any two of:
the device comprises a linear Frequency modulation module, a phase coding module, an FSK module (Frequency shift keying), a single carrier Frequency module and a non-linear Frequency modulation module.
According to some embodiments of the invention, the interpolation module comprises:
a configuration register for setting interpolation multiples of the external waveform data;
and the FIR filter (Finite Impulse Response, finite length unit impulse response filter) is used for carrying out filtering processing on the interpolated external waveform data so as to eliminate high-frequency noise generated by interpolation.
According to some embodiments of the invention, the data processing unit comprises:
the equalization filtering module is connected with the waveform generation unit and is used for performing equalization filtering processing on the IQ orthogonal signals output by the waveform generation unit so as to finish phase amplitude consistency compensation of the IQ orthogonal signals in a large bandwidth;
the anti-Sinc module is connected with the equalization filtering module and is used for carrying out anti-Sinc function processing on the IQ orthogonal signals so as to eliminate the amplitude inconsistency of a broadband during frequency conversion;
the decimal delay module is connected with the inverted Sinc module and is used for adjusting the clock period of the waveform group delay;
the IQ orthogonal correction and direct current offset module is connected with the decimal delay module and is used for carrying out orthogonal correction and direct current offset compensation on IQ signals;
And the Dither module is connected with the IQ orthogonal correction and direct current bias module and is used for reducing output spurious of the DAC due to quantization errors.
According to some embodiments of the invention, the fractional delay module comprises:
a coefficient storage ROM storing a normalized coefficient;
fine-tuning the fractional delay, connecting with the coefficient storage ROM;
a coarse fraction delay coupled to the coefficient store ROM and the fine fraction delay;
integer delay, connect with said coefficient memory ROM and said coarse adjustment decimal delay;
and the normalization multiplier is connected with the coefficient storage ROM and the integer delay.
According to some embodiments of the invention, the DAC IP core unit comprises:
the device comprises two paths of input latches, a time sequence generating circuit, a bias generating circuit and two paths of DAC cores, wherein the input latches are connected with the DAC cores, the time sequence generating circuit is arranged between the two paths of input latches, and the time sequence generating circuit and the bias generating circuit are connected between the two paths of DAC cores.
In a second aspect, the present invention provides an up-conversion link device applicable to a wideband digital TR chip, including: eight identical up-conversion channels provided with an up-conversion link system adapted for a wideband digital TR chip as claimed in any one of the first aspects.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the present invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings, in which the summary drawings are to be fully consistent with one of the drawings of the specification:
fig. 1 is a schematic diagram of an up-conversion link system suitable for a wideband digital TR chip according to an embodiment of the present invention;
fig. 2 is a diagram showing a waveform generation unit of an up-conversion link system applicable to a wideband digital TR chip according to another embodiment of the present invention;
FIG. 3 is a schematic diagram of an interpolation module of an up-conversion link system suitable for a broadband digital TR chip according to another embodiment of the present invention;
fig. 4 is a diagram showing an NCO module composition of an up-conversion link system applicable to a broadband digital TR chip according to another embodiment of the present invention;
fig. 5 is a diagram showing a data processing unit of an up-conversion link system applicable to a wideband digital TR chip according to another embodiment of the present invention;
fig. 6 is a diagram of a fractional delay module of an up-conversion link system applicable to a wideband digital TR chip according to another embodiment of the present invention;
FIG. 7 is a diagram of a dither module for an up-conversion link system for a broadband digital TR chip according to another embodiment of the present invention;
fig. 8 is a block diagram of an analog DAC IP core for an up-conversion link system for a broadband digital TR chip according to another embodiment of the present invention.
Reference numerals illustrate: the device comprises a control word analysis unit 110, a waveform generation unit 120, an external waveform receiving and storing unit 130, a data processing unit 140, a DAC IP core unit 150, a waveform code generation module 121, a Cordic waveform generation module 122, an NCO module 123 and an amplitude adjustment module 124.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
It should be noted that although functional block diagrams are depicted as block diagrams, and logical sequences are shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the block diagrams in the system. The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
The invention provides an up-conversion link system suitable for a broadband digital TR chip, which can effectively reduce the system cost and the chip area under the condition of realizing 640Msps sampling rate by carrying out chip design on waveform generation and up-conversion and carrying out digital-analog hybrid integration on an analog DAC IP core, and has the advantages of low power consumption and high integration level. The invention solves the problem that the existing digital TR chip can not meet the generation requirement of broadband waveform data, and overcomes the defects of high cost and large area caused by the large-scale use of the FPGA chip.
Embodiments of the present invention will be further described below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 is a schematic diagram of an up-conversion link system suitable for a wideband digital TR chip according to an embodiment of the present invention.
In one embodiment, an up-conversion link system suitable for a wideband digital TR chip includes: a control word parsing unit 110, configured to perform data parsing on control word information received from an external system, so as to obtain waveform type and operation mode information required for the operation of the up-conversion link; a waveform generation unit 120 connected to the control word analysis unit 110, the waveform generation unit 120 generating a waveform signal according to the waveform type; an external waveform receiving and storing unit 130 connected to the control word analyzing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analysis unit 110 and the waveform generation unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; the DAC IP core unit 150 is connected to the data processing unit 140, and the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
It can be understood that after the chip is powered on, the control word information is first sent to the up-conversion link system through the high-speed interface, and after the control word analysis unit 110 receives the control word, the control word is subjected to address data analysis to obtain configuration parameters of the up-conversion link system, and the configuration parameters are output to each unit to complete initialization configuration.
When the synchronous pulse signal arrives, the up-conversion link system starts to enter a working state, corresponding working waveforms are generated by the waveform unit according to a preset working mode or waveform data are directly written into the external waveform receiving and storing unit 130 by the external high-speed interface, the waveform data are processed and then output to the DAC IP core, the conversion from digital to analog signals is realized after the data pass through the DAC IP core, and finally the waveform data are output to the next stage of the component.
The control word parsing unit 110 recognizes the received high-speed data stream information, searches and aligns the synchronization header according to a specific digital protocol, then starts to parse the header, parses the subsequent data streams one by one according to the address, stores the parsed data streams in a register, and outputs the data streams to other units.
Referring to fig. 2, fig. 2 is a diagram showing a waveform generation unit 120 of an up-conversion link system suitable for a broadband digital TR chip according to another embodiment of the present invention.
In one embodiment, an up-conversion link system suitable for a wideband digital TR chip includes: a control word parsing unit 110, configured to perform data parsing on control word information received from an external system, so as to obtain waveform type and operation mode information required for the operation of the up-conversion link; a waveform generation unit 120 connected to the control word analysis unit 110, the waveform generation unit 120 generating a waveform signal according to the waveform type; an external waveform receiving and storing unit 130 connected to the control word analyzing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analysis unit 110 and the waveform generation unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; the DAC IP core unit 150 is connected to the data processing unit 140, and the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generation unit 120 includes: a plurality of waveform code generating modules 121 connected to the control word analyzing unit 110, the waveform code generating modules 121 being configured to generate corresponding waveform signals according to the control word information analyzed by the control word analyzing unit 110; the Cordic waveform generation module 122 is connected with the waveform code generation module 121, and the Cordic waveform generation module 122 is used for converting the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generation module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signals to realize the frequency phase adjustment of the waveform; the input end of the amplitude adjustment module 124 is connected with the NCO module 123, the output end is connected with the data processing unit 140, and the amplitude adjustment module 124 is used for adjusting waveform amplitude of the IQ quadrature signal and outputting the IQ quadrature signal to the data processing unit 140.
In one embodiment, an up-conversion link system suitable for a wideband digital TR chip includes: a control word parsing unit 110, configured to perform data parsing on control word information received from an external system, so as to obtain waveform type and operation mode information required for the operation of the up-conversion link; a waveform generation unit 120 connected to the control word analysis unit 110, the waveform generation unit 120 generating a waveform signal according to the waveform type; an external waveform receiving and storing unit 130 connected to the control word analyzing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analysis unit 110 and the waveform generation unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; the DAC IP core unit 150 is connected to the data processing unit 140, and the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generation unit 120 includes: a plurality of waveform code generating modules 121 connected to the control word analyzing unit 110, the waveform code generating modules 121 being configured to generate corresponding waveform signals according to the control word information analyzed by the control word analyzing unit 110; the Cordic waveform generation module 122 is connected with the waveform code generation module 121, and the Cordic waveform generation module 122 is used for converting the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generation module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signals to realize the frequency phase adjustment of the waveform; the input end of the amplitude adjustment module 124 is connected with the NCO module 123, the output end is connected with the data processing unit 140, and the amplitude adjustment module 124 is used for adjusting waveform amplitude of the IQ quadrature signal and outputting the IQ quadrature signal to the data processing unit 140.
The waveform generation unit 120 further includes: the FIFO control module is connected with the external waveform receiving and storing unit 130, and the waveform generating unit 120 reads specified external waveform data from the external waveform receiving and storing unit 130 according to the read-write control time sequence requirement of the FIFO control module; and the interpolation module is connected with the FIFO control module and the NCO module 123, and is used for carrying out interpolation processing on the external waveform data and outputting the external waveform data to the NCO module 123.
In one embodiment, an up-conversion link system suitable for a wideband digital TR chip includes: a control word parsing unit 110, configured to perform data parsing on control word information received from an external system, so as to obtain waveform type and operation mode information required for the operation of the up-conversion link; a waveform generation unit 120 connected to the control word analysis unit 110, the waveform generation unit 120 generating a waveform signal according to the waveform type; an external waveform receiving and storing unit 130 connected to the control word analyzing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analysis unit 110 and the waveform generation unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; the DAC IP core unit 150 is connected to the data processing unit 140, and the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generation unit 120 includes: a plurality of waveform code generating modules 121 connected to the control word analyzing unit 110, the waveform code generating modules 121 being configured to generate corresponding waveform signals according to the control word information analyzed by the control word analyzing unit 110; the Cordic waveform generation module 122 is connected with the waveform code generation module 121, and the Cordic waveform generation module 122 is used for converting the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generation module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signals to realize the frequency phase adjustment of the waveform; the input end of the amplitude adjustment module 124 is connected with the NCO module 123, the output end is connected with the data processing unit 140, and the amplitude adjustment module 124 is used for adjusting waveform amplitude of the IQ quadrature signal and outputting the IQ quadrature signal to the data processing unit 140.
The waveform generation unit 120 further includes: the FIFO control module is connected with the external waveform receiving and storing unit 130, and the waveform generating unit 120 reads specified external waveform data from the external waveform receiving and storing unit 130 according to the read-write control time sequence requirement of the FIFO control module; and the interpolation module is connected with the FIFO control module and the NCO module 123, and is used for carrying out interpolation processing on the external waveform data and outputting the external waveform data to the NCO module 123. The waveform generation unit 120 further includes: the sub-control word analysis module is connected with the control word analysis unit 110, the waveform code generation module 121, the interpolation module, the NCO module 123, the amplitude adjustment module 124 and the FIFO control module, and is used for further analyzing the control word information analyzed by the control word analysis unit 110 to obtain all configuration information required by final waveform generation.
It is understood that the waveform generation unit 120 includes: the system comprises a sub control word analysis module, a FIFO control module, a plurality of waveform code generation modules 121, an interpolation module, a Cordic waveform generation module 122, an NCO module 123 and an amplitude adjustment module 124. The sub-control word parsing module further parses the control word information transmitted from the control word parsing unit 110 to obtain all configuration information required for generating the final waveform, where the waveform generating modes are two main types, the first type is that the waveform code generating module 121 generates the waveform code, and the second type is that the waveform code is directly written into the internal FIFO control module from the outside through the high-speed interface and then is transmitted. When the waveform generation mode is the first type, one or more of the linear frequency modulation, the phase coding, the FSK, the single carrier frequency and the nonlinear frequency modulation module start to work according to the control word information, and angle signals with certain length and quantity are generated according to the designated waveform type and requirement. The Cordic waveform generation module 122 converts the angle signals into IQ quadrature signals with corresponding frequency phases, and then performs multiplication and addition operation through the NCO module 123 to realize the frequency phase adjustment of the waveform, and in order to avoid overflow, the amplitude of the waveform is adjusted through the amplitude adjustment module 124 and then output to the data processing unit 140. When the waveform generation mode is the second type, the waveform generation unit 120 directly reads the specified external waveform data from the external waveform storage unit according to the read-write control timing requirement of the FIFO control module, and because the storage space is limited, the external waveform data rate is often low, and in order to recover the low data rate to obtain the waveform with high data rate, an interpolation module is connected to interpolate the original waveform data, and then the interpolated waveform data is sent to the NCO module 123 for processing. The waveform generation unit 120 may sequentially generate a front shield waveform, a rear shield waveform, an intra-pulse shield waveform, and a working waveform in a time-sharing manner, or may superimpose these waveforms to realize digital multi-beam transmission.
In one embodiment, an up-conversion link system suitable for a wideband digital TR chip includes: a control word parsing unit 110, configured to perform data parsing on control word information received from an external system, so as to obtain waveform type and operation mode information required for the operation of the up-conversion link; a waveform generation unit 120 connected to the control word analysis unit 110, the waveform generation unit 120 generating a waveform signal according to the waveform type; an external waveform receiving and storing unit 130 connected to the control word analyzing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analysis unit 110 and the waveform generation unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; the DAC IP core unit 150 is connected to the data processing unit 140, and the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generation unit 120 includes: a plurality of waveform code generating modules 121 connected to the control word analyzing unit 110, the waveform code generating modules 121 being configured to generate corresponding waveform signals according to the control word information analyzed by the control word analyzing unit 110; the Cordic waveform generation module 122 is connected with the waveform code generation module 121, and the Cordic waveform generation module 122 is used for converting the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generation module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signals to realize the frequency phase adjustment of the waveform; the input end of the amplitude adjustment module 124 is connected with the NCO module 123, the output end is connected with the data processing unit 140, and the amplitude adjustment module 124 is used for adjusting waveform amplitude of the IQ quadrature signal and outputting the IQ quadrature signal to the data processing unit 140. The waveform code generation module 121 includes at least any two of the following: the device comprises a linear frequency modulation module, a phase encoding module, an FSK module, a single carrier frequency module and a nonlinear frequency modulation module.
Referring to fig. 3 and fig. 4, fig. 3 is a schematic diagram of an interpolation module of an up-conversion link system applicable to a wideband digital TR chip according to another embodiment of the present invention; fig. 4 is a diagram showing an NCO module 123 of an up-conversion link system applicable to a broadband digital TR chip according to another embodiment of the present invention.
In one embodiment, an up-conversion link system suitable for a wideband digital TR chip includes: a control word parsing unit 110, configured to perform data parsing on control word information received from an external system, so as to obtain waveform type and operation mode information required for the operation of the up-conversion link; a waveform generation unit 120 connected to the control word analysis unit 110, the waveform generation unit 120 generating a waveform signal according to the waveform type; an external waveform receiving and storing unit 130 connected to the control word analyzing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analysis unit 110 and the waveform generation unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; the DAC IP core unit 150 is connected to the data processing unit 140, and the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generation unit 120 includes: a plurality of waveform code generating modules 121 connected to the control word analyzing unit 110, the waveform code generating modules 121 being configured to generate corresponding waveform signals according to the control word information analyzed by the control word analyzing unit 110; the Cordic waveform generation module 122 is connected with the waveform code generation module 121, and the Cordic waveform generation module 122 is used for converting the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generation module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signals to realize the frequency phase adjustment of the waveform; the input end of the amplitude adjustment module 124 is connected with the NCO module 123, the output end is connected with the data processing unit 140, and the amplitude adjustment module 124 is used for adjusting waveform amplitude of the IQ quadrature signal and outputting the IQ quadrature signal to the data processing unit 140.
The waveform generation unit 120 further includes: the FIFO control module is connected with the external waveform receiving and storing unit 130, and the waveform generating unit 120 reads specified external waveform data from the external waveform receiving and storing unit 130 according to the read-write control time sequence requirement of the FIFO control module; and the interpolation module is connected with the FIFO control module and the NCO module 123, and is used for carrying out interpolation processing on the external waveform data and outputting the external waveform data to the NCO module 123. The interpolation module comprises: a configuration register for setting interpolation multiples of external waveform data; and the FIR filter is connected with the configuration register and is used for carrying out filtering processing on the external waveform data after interpolation so as to eliminate high-frequency noise generated by the interpolation.
The interpolation module supports 1/2/4/8/16 times of adjustable up-conversion interpolation, and the interpolation multiple is set by a configuration register. To eliminate the high frequency noise that occurs during interpolation, there is an FIR filter to filter the data after each x2 interpolation. Wherein, a 59-order fixed coefficient FIR filter is arranged after 1-2 interpolation, the FIR filter after 2-4 interpolation is 23-order, and the filters behind the 4-8/8-16 interpolators are 11-order. The filter with fixed coefficients is a plurality of Wallace trees, and the final result is generated after a plurality of times of merging. The delay and the area occupation of the filter with fixed coefficients are less, and the delay of each FIR filter is 2-3 clock cycles.
The NCO module 123 adopts a pipeline structure, and performs accumulation iteration on the phase under the initial phase control word and the frequency control word, and after quadrant judgment is required to be performed on the input angle value before calculation, the input angle value is converted into a range of 0-90 ° for calculation, and finally, the input angle value is inversely converted into the original quadrant to obtain a final result. The state register controls the object limit conversion module by judging the highest 2 bits of the input angle, and the frequency control word and the initial phase control word are 32 bits.
The external waveform receiving and storing unit 130 stores waveform data transmitted from the optical fiber into three FIFOs with the size of 4K according to the waveform data receiving protocol requirement of table 1, and the data receiving rate is 10Gbps. When the waveform generation unit 120 needs to read waveform data, the FIFO control module performs read-write operation on the three FIFOs according to the timing required by waveform generation.
TABLE 1
Referring to fig. 5, fig. 5 is a block diagram of a data processing unit 140 of an up-conversion link system suitable for a broadband digital TR chip according to another embodiment of the present invention.
In one embodiment, an up-conversion link system suitable for a wideband digital TR chip includes: a control word parsing unit 110, configured to perform data parsing on control word information received from an external system, so as to obtain waveform type and operation mode information required for the operation of the up-conversion link; a waveform generation unit 120 connected to the control word analysis unit 110, the waveform generation unit 120 generating a waveform signal according to the waveform type; an external waveform receiving and storing unit 130 connected to the control word analyzing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analysis unit 110 and the waveform generation unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; the DAC IP core unit 150 is connected to the data processing unit 140, and the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generation unit 120 includes: a plurality of waveform code generating modules 121 connected to the control word analyzing unit 110, the waveform code generating modules 121 being configured to generate corresponding waveform signals according to the control word information analyzed by the control word analyzing unit 110; the Cordic waveform generation module 122 is connected with the waveform code generation module 121, and the Cordic waveform generation module 122 is used for converting the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generation module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signals to realize the frequency phase adjustment of the waveform; the input end of the amplitude adjustment module 124 is connected with the NCO module 123, the output end is connected with the data processing unit 140, and the amplitude adjustment module 124 is used for adjusting waveform amplitude of the IQ quadrature signal and outputting the IQ quadrature signal to the data processing unit 140.
The data processing unit 140 includes: the equalization filtering module is connected with the waveform generation unit 120 and is used for performing equalization filtering processing on the IQ orthogonal signals output by the waveform generation unit 120 so as to finish phase amplitude consistency compensation of the IQ orthogonal signals in a large bandwidth; the anti-Sinc module is connected with the equalization filtering module and is used for carrying out anti-Sinc function processing on the IQ orthogonal signals so as to eliminate the amplitude inconsistency of the broadband during frequency conversion; the decimal delay module is connected with the inverted Sinc module and is used for adjusting the clock period of the waveform group delay; the IQ orthogonal correction and direct current offset module is connected with the decimal delay module and is used for carrying out orthogonal correction and direct current offset compensation on the IQ signals; and the dither module is connected with the IQ orthogonal correction and direct current bias module and is used for reducing output spurious of the DAC due to quantization errors.
The data processing unit 140 includes: the system comprises an equalization filtering module, an anti-Sinc module, a decimal delay module, an IQ orthogonal correction and direct current bias module and a dither module. After the waveform data output by the waveform generation unit 120 enter the data processing unit 140, phase amplitude consistency compensation of the waveform data in a large bandwidth is finished through a complex equalization filter module of an FIR (finite impulse response) with a configurable 63-order coefficient, then amplitude inconsistency of a broadband of a subsequent DAC (digital-to-analog converter) in frequency conversion is eliminated through an inverse sine function, and the inverse sine function is a 9-order fixed coefficient FIR. The decimal delay module adjusts the clock period of the waveform group delay, and the IQ correction module realizes quadrature correction and direct current bias compensation on the IQ signal. The dither module may reduce output spurs of the DAC due to quantization errors. The modules are bypass-able, and each adjustment parameter is configurable to meet the requirements of different application contexts.
Referring to fig. 6 and 7, fig. 6 is a diagram showing a fractional delay module of an up-conversion link system applicable to a broadband digital TR chip according to another embodiment of the present invention; fig. 7 is a schematic diagram of a dither module of an up-conversion link system suitable for a wideband digital TR chip according to another embodiment of the present invention.
In one embodiment, an up-conversion link system suitable for a wideband digital TR chip includes: a control word parsing unit 110, configured to perform data parsing on control word information received from an external system, so as to obtain waveform type and operation mode information required for the operation of the up-conversion link; a waveform generation unit 120 connected to the control word analysis unit 110, the waveform generation unit 120 generating a waveform signal according to the waveform type; an external waveform receiving and storing unit 130 connected to the control word analyzing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analysis unit 110 and the waveform generation unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; the DAC IP core unit 150 is connected to the data processing unit 140, and the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generation unit 120 includes: a plurality of waveform code generating modules 121 connected to the control word analyzing unit 110, the waveform code generating modules 121 being configured to generate corresponding waveform signals according to the control word information analyzed by the control word analyzing unit 110; the Cordic waveform generation module 122 is connected with the waveform code generation module 121, and the Cordic waveform generation module 122 is used for converting the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generation module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signals to realize the frequency phase adjustment of the waveform; the input end of the amplitude adjustment module 124 is connected with the NCO module 123, the output end is connected with the data processing unit 140, and the amplitude adjustment module 124 is used for adjusting waveform amplitude of the IQ quadrature signal and outputting the IQ quadrature signal to the data processing unit 140.
The data processing unit 140 includes: the equalization filtering module is connected with the waveform generation unit 120 and is used for performing equalization filtering processing on the IQ orthogonal signals output by the waveform generation unit 120 so as to finish phase amplitude consistency compensation of the IQ orthogonal signals in a large bandwidth; the anti-Sinc module is connected with the equalization filtering module and is used for carrying out anti-Sinc function processing on the IQ orthogonal signals so as to eliminate the amplitude inconsistency of the broadband during frequency conversion; the decimal delay module is connected with the inverted Sinc module and is used for adjusting the clock period of the waveform group delay; the IQ orthogonal correction and direct current offset module is connected with the decimal delay module and is used for carrying out orthogonal correction and direct current offset compensation on the IQ signals; and the dither module is connected with the IQ orthogonal correction and direct current bias module and is used for reducing output spurious of the DAC due to quantization errors.
The decimal delay module comprises: a coefficient storage ROM storing a normalized coefficient; fine-tuning the fractional delay, connecting with the coefficient storage ROM; the coarse decimal delay is connected with the coefficient storage ROM and the fine decimal delay; the integer delay is connected with the coefficient storage ROM and the coarse decimal delay; and the normalization multiplier is connected with the coefficient storage ROM and the integer delay.
It is understood that the delay module includes five parts including a coefficient memory ROM, a fine fraction delay, a coarse fraction delay, an integer delay and a normalized multiplier. Wherein the fine fraction delay is implemented using a 9-order FIR filter. The delay time is 0-0.200 period, the adjustment interval is 0.002 period, and the delay time is controlled by 7 bit coefficients. The coarse fractional delay is implemented using a 7-order FIR filter. The delay time is 0-0.875 period, the adjustment interval is 0.125 period, and the delay time is controlled by the 3-bit coefficient. The integer delay is 0-3 beats, controlled by a 2-bit control code. The normalization multiplier is a 16x16 multiplier, and the 16-bit normalization coefficient is provided by the coefficient memory ROM. By modifying the weighting coefficients of the filters, the phase of the data can be adjusted, thereby changing the delay time of the data. The weighting coefficient corresponding to each delay is set, the delay time is selected by an external control code, and the input and output of the decimal delay are 16 bits.
The dither module adopts an M sequence structure, generates a pseudo-random sequence by carrying out linear feedback through N registers, has periodicity, the coefficient of each register is determined by an intrinsic polynomial corresponding to an order N, N and the intrinsic polynomial can be set through a control word, N in a default initialization state is 8, and the intrinsic polynomial is 1+X 2 +X 3 +X 4 +X 8 。
Referring to fig. 8, fig. 8 is a block diagram of an analog DAC IP core of an up-conversion link system applicable to a broadband digital TR chip according to another embodiment of the present invention.
In one embodiment, an up-conversion link system suitable for a wideband digital TR chip includes: a control word parsing unit 110, configured to perform data parsing on control word information received from an external system, so as to obtain waveform type and operation mode information required for the operation of the up-conversion link; a waveform generation unit 120 connected to the control word analysis unit 110, the waveform generation unit 120 generating a waveform signal according to the waveform type; an external waveform receiving and storing unit 130 connected to the control word analyzing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analysis unit 110 and the waveform generation unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; the DAC IP core unit 150 is connected to the data processing unit 140, and the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The DAC IP core can adopt 28nm technology, is four-channel 12bit, has the highest sampling rate of 640Msps, can provide differential current output, and supports single-ended or differential configuration. The supply voltages were 0.9V and 1.8V. The internal part of the device mainly comprises 2 paths of input latches, 2 paths of DAC conversion circuits, a time sequence generation circuit and a bias generation circuit. The output current can be used for directly driving two external resistive loads to obtain two complementary single-ended output voltages, and can also be used for driving an external transformer or an amplifier to obtain the single-ended output voltages. The DAC adopts a current rudder type structure decoded by the segmented thermometer, and controls the output of current generated by different bit weight current sources by inputting a digital signal sequence, so that digital signals are converted into analog signals, and the DAC can realize very high data update rate, 12-bit inherent static precision and very good dynamic characteristics. The internal bandgap voltage reference and external resistor are used to set the full scale current of the DAC. The DAC is integrated in the digital TR chip in an IP mode, and registers such as working mode, full scale, starting time and the like are directly configured by the control word.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
While the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the above embodiment, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present invention, and these equivalent modifications and substitutions are intended to be included in the scope of the present invention as defined in the appended claims.
The above-described embodiments of the present invention do not limit the scope of the present invention. Any other corresponding changes and modifications made in accordance with the technical idea of the present invention shall be included in the scope of the claims of the present invention.
Claims (9)
1. An up-conversion link system for a broadband digital TR chip, comprising:
the control word analysis unit is used for carrying out data analysis on the control word information received from the external system to obtain the waveform type and the working mode information required by the up-conversion link operation;
the waveform generation unit is connected with the control word analysis unit and generates a waveform signal according to the waveform type;
the external waveform receiving and storing unit is connected with the control word analyzing unit and the waveform generating unit and is used for receiving and storing external waveform data;
The data processing unit is connected with the control word analysis unit and the waveform generation unit and is used for carrying out amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signals;
the DAC IP core unit is connected with the data processing unit and is used for carrying out digital-to-analog conversion on the waveform signals;
the waveform generation unit includes:
the waveform code generation module is connected with the control word analysis unit and is used for generating the corresponding waveform signals according to the control word information analyzed by the control word analysis unit;
the Cordic waveform generation module is connected with the waveform code generation module and is used for converting the waveform signal into an IQ orthogonal signal with a corresponding frequency phase;
the NCO module is connected with the Cordic waveform generation module and is used for carrying out multiplication and addition operation on the IQ orthogonal signals to realize the frequency phase adjustment of waveforms;
and the amplitude adjusting module is used for adjusting the waveform amplitude of the IQ orthogonal signal and outputting the IQ orthogonal signal to the data processing unit.
2. The up-conversion link system adapted for a broadband digital TR chip according to claim 1, wherein said waveform generation unit further comprises:
the FIFO control module is connected with the external waveform receiving and storing unit, and the waveform generating unit reads specified external waveform data from the external waveform receiving and storing unit according to the read-write control time sequence requirement of the FIFO control module;
the interpolation module is connected with the FIFO control module and the NCO module, and is used for carrying out interpolation processing on the external waveform data and outputting the external waveform data to the NCO module.
3. The up-conversion link system adapted for a broadband digital TR chip according to claim 2, wherein said waveform generation unit further comprises:
the sub-control word analysis module is connected with the control word analysis unit, the waveform code generation module, the interpolation module, the NCO module, the amplitude adjustment module and the FIFO control module, and is used for further analyzing the control word information analyzed by the control word analysis unit to obtain all configuration information required by final waveform generation.
4. The up-conversion link system for wideband digital TR chip as set forth in claim 1, wherein said waveform code generation module includes at least any two of:
the device comprises a linear frequency modulation module, a phase encoding module, an FSK module, a single carrier frequency module and a nonlinear frequency modulation module.
5. The up-conversion link system adapted for use with a wideband digital TR chip of claim 2, wherein said interpolation module comprises:
a configuration register for setting interpolation multiples of the external waveform data;
and the FIR filter is connected with the configuration register and is used for carrying out filtering processing on the interpolated external waveform data so as to eliminate high-frequency noise generated by interpolation.
6. The up-conversion link system adapted for use with a broadband digital TR chip according to claim 1, wherein said data processing unit comprises:
the equalization filtering module is connected with the waveform generation unit and is used for performing equalization filtering processing on the IQ orthogonal signals output by the waveform generation unit so as to finish phase amplitude consistency compensation of the IQ orthogonal signals in a large bandwidth;
The anti-Sinc module is connected with the equalization filtering module and is used for carrying out anti-Sinc function processing on the IQ orthogonal signals so as to eliminate the amplitude inconsistency of a broadband during frequency conversion;
the decimal delay module is connected with the inverted Sinc module and is used for adjusting the clock period of the waveform group delay;
the IQ orthogonal correction and direct current offset module is connected with the decimal delay module and is used for carrying out orthogonal correction and direct current offset compensation on IQ signals;
and the dither module is connected with the IQ orthogonal correction and direct current bias module and is used for reducing output spurious of the DAC due to quantization errors.
7. The up-conversion link system for a wideband digital TR chip of claim 6, wherein said fractional delay module comprises:
a coefficient storage ROM storing a normalized coefficient;
fine-tuning the fractional delay, connecting with the coefficient storage ROM;
a coarse fraction delay coupled to the coefficient store ROM and the fine fraction delay;
integer delay, connect with said coefficient memory ROM and said coarse adjustment decimal delay;
and the normalization multiplier is connected with the coefficient storage ROM and the integer delay.
8. The up-conversion link system adapted for use with a wideband digital TR chip of claim 1, wherein said DAC IP core unit comprises:
the device comprises two paths of input latches, a time sequence generating circuit, a bias generating circuit and two paths of DAC cores, wherein the input latches are connected with the DAC cores, the time sequence generating circuit is arranged between the two paths of input latches, and the time sequence generating circuit and the bias generating circuit are connected between the two paths of DAC cores.
9. An up-conversion link device suitable for a broadband digital TR chip, comprising: eight identical up-conversion channels provided with an up-conversion link system according to any of claims 1 to 8, suitable for a broadband digital TR chip.
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