CN115276704A - Up-conversion link system and device suitable for broadband digital TR chip - Google Patents

Up-conversion link system and device suitable for broadband digital TR chip Download PDF

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Publication number
CN115276704A
CN115276704A CN202210795541.2A CN202210795541A CN115276704A CN 115276704 A CN115276704 A CN 115276704A CN 202210795541 A CN202210795541 A CN 202210795541A CN 115276704 A CN115276704 A CN 115276704A
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waveform
module
unit
control word
external
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CN115276704B (en
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李刚伟
杨洋
王嘉祥
李直
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Aerospace Nanhu Electronic Information Technology Co ltd
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Aerospace Nanhu Electronic Information Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/005—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges
    • H04B1/0096—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission adapting radio receivers, transmitters andtransceivers for operation on two or more bands, i.e. frequency ranges where a full band is frequency converted into another full band
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The application provides an up-conversion link system and device suitable for broadband digital TR chip, and the system includes: the control word analysis unit is used for carrying out data analysis on the control word information received from an external system; a waveform generating unit generating a waveform signal according to a waveform type; the external waveform receiving and storing unit is used for receiving and storing external waveform data; the data processing unit is connected with the control word analysis unit and the waveform generation unit and is used for carrying out amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; and the DAC IP core unit is connected with the data processing unit and is used for carrying out digital-to-analog conversion on the waveform signal. The invention solves the problem that the existing digital TR chip can not meet the requirement of broadband waveform data generation, and overcomes the defects of high cost and large area brought by the FPGA chip under the condition of large-scale use.

Description

Up-conversion link system and device suitable for broadband digital TR chip
Technical Field
The invention relates to the technical field of digital-analog hybrid chip design, in particular to an up-conversion link system and device suitable for a broadband digital TR chip.
Background
With the development of digital technology, digital TR (Transmitter and Receiver) components are increasingly used in radar, satellite communication and other systems, and play an important role. With the continuous improvement of radar bandwidth and the development of high-speed signal processing technology, a radar system has higher requirements on the speed and efficiency of mass data transmission, and due to the fact that the number of array units is large, the problems of high cost and large size are caused when a traditional digital assembly based on an FPGA is adopted to complete digital array receiving and sending.
Disclosure of Invention
The invention aims to overcome the technical defects, provides an up-conversion link system and a device suitable for a broadband digital TR chip, and solves the technical problems of high cost and large volume caused by the fact that a traditional digital component based on an FPGA completes digital array receiving and sending in the prior art.
To achieve the above technical object, in a first aspect, a technical solution of the present invention provides an up-conversion link system suitable for a wideband digital TR chip, including:
the control word analysis unit is used for carrying out data analysis on control word information received from an external system to obtain the waveform type and the working mode information required by the work of the up-conversion link;
the waveform generating unit is connected with the control word analyzing unit and generates a waveform signal according to the waveform type;
the external waveform receiving and storing unit is connected with the control word analyzing unit and the waveform generating unit and is used for receiving and storing external waveform data;
the data processing unit is connected with the control word analysis unit and the waveform generation unit and is used for carrying out amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal;
and a DAC IP core unit (Digital to analog converter) connected to the data processing unit, the DAC IP core unit being configured to perform Digital to analog conversion on the waveform signal.
Compared with the prior art, the invention has the beneficial effects that:
according to the up-conversion link system suitable for the broadband digital TR chip, provided by the technical scheme of the invention, by carrying out chip design on waveform generation and up-conversion and carrying out digital-analog hybrid integration on an analog DAC IP core, the system cost can be effectively reduced and the chip area can be reduced under the condition of realizing a 640Msps sampling rate, and meanwhile, the up-conversion link system has the advantages of low power consumption and high integration degree. The invention solves the problem that the existing digital TR chip can not meet the requirement of broadband waveform data generation, and overcomes the defects of high cost and large area brought by the FPGA chip under the condition of large-scale use.
According to some embodiments of the invention, the waveform generation unit comprises:
the multi-waveform code generating module is connected with the control word analyzing unit and is used for generating corresponding waveform signals according to the control word information analyzed by the control word analyzing unit;
a Cordic (Coordinate Rotation Digital Computer) waveform generating module connected to the waveform code generating module, the Cordic waveform generating module being configured to convert the waveform signal into an IQ quadrature signal (modulation signal orthogonal to phase) of a corresponding frequency phase;
an NCO (numerically controlled oscillator) module connected to the Cordic waveform generating module, wherein the NCO module is configured to perform a multiply-add operation on the IQ quadrature signal to adjust a frequency phase of a waveform;
and the input end of the amplitude adjustment module is connected with the NCO module, the output end of the amplitude adjustment module is connected with the data processing unit, and the amplitude adjustment module is used for carrying out waveform amplitude adjustment on the IQ orthogonal signal and outputting the IQ orthogonal signal to the data processing unit.
According to some embodiments of the invention, the waveform generation unit further comprises:
a First Input First Output (FIFO) control module connected to the external waveform receiving and storing unit, the waveform generating unit reading specified external waveform data from the external waveform receiving and storing unit according to the read-write control timing requirement of the FIFO control module;
and the interpolation module is connected with the FIFO control module and the NCO module and is used for carrying out interpolation processing on the external waveform data and outputting the external waveform data to the NCO module.
According to some embodiments of the invention, the waveform generation unit further comprises:
and the sub control word analysis module is connected with the control word analysis unit, the waveform code generation module, the interpolation module, the NCO module, the amplitude adjustment module and the FIFO control module, and is used for further analyzing the control word information analyzed by the control word analysis unit to obtain all configuration information required by final waveform generation.
According to some embodiments of the invention, the waveform code generation module comprises at least any two of:
a chirp module, a phase encoding module, an FSK module (Frequency-shift keying), a single carrier Frequency module, and a non-chirp module.
According to some embodiments of the invention, the interpolation module comprises:
a configuration register for setting an interpolation multiple for the external waveform data;
and the FIR filter (Finite Impulse Response filter) is connected with the configuration register and is used for filtering the external waveform data after interpolation so as to eliminate high-frequency noise generated by interpolation.
According to some embodiments of the invention, the data processing unit comprises:
the balanced filtering module is connected with the waveform generating unit and is used for carrying out balanced filtering processing on the IQ orthogonal signal output by the waveform generating unit so as to finish phase amplitude consistency compensation of the IQ orthogonal signal in a large bandwidth;
the inverse Sinc module is connected with the equalizing filter module and is used for performing inverse Sinc function processing on the IQ orthogonal signal so as to eliminate amplitude inconsistency of a wide frequency band during frequency conversion;
the decimal time delay module is connected with the reverse Sinc module and used for adjusting the clock period of the waveform group delay;
the IQ orthogonal correction and direct current bias module is connected with the decimal delay module and is used for carrying out orthogonal correction and direct current bias compensation on IQ signals;
and the diter (jitter) module is connected with the IQ quadrature correction and direct current offset module and is used for reducing output stray of the DAC caused by quantization error.
According to some embodiments of the invention, the fractional delay module comprises:
a coefficient storage ROM for storing a normalization coefficient;
a fine fractional delay coupled to the coefficient storage ROM;
a coarse fractional delay coupled to the coefficient storage ROM and the fine fractional delay;
the integer time delay is connected with the coefficient storage ROM and the coarse adjustment decimal time delay;
and the normalization multiplier is connected with the coefficient storage ROM and the integer time delay.
According to some embodiments of the invention, the DAC IP core unit comprises:
the device comprises two paths of input latches, a time sequence generating circuit, a bias generating circuit and two paths of DAC cores, wherein the input latches are connected with the DAC cores, the time sequence generating circuit is arranged between the two paths of input latches, and the time sequence generating circuit and the bias generating circuit are connected between the two paths of DAC cores.
In a second aspect, an embodiment of the present invention provides an up-conversion link device suitable for a wideband digital TR chip, including: eight identical up-conversion channels provided with an up-conversion link system adapted for a wideband digital TR chip as described in any of the first aspects.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which the abstract is to be fully consistent with one of the figures of the specification:
fig. 1 is a schematic diagram of an up-conversion link system suitable for a wideband digital TR chip according to an embodiment of the present invention;
fig. 2 is a block diagram of a waveform generating unit of an up-conversion link system suitable for a wideband digital TR chip according to another embodiment of the present invention;
fig. 3 is a schematic diagram of an interpolation module of an up-conversion link system suitable for a wideband digital TR chip according to another embodiment of the present invention;
fig. 4 is a diagram of an NCO module of an up-conversion link system suitable for a wideband digital TR chip according to another embodiment of the present invention;
fig. 5 is a block diagram of a data processing unit of an up-conversion link system suitable for a wideband digital TR chip according to another embodiment of the present invention;
fig. 6 is a diagram of a fractional delay module of an upconverter link system suitable for a wideband digital TR chip according to another embodiment of the present invention;
fig. 7 is a diagram of a diter module structure of an up-conversion link system suitable for a wideband digital TR chip according to another embodiment of the present invention;
fig. 8 is a block diagram of an analog DAC IP core of an upconversion link system suitable for a wideband digital TR chip according to another embodiment of the present invention.
Description of reference numerals: the device comprises a control word analysis unit 110, a waveform generation unit 120, an external waveform receiving and storing unit 130, a data processing unit 140, a DAC IP core unit 150, a waveform code generation module 121, a Cordic waveform generation module 122, an NCO module 123 and an amplitude adjustment module 124.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It should be noted that although functional block divisions are provided in the system drawings and logical orders are shown in the flowcharts, in some cases, the steps shown and described may be performed in different orders than the block divisions in the systems or in the flowcharts. The terms first, second and the like in the description and in the claims, as well as in the drawings described above, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
The invention provides an up-conversion link system suitable for a broadband digital TR chip, which can effectively reduce the system cost and the chip area under the condition of realizing the sampling rate of 640Msps by carrying out chip design on waveform generation and up-conversion and carrying out digital-analog hybrid integration on an analog DAC IP core, and has the advantages of low power consumption and high integration level. The invention solves the problem that the existing digital TR chip can not meet the requirement of broadband waveform data generation, and overcomes the defects of high cost and large area brought by the FPGA chip under the condition of large-scale use.
The embodiments of the present invention will be further explained with reference to the drawings.
Referring to fig. 1, fig. 1 is a schematic diagram of an up-conversion link system suitable for a wideband digital TR chip according to an embodiment of the present invention.
In one embodiment, an upconversion link system suitable for use with a wideband digital TR chip includes: a control word analyzing unit 110, configured to perform data analysis on control word information received from an external system to obtain a waveform type and working mode information required by an up-conversion link; a waveform generating unit 120 connected to the control word parsing unit 110, the waveform generating unit 120 generating a waveform signal according to the type of the waveform; an external waveform receiving and storing unit 130 connected to the control word parsing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analyzing unit 110 and the waveform generating unit 120, and the data processing unit 140 is configured to perform amplitude phase compensation, intra-channel orthogonality correction, and inter-channel consistency compensation on the waveform signal; and a DAC IP core unit 150 connected to the data processing unit 140, where the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
It can be understood that, after the chip is powered on, the chip first sends control word information to the up-conversion link system through the high-speed interface, and after receiving the control word, the control word analyzing unit 110 analyzes address data of the control word to obtain configuration parameters for the up-conversion link system, and outputs the configuration parameters to each unit to complete initialization configuration.
When the synchronous pulse signal arrives, the up-conversion link system starts to enter a working state, corresponding working waveforms are generated by the waveform unit according to a preset working mode or waveform data are directly written into the external waveform receiving and storing unit 130 by the external high-speed interface, the waveform data are processed and then output to the DAC IP core, the data are converted from digital to analog signals after passing through the DAC IP core, and finally the data are output to the next stage of the component.
The control word parsing unit 110 identifies the received high-speed data stream information, searches and aligns the synchronization header according to a specific digital protocol, then begins to parse the packet header, and parses and stores the subsequent data streams into a register one by one according to addresses to output the data streams to other units.
Referring to fig. 2, fig. 2 is a block diagram of a waveform generating unit 120 of an up-conversion link system suitable for a wideband digital TR chip according to another embodiment of the present invention.
In one embodiment, an upconversion link system suitable for use with a wideband digital TR chip includes: a control word analyzing unit 110, configured to perform data analysis on control word information received from an external system to obtain a waveform type and working mode information required by an up-conversion link; a waveform generating unit 120 connected to the control word parsing unit 110, the waveform generating unit 120 generating a waveform signal according to the type of the waveform; an external waveform receiving and storing unit 130, connected to the control word parsing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analyzing unit 110 and the waveform generating unit 120, and the data processing unit 140 is configured to perform amplitude phase compensation, intra-channel orthogonality correction, and inter-channel consistency compensation on the waveform signal; and a DAC IP core unit 150 connected to the data processing unit 140, where the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generating unit 120 includes: a plurality of waveform code generating modules 121 connected to the control word parsing unit 110, the waveform code generating modules 121 being configured to generate corresponding waveform signals according to the control word information parsed by the control word parsing unit 110; a Cordic waveform generating module 122 connected to the waveform code generating module 121, wherein the Cordic waveform generating module 122 is configured to convert the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generating module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signal to realize frequency phase adjustment on the waveform; and an input end of the amplitude adjusting module 124 is connected with the NCO module 123, an output end of the amplitude adjusting module 124 is connected with the data processing unit 140, and the amplitude adjusting module 124 is configured to perform waveform amplitude adjustment on the IQ quadrature signal and output the IQ quadrature signal to the data processing unit 140.
In one embodiment, an upconversion link system suitable for use with a wideband digital TR chip includes: a control word analyzing unit 110, configured to perform data analysis on control word information received from an external system to obtain a waveform type and working mode information required by an up-conversion link; a waveform generating unit 120 connected to the control word parsing unit 110, the waveform generating unit 120 generating a waveform signal according to the type of the waveform; an external waveform receiving and storing unit 130, connected to the control word parsing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analyzing unit 110 and the waveform generating unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; and a DAC IP core unit 150 connected to the data processing unit 140, where the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generating unit 120 includes: the various waveform code generating module 121 is connected to the control word parsing unit 110, and the waveform code generating module 121 is configured to generate a corresponding waveform signal according to the control word information parsed by the control word parsing unit 110; a Cordic waveform generating module 122 connected to the waveform code generating module 121, wherein the Cordic waveform generating module 122 is configured to convert the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generating module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signal to realize frequency phase adjustment on the waveform; and an input end of the amplitude adjusting module 124 is connected with the NCO module 123, an output end of the amplitude adjusting module 124 is connected with the data processing unit 140, and the amplitude adjusting module 124 is configured to perform waveform amplitude adjustment on the IQ quadrature signal and output the IQ quadrature signal to the data processing unit 140.
The waveform generating unit 120 further includes: a FIFO control module connected to the external waveform receiving and storing unit 130, the waveform generating unit 120 reading the designated external waveform data from the external waveform receiving and storing unit 130 according to the read-write control timing requirement of the FIFO control module; and the interpolation module is connected with the FIFO control module and the NCO module 123 and is used for carrying out interpolation processing on the external waveform data and outputting the external waveform data to the NCO module 123.
In one embodiment, an up-conversion link system for a wideband digital TR chip includes: a control word analyzing unit 110, configured to perform data analysis on control word information received from an external system to obtain a waveform type and working mode information required by an up-conversion link; a waveform generating unit 120 connected to the control word parsing unit 110, the waveform generating unit 120 generating a waveform signal according to the type of the waveform; an external waveform receiving and storing unit 130 connected to the control word parsing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analyzing unit 110 and the waveform generating unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; and a DAC IP core unit 150 connected to the data processing unit 140, where the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generating unit 120 includes: the various waveform code generating module 121 is connected to the control word parsing unit 110, and the waveform code generating module 121 is configured to generate a corresponding waveform signal according to the control word information parsed by the control word parsing unit 110; a Cordic waveform generating module 122 connected to the waveform code generating module 121, wherein the Cordic waveform generating module 122 is configured to convert the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generating module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signal to realize frequency phase adjustment on the waveform; and an input end of the amplitude adjusting module 124 is connected with the NCO module 123, an output end of the amplitude adjusting module 124 is connected with the data processing unit 140, and the amplitude adjusting module 124 is configured to perform waveform amplitude adjustment on the IQ quadrature signal and output the IQ quadrature signal to the data processing unit 140.
The waveform generating unit 120 further includes: a FIFO control module connected to the external waveform receiving and storing unit 130, the waveform generating unit 120 reading the designated external waveform data from the external waveform receiving and storing unit 130 according to the read-write control timing requirement of the FIFO control module; and the interpolation module is connected with the FIFO control module and the NCO module 123 and is used for carrying out interpolation processing on the external waveform data and outputting the external waveform data to the NCO module 123. The waveform generating unit 120 further includes: and the sub control word analysis module is connected with the control word analysis unit 110, the waveform code generation module 121, the interpolation module, the NCO module 123, the amplitude adjustment module 124 and the FIFO control module, and is used for further analyzing the control word information analyzed by the control word analysis unit 110 to obtain all configuration information required by the final waveform generation.
It is understood that the waveform generating unit 120 includes: the device comprises a sub control word analysis module, an FIFO control module, a multi-waveform code generation module 121, an interpolation module, a Cordic waveform generation module 122, an NCO module 123 and an amplitude adjustment module 124. The sub control word analysis module further analyzes the control word information transmitted from the control word analysis unit 110 to obtain all configuration information required by the final waveform generation, and the waveform generation mode has two major types, the first type is generated by the waveform code generation module 121 in the module, and the second type is directly transmitted after being written into the internal FIFO control module through the high-speed interface from the outside. When the waveform generation mode is the first type, one or more of a linear frequency modulation module, a phase coding module, an FSK module, a single carrier frequency module and a non-linear frequency modulation module start to work according to the control word information, and angle signals with certain length and quantity are generated according to the specified waveform type and requirements. The Cordic waveform generation module 122 converts these angle signals into IQ quadrature signals of corresponding frequency phases, and then performs multiply-add operation by the NCO module 123 to adjust the frequency phases of the waveforms, and in order to avoid overflow, the amplitude adjustment module 124 adjusts the amplitude of the waveforms and outputs the adjusted waveform amplitudes to the data processing unit 140. When the waveform generation mode is the second type, the waveform generation unit 120 directly reads the designated external waveform data from the external waveform storage unit according to the read-write control timing requirement of the FIFO control module, and since the storage space is limited, the external waveform data rate is often low, in order to recover the low data rate to obtain a waveform with a high data rate, the original waveform data is interpolated by a subsequent interpolation module and then is transmitted to the NCO module 123 for processing. The waveform generating unit 120 may sequentially generate a front shield waveform, a rear shield waveform, an intra-pulse shield waveform, and a working waveform in time division, and may also superimpose these waveforms to implement digital multi-beam transmission.
In one embodiment, an up-conversion link system for a wideband digital TR chip includes: a control word analyzing unit 110, configured to perform data analysis on control word information received from an external system to obtain a waveform type and working mode information required by an up-conversion link; a waveform generating unit 120 connected to the control word parsing unit 110, the waveform generating unit 120 generating a waveform signal according to the type of the waveform; an external waveform receiving and storing unit 130, connected to the control word parsing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analyzing unit 110 and the waveform generating unit 120, and the data processing unit 140 is configured to perform amplitude phase compensation, intra-channel orthogonality correction, and inter-channel consistency compensation on the waveform signal; and a DAC IP core unit 150 connected to the data processing unit 140, where the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generating unit 120 includes: the various waveform code generating module 121 is connected to the control word parsing unit 110, and the waveform code generating module 121 is configured to generate a corresponding waveform signal according to the control word information parsed by the control word parsing unit 110; a Cordic waveform generating module 122 connected to the waveform code generating module 121, wherein the Cordic waveform generating module 122 is configured to convert the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generating module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signal to realize frequency phase adjustment on the waveform; and an input end of the amplitude adjusting module 124 is connected with the NCO module 123, an output end of the amplitude adjusting module 124 is connected with the data processing unit 140, and the amplitude adjusting module 124 is configured to perform waveform amplitude adjustment on the IQ quadrature signal and output the IQ quadrature signal to the data processing unit 140. The waveform code generating module 121 includes at least any two of the following: the device comprises a linear frequency modulation module, a phase coding module, an FSK module, a single carrier frequency module and a non-linear frequency modulation module.
Referring to fig. 3 and 4, fig. 3 is a schematic diagram of an interpolation module of an up-conversion link system suitable for a wideband digital TR chip according to another embodiment of the present invention; fig. 4 is a block diagram of an NCO module 123 of the up-conversion link system suitable for the wideband digital TR chip according to another embodiment of the present invention.
In one embodiment, an up-conversion link system for a wideband digital TR chip includes: a control word analyzing unit 110, configured to perform data analysis on control word information received from an external system to obtain a waveform type and working mode information required by an up-conversion link; a waveform generating unit 120 connected to the control word parsing unit 110, the waveform generating unit 120 generating a waveform signal according to the type of the waveform; an external waveform receiving and storing unit 130, connected to the control word parsing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analyzing unit 110 and the waveform generating unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; and a DAC IP core unit 150 connected to the data processing unit 140, where the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generating unit 120 includes: a plurality of waveform code generating modules 121 connected to the control word parsing unit 110, the waveform code generating modules 121 being configured to generate corresponding waveform signals according to the control word information parsed by the control word parsing unit 110; a Cordic waveform generating module 122 connected to the waveform code generating module 121, wherein the Cordic waveform generating module 122 is configured to convert the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generating module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signal to realize frequency phase adjustment on the waveform; and an input end of the amplitude adjusting module 124 is connected with the NCO module 123, an output end of the amplitude adjusting module 124 is connected with the data processing unit 140, and the amplitude adjusting module 124 is configured to perform waveform amplitude adjustment on the IQ quadrature signal and output the IQ quadrature signal to the data processing unit 140.
The waveform generating unit 120 further includes: a FIFO control module connected to the external waveform receiving and storing unit 130, the waveform generating unit 120 reading the designated external waveform data from the external waveform receiving and storing unit 130 according to the read-write control timing requirement of the FIFO control module; and the interpolation module is connected with the FIFO control module and the NCO module 123 and is used for carrying out interpolation processing on the external waveform data and outputting the external waveform data to the NCO module 123. The interpolation module comprises: a configuration register for setting an interpolation multiple to the external waveform data; and the FIR filter is connected with the configuration register and is used for filtering the external waveform data after interpolation so as to eliminate high-frequency noise generated by interpolation.
The interpolation module supports 1/2/4/8/16 times of adjustable up-conversion interpolation, and the interpolation times are set by a configuration register. To remove the high frequency noise that occurs during interpolation, a FIR filter filters the data after each x2 interpolation. Wherein, the 1-2 interpolation is followed by a 59-order fixed coefficient FIR filter, the 2-4 interpolation is followed by a 23-order FIR filter, and the filters after the 4-8/8-16 two interpolators are 11-order filters. The filter with fixed coefficients is a plurality of Wallace trees, and a final result is generated after multiple times of combination. The delay and the area occupation of the filter with fixed coefficients are less, and the delay of each FIR filter is 2-3 clock cycles.
The NCO module 123 adopts a pipeline structure, continuously performs accumulation iteration on the phase under the initial phase control word and the frequency control word, performs quadrant judgment on the input angle value before calculation, then converts the input angle value into a range of 0-90 degrees for calculation, and finally inversely converts the input angle value into the original quadrant to obtain a final result. The state register controls the object limit conversion module by judging the highest 2 bits of the input angle, and both the frequency control word and the initial phase control word are 32 bits.
The external waveform receiving and storing unit 130 stores the waveform data transmitted from the optical fiber into three FIFOs with 4K size according to the waveform data receiving protocol requirement of Table 1, and the waveform data corresponds to a front shield waveform, a rear shield waveform and a working waveform respectively, and the data receiving rate is 10Gbps. When the waveform generating unit 120 needs to read the waveform data, the three FIFOs are read and written by the FIFO control module according to the timing sequence required by the waveform generation.
TABLE 1
Figure BDA0003735671340000111
Figure BDA0003735671340000121
Referring to fig. 5, fig. 5 is a block diagram of a data processing unit 140 of an up-conversion link system suitable for a wideband digital TR chip according to another embodiment of the present invention.
In one embodiment, an upconversion link system suitable for use with a wideband digital TR chip includes: a control word analyzing unit 110, configured to perform data analysis on control word information received from an external system to obtain a waveform type and working mode information required by an up-conversion link; a waveform generating unit 120 connected to the control word parsing unit 110, the waveform generating unit 120 generating a waveform signal according to the type of the waveform; an external waveform receiving and storing unit 130, connected to the control word parsing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analyzing unit 110 and the waveform generating unit 120, and the data processing unit 140 is configured to perform amplitude phase compensation, intra-channel orthogonality correction, and inter-channel consistency compensation on the waveform signal; and a DAC IP core unit 150 connected to the data processing unit 140, where the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generating unit 120 includes: the various waveform code generating module 121 is connected to the control word parsing unit 110, and the waveform code generating module 121 is configured to generate a corresponding waveform signal according to the control word information parsed by the control word parsing unit 110; a Cordic waveform generating module 122 connected to the waveform code generating module 121, wherein the Cordic waveform generating module 122 is configured to convert the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generating module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signal to realize frequency phase adjustment on the waveform; and an input end of the amplitude adjusting module 124 is connected with the NCO module 123, an output end of the amplitude adjusting module 124 is connected with the data processing unit 140, and the amplitude adjusting module 124 is configured to perform waveform amplitude adjustment on the IQ quadrature signal and output the IQ quadrature signal to the data processing unit 140.
The data processing unit 140 includes: the equalization filtering module is connected with the waveform generating unit 120, and is used for performing equalization filtering processing on the IQ orthogonal signal output by the waveform generating unit 120 so as to complete phase amplitude consistency compensation of the IQ orthogonal signal in a large bandwidth; the anti-Sinc module is connected with the balanced filtering module and is used for carrying out anti-Sinc function processing on the IQ orthogonal signal so as to eliminate amplitude inconsistency of a wide frequency band during frequency conversion; the decimal delay module is connected with the inverse Sinc module and used for adjusting the clock period of the waveform group delay; the IQ orthogonal correction and direct current offset module is connected with the decimal delay module and is used for carrying out orthogonal correction and direct current offset compensation on the IQ signal; and the diter module is connected with the IQ orthogonal correction and direct current offset module and is used for reducing output spurs of the DAC caused by quantization errors.
The data processing unit 140 includes: the device comprises an equalization filtering module, an inverse Sinc module, a decimal delay module, an IQ (in-phase quadrature) correction and direct current offset module and a diter module. After waveform data output by the waveform generating unit 120 enters the data processing unit 140, phase amplitude consistency compensation of the waveform data in a large bandwidth is completed through a configurable FIR complex equalization filtering module containing 63-order coefficients, amplitude inconsistency of a frequency band of a subsequent DAC in frequency conversion is eliminated through an inverse sinc function, and the inverse sinc function is a 9-order fixed coefficient FIR. The decimal delay module adjusts the clock period of the waveform group delay, and the IQ correction module realizes the orthogonal correction and the direct current offset compensation of the IQ signals. The dither module may reduce output spurs of the DAC due to quantization errors. The modules are all bypassable, and all adjustment parameters are configurable so as to meet the requirements under different application backgrounds.
Referring to fig. 6 and 7, fig. 6 is a block diagram of a fractional delay module of an up-conversion link system suitable for a wideband digital TR chip according to another embodiment of the present invention; fig. 7 is a schematic diagram of a diter module of an up-conversion link system suitable for a wideband digital TR chip according to another embodiment of the present invention.
In one embodiment, an upconversion link system suitable for use with a wideband digital TR chip includes: a control word analyzing unit 110, configured to perform data analysis on control word information received from an external system to obtain a waveform type and working mode information required by an up-conversion link; a waveform generating unit 120 connected to the control word parsing unit 110, the waveform generating unit 120 generating a waveform signal according to the type of the waveform; an external waveform receiving and storing unit 130, connected to the control word parsing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analyzing unit 110 and the waveform generating unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; and a DAC IP core unit 150 connected to the data processing unit 140, where the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The waveform generating unit 120 includes: the various waveform code generating module 121 is connected to the control word parsing unit 110, and the waveform code generating module 121 is configured to generate a corresponding waveform signal according to the control word information parsed by the control word parsing unit 110; a Cordic waveform generating module 122 connected to the waveform code generating module 121, wherein the Cordic waveform generating module 122 is configured to convert the waveform signal into an IQ quadrature signal with a corresponding frequency phase; the NCO module 123 is connected with the Cordic waveform generating module 122, and the NCO module 123 is used for carrying out multiplication and addition operation on the IQ orthogonal signal to realize frequency phase adjustment on the waveform; and an input end of the amplitude adjusting module 124 is connected with the NCO module 123, an output end of the amplitude adjusting module 124 is connected with the data processing unit 140, and the amplitude adjusting module 124 is configured to perform waveform amplitude adjustment on the IQ quadrature signal and output the IQ quadrature signal to the data processing unit 140.
The data processing unit 140 includes: the equalization filtering module is connected with the waveform generating unit 120, and is used for performing equalization filtering processing on the IQ orthogonal signal output by the waveform generating unit 120 so as to complete phase amplitude consistency compensation of the IQ orthogonal signal in a large bandwidth; the inverse Sinc module is connected with the balanced filtering module and is used for carrying out inverse Sinc function processing on the IQ orthogonal signals so as to eliminate amplitude inconsistency of a wide frequency band during frequency conversion; the decimal delay module is connected with the inverse Sinc module and used for adjusting the clock period of the waveform group delay; the IQ orthogonal correction and direct current offset module is connected with the decimal delay module and is used for carrying out orthogonal correction and direct current offset compensation on the IQ signal; and the diter module is connected with the IQ orthogonal correction and direct current offset module and is used for reducing output spurs of the DAC caused by quantization errors.
The decimal delay module comprises: a coefficient storage ROM for storing a normalization coefficient; fine fractional delay, connected to coefficient storage ROM; coarse fractional delay connected with the coefficient storage ROM and fine fractional delay; the integer time delay is connected with the coefficient storage ROM and the coarse adjustment decimal time delay; and the normalization multiplier is connected with the coefficient storage ROM and the integer time delay.
It is understood that the delay module internally comprises five parts of a coefficient storage ROM, a fine fractional delay, a coarse fractional delay, an integer delay and a normalization multiplier. Where the fine fractional delay is implemented using a 9 th order FIR filter. The delay time is 0-0.200 cycle, the adjustment interval is 0.002 cycle, and is controlled by 7-bit coefficient. The coarse fractional delay is implemented using a 7 th order FIR filter. Delay time 0-0.875 period, adjustment interval 0.125 period, controlled by 3-bit coefficient. The integer delay is 0-3 beats and is controlled by a 2-bit control code. The normalization multiplier is a 16x16 multiplier, and the 16-bit normalization coefficient is provided by the coefficient storage ROM. By modifying the weighting coefficients of the filter, the phase of the data can be adjusted, thereby changing the delay time of the data. The weighting coefficient corresponding to each delay is set, the delay time is selected by an external control code, and the input and output of the decimal delay are both 16 bits.
The dither module adopts an M sequence structure, generates a pseudorandom sequence by carrying out linear feedback through N registers, has periodicity, the coefficient of each register is determined by an intrinsic polynomial corresponding to the order N, both the N and the intrinsic polynomial can be set through a control word, the default initialization state N is 8, and the intrinsic polynomial is 1+X2+X3+X4+X8。
Referring to fig. 8, fig. 8 is a block diagram of an analog DAC IP core of an up-conversion link system suitable for a wideband digital TR chip according to another embodiment of the present invention.
In one embodiment, an upconversion link system suitable for use with a wideband digital TR chip includes: a control word parsing unit 110, configured to perform data parsing on control word information received from an external system to obtain a waveform type and working mode information required by an up-conversion link; a waveform generating unit 120 connected to the control word parsing unit 110, the waveform generating unit 120 generating a waveform signal according to the type of the waveform; an external waveform receiving and storing unit 130, connected to the control word parsing unit 110 and the waveform generating unit 120, the external waveform receiving and storing unit 130 being configured to receive and store external waveform data; the data processing unit 140 is connected with the control word analyzing unit 110 and the waveform generating unit 120, and the data processing unit 140 is used for performing amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal; and a DAC IP core unit 150 connected to the data processing unit 140, where the DAC IP core unit 150 is configured to perform digital-to-analog conversion on the waveform signal.
The DAC IP core can adopt a 28nm technology, is a four-channel 12bit, has the highest sampling rate of 640Msps, can provide differential current output and supports single-ended or differential configuration. The supply voltage was 0.9V and 1.8V. The circuit mainly comprises a 2-path input latch, a 2-path DAC conversion circuit, a time sequence generation circuit and a bias generation circuit. The output current can be used for directly driving two external resistive loads to obtain two complementary single-ended output voltages, and can also be used for driving an external transformer or amplifier to obtain a single-ended output voltage. The DAC adopts a current steering structure of segmented thermometer decoding, controls the output of currents generated by different bit weight current sources by inputting a digital signal sequence, converts the digital signals into analog signals, and can realize very high data updating rate, 12-bit inherent static precision and very good dynamic characteristics. An internal bandgap voltage reference and an external resistor are used to set the full scale current of the DAC. The DAC is integrated in the digital TR chip in an IP mode, and registers of a working mode, a full scale, starting time and the like are directly configured by control words.
One of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention.
The above-described embodiments of the present invention should not be construed as limiting the scope of the present invention. Any other corresponding changes and modifications made according to the technical idea of the present invention should be included in the protection scope of the claims of the present invention.

Claims (10)

1. An upconversion link system adapted for use with a wideband digital TR chip, comprising:
the control word analysis unit is used for carrying out data analysis on control word information received from an external system to obtain the waveform type and the working mode information required by the work of the up-conversion link;
the waveform generating unit is connected with the control word analyzing unit and generates a waveform signal according to the waveform type;
the external waveform receiving and storing unit is connected with the control word analyzing unit and the waveform generating unit and is used for receiving and storing external waveform data;
the data processing unit is connected with the control word analysis unit and the waveform generation unit and is used for carrying out amplitude phase compensation, intra-channel orthogonality correction and inter-channel consistency compensation on the waveform signal;
and the DAC IP core unit is connected with the data processing unit and is used for carrying out digital-to-analog conversion on the waveform signal.
2. The upconversion link system suitable for use in a wideband digital TR chip according to claim 1, wherein the waveform generation unit comprises:
the multi-waveform code generating module is connected with the control word analyzing unit and is used for generating corresponding waveform signals according to the control word information analyzed by the control word analyzing unit;
the Cordic waveform generation module is connected with the waveform code generation module and is used for converting the waveform signal into an IQ (in-phase quadrature) signal with a corresponding frequency phase;
the NCO module is connected with the Cordic waveform generating module and is used for carrying out multiplication and addition operation on the IQ orthogonal signal to realize frequency phase adjustment on the waveform;
and the input end of the amplitude adjusting module is connected with the NCO module, the output end of the amplitude adjusting module is connected with the data processing unit, and the amplitude adjusting module is used for carrying out waveform amplitude adjustment on the IQ orthogonal signal and outputting the IQ orthogonal signal to the data processing unit.
3. The upconverting link system suitable for use with a wideband digital TR chip according to claim 2, wherein the waveform generation unit further comprises:
the FIFO control module is connected with the external waveform receiving and storing unit, and the waveform generating unit reads the specified external waveform data from the external waveform receiving and storing unit according to the read-write control time sequence requirement of the FIFO control module;
and the interpolation module is connected with the FIFO control module and the NCO module and is used for carrying out interpolation processing on the external waveform data and outputting the external waveform data to the NCO module.
4. The upconversion link system suitable for use with a wideband digital TR chip according to claim 3, wherein the waveform generation unit further comprises:
and the sub control word analysis module is connected with the control word analysis unit, the waveform code generation module, the interpolation module, the NCO module, the amplitude adjustment module and the FIFO control module, and is used for further analyzing the control word information analyzed by the control word analysis unit to obtain all configuration information required by final waveform generation.
5. The upconversion link system adapted for use with a wideband digital TR chip as claimed in claim 2, wherein the waveform code generating module comprises at least any two of:
the device comprises a linear frequency modulation module, a phase coding module, an FSK module, a single carrier frequency module and a non-linear frequency modulation module.
6. The upconversion link system adapted for use with a wideband digital TR chip according to claim 3, wherein the interpolation module comprises:
a configuration register for setting an interpolation multiple of the external waveform data;
and the FIR filter is connected with the configuration register and is used for filtering the external waveform data after interpolation so as to eliminate high-frequency noise generated by interpolation.
7. The upconversion link system adapted for use with a wideband digital TR chip according to claim 2, wherein the data processing unit comprises:
the balanced filtering module is connected with the waveform generating unit and is used for carrying out balanced filtering processing on the IQ orthogonal signal output by the waveform generating unit so as to finish phase amplitude consistency compensation of the IQ orthogonal signal in a large bandwidth;
the inverse Sinc module is connected with the equalizing filter module and is used for performing inverse Sinc function processing on the IQ orthogonal signal so as to eliminate amplitude inconsistency of a wide frequency band during frequency conversion;
the decimal time delay module is connected with the reverse Sinc module and used for adjusting the clock period of the waveform group delay;
the IQ orthogonal correction and direct current bias module is connected with the decimal delay module and is used for carrying out orthogonal correction and direct current bias compensation on IQ signals;
and the diter module is connected with the IQ orthogonal correction and direct current offset module and is used for reducing output spurs of the DAC caused by quantization errors.
8. The upconverting link system according to claim 7, wherein the fractional delay module includes:
a coefficient storage ROM for storing a normalization coefficient;
a fine fractional delay coupled to the coefficient storage ROM;
a coarse fractional delay coupled to the coefficient storage ROM and the fine fractional delay;
the integer time delay is connected with the coefficient storage ROM and the coarse adjustment decimal time delay;
and the normalization multiplier is connected with the coefficient storage ROM and the integer time delay.
9. The upconversion link system adapted for use with a wideband digital TR chip according to claim 1, wherein the DAC IP core unit comprises:
the device comprises two paths of input latches, a time sequence generating circuit, a bias generating circuit and two paths of DAC cores, wherein the input latches are connected with the DAC cores, the time sequence generating circuit is arranged between the two paths of input latches, and the time sequence generating circuit and the bias generating circuit are connected between the two paths of DAC cores.
10. An up-conversion link apparatus adapted for a wideband digital TR chip, comprising: eight identical up-conversion channels provided with an up-conversion link system suitable for a wideband digital TR chip as claimed in any one of claims 1 to 9.
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