CN115097897B - Staggered weaving output method of signal generator - Google Patents
Staggered weaving output method of signal generator Download PDFInfo
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- CN115097897B CN115097897B CN202210546393.0A CN202210546393A CN115097897B CN 115097897 B CN115097897 B CN 115097897B CN 202210546393 A CN202210546393 A CN 202210546393A CN 115097897 B CN115097897 B CN 115097897B
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Abstract
The invention aims to provide a staggered weaving output method of a signal generator capable of effectively improving odd-numbered harmonics. The invention comprises the following steps: firstly, a phase generator transmits a phase signal, a frequency generator transmits a frequency signal, and a phase accumulator adds the phase signal and the frequency signal to form a first superposition signal; secondly, the phase shifter changes the first superimposed signal into a phase-shifting signal after phase staggering, adds the first superimposed signal and the phase-shifting signal corresponding to the first superimposed signal to form a second superimposed signal, and then outputs the second superimposed signal to the data selector to finish phase shifting; thirdly, the cycle counter outputs a plurality of frequency division signals alternately to the data selector in a certain frequency period; and finally, after the data selector receives a plurality of frequency division signals, alternately selecting a plurality of second superposition signals, and respectively selecting a plurality of corresponding channels for outputting to form staggered sine signals. The invention is applied to the technical field of signal generators.
Description
Technical Field
The invention is applied to the technical field of signal generators, and particularly relates to a staggered weaving output method of a signal generator.
Background
In automated test systems (ATE for short), it is often necessary to use a signal generator to generate arbitrary waveforms, in particular sinusoidal signals. In some test applications, such as the test of an analog-to-digital converter (ADC) chip special for audio, a high-fidelity sinusoidal signal needs to be generated, the total harmonic distortion of the sinusoidal signal at 1V output is required to be less than-100 dB, and a special audio signal generator can be usually selected, but the frequency of the sinusoidal signal output cannot exceed MHz, and an arbitrary waveform with adjustable amplitude cannot be output.
In order to meet the index requirements of the test on the instrument, only based on the actual performance of the signal generator, a proper filter is designed for a signal in a specific frequency band, harmonic components in the output signal of the signal generator are filtered, or different signal generator combinations are selected for different test items, but the combination of the system becomes complex, and for some high-speed ADCs, proper signal generators are very difficult to select.
The harmonic components output by the signal generator can be generally divided into even harmonics and odd harmonics, and the harmonic distortion of the signal generator is mainly 3 rd order or 5 th order. Even harmonics can be easily counteracted by a differential circuit, odd harmonics are difficult to improve by optimizing circuit design, and only high-performance components can be selected in the circuit design, so that the cost is high. The problems can be well solved if a staggered weaving output method of the signal generator, which can reduce the cost, avoid complex system combination and effectively improve odd-order harmonics, can be designed.
Disclosure of Invention
The invention aims to solve the technical problem of overcoming the defects of the prior art, and provides the staggered weaving output method of the signal generator, which can reduce the cost, avoid complex system combination and effectively improve odd-order harmonics.
The technical scheme adopted by the invention is as follows: the signal generator applied to the staggered output method comprises a data processor and a sampling clock, wherein the data processor comprises a phase generator, a frequency generator, a phase accumulator, a cycle counter, a data selector and at least one phase shifter, the phase generator and the frequency generator are in signal connection with the phase accumulator, the phase accumulator is in signal connection with the phase shifter, the phase shifter is in signal connection with the data selector, the data selector is in signal connection with the cycle counter, the cycle counter and the phase generator are in signal connection with the sampling clock, and the staggered output method comprises the following steps:
s1, initializing a phase signal to be zero by the phase generator, transmitting the phase signal to the phase accumulator according to the sampling period of the sampling clock, and transmitting a frequency signal to the phase accumulator according to the output frequency by the frequency generator;
s2, adding the received phase signal and the frequency signal by the phase accumulator to form a first superposition signal, and transmitting the first superposition signal to the phase shifter;
s3, under the change time of the sampling clock, the phase signal output by the phase generator is automatically updated, and the first superposition signal output by the phase accumulator is automatically stored;
s4, if the first superposition signal output by the phase accumulator exceeds a preset upper limit, jumping to the step S1, and re-executing the steps S2, S3 and S4, and if the first superposition signal output by the phase accumulator does not exceed the preset upper limit, executing the next step;
s5, the phase shifter changes the received first superimposed signal into a phase-shifting signal after phase-shifting, adds the first superimposed signal and the phase-shifting signal corresponding to the first superimposed signal to form a second superimposed signal, and then outputs the second superimposed signal to the data selector to finish phase shifting;
s6, the cycle counter circularly calculates the number of the adopted cycles of the sampling clock and alternately outputs a plurality of frequency division signals to the data selector in a certain frequency cycle;
s7, after the data selector receives a plurality of frequency division signals, the data selector alternately selects a plurality of second superposition signals in the step S5, and respectively selects a plurality of corresponding channels to output so as to form staggered sine signals.
Further, the staggering intersection output method further includes step S8: and outputting the sine signal in the step 7 by a table look-up mode.
Further, the table look-up method includes the following steps:
A. uniformly sampling and quantizing a sine signal in a complete period, solidifying quantized values in a storage of the data processor to form a sine wave table, and pointing a read pointer to the table head of the sine wave table, wherein an index address of the sine wave table is an indication value of the read pointer;
B. and linearly increasing the indication value of the read pointer, looking up the table, outputting a sine signal with a complete period point by point, and when the table tail of the sine wave table is reached, redirecting the read pointer to the table head of the sine wave table, and outputting the sine signal continuously in a circulating manner.
Further, the signal generator further comprises a digital-to-analog converter, and the sampling clock and the data selector are both in signal connection with the digital-to-analog converter; the staggering intersection output method further comprises the step S9: the data selector transmits the sinusoidal signal in the step B to the digital-to-analog converter, which converts the received sinusoidal signal into an analog signal.
Further, the signal generator further comprises an analog filter, and the digital-to-analog converter is in signal connection with the analog filter; the staggering intersection output method further comprises the step S10: the digital-to-analog converter transmits the analog signal to the analog filter, and after the analog filter receives the analog signal, the analog filter filters out the mirror image frequency which is symmetrical about the Nyquist frequency in the analog signal, and finally outputs the sine signal without odd harmonics.
Further, in the step S5, the phase of the phase-shifted signal and the phase of the first superimposed signal are 180 degrees different.
The beneficial effects of the invention are as follows: by adjusting the phase of the first superimposed signal, the phase of the adjusted phase-shifted signal and the phase of the first superimposed signal before adjustment are just 180 degrees different, and the original first superimposed signal and the phase-shifted signal after adjustment are alternately input into the data selector, so that the first superimposed signal and the harmonic signal of the phase-shifted signal are superimposed together, and the harmonic signal can be completely eliminated due to the opposite phases of the two signals. Therefore, the invention can effectively improve odd harmonic performance of the existing hardware, is simple to realize by using common arbitrary waveform signal generator and other general instruments in laboratory, and can avoid complex system combination, has low requirement on hardware performance and reduces cost.
Drawings
FIG. 1 is a schematic diagram of an improved digital-to-analog converter odd harmonic model of an out-of-phase sinusoidal signal;
FIG. 2 is a first schematic diagram of the signal generator;
FIG. 3 is a schematic diagram of an arbitrary waveform generator with the elimination of odd harmonic distortion by the present invention;
FIG. 4 is a second schematic diagram of the signal generator;
fig. 5 is a graph comparing waveform changes before and after using the present invention.
Detailed Description
Example 1
As shown in fig. 1, in this embodiment, the principle of the present invention is as follows:
in devices such as arbitrary waveform generators (AWG for short), the sinusoidal signal is typically supplied in digital form to a digital-to-analog converter (DAC for short), converted by the DAC into a corresponding analog signal, and output through an associated analog filter circuit. It is generally believed that the non-linearity of the DAC or the analog filter circuit itself can lead to the occurrence of harmonic signals, and for simplicity of analysis, assuming that the DAC has very significant 3 rd harmonic distortion, the mathematical model corresponding to the DAC is as follows:wherein a is 1 And a 3 The coefficients of the polynomial, D, are the digital signals input to the DAC.
If the DAC input discrete digital signal is:where f is the frequency of the sinusoidal signal to be generated, T S And n is the sampling point sequence number. The output is: />It can be seen that the output signal Y 0 Contains 3 rd harmonic components, if compared with D 0 Signal, add sine signal D with certain phase shift 1 ：The output becomes: />After a certain phase is shifted, the amplitude of the fundamental component in the output signal can be changed, and the phase shift of the 3 rd harmonic can be amplified by 3 times. If the adjustment phase is +>Y is then 0 、Y 1 The 3 rd harmonic signals in the (a) are just opposite in phase. Since the output characteristic of the DAC is a 0-order hold, it can hold outputting the last sample value. If let D 0 、D 1 Alternate input DAC, i.e. let D 0 、D 1 After interleaving, the output of DAC will have Y at the same time 0 、Y 1 Signal, then Y 0 、Y 1 The 3 rd harmonics in (c) will be completely cancelled.
As shown in fig. 2 and 3, in the present embodiment, the signal generator applied to the interleaving output method includes a data processor and a sampling clock 1, the data processor includes a phase generator 2, a frequency generator 3, a phase accumulator 4, a loop counter 5, a data selector 6, and a phase shifter 7, the phase generator 2 and the frequency generator 3 are both in signal connection with the phase accumulator 4, the phase accumulator 4 is in signal connection with the phase shifter 7, the phase shifter 7 is in signal connection with the data selector 6, the data selector 6 is in signal connection with the loop counter 5, the loop counter 5 and the phase generator 2 are both in signal connection with the sampling clock 1, the modulus of the loop counter 5 is 4, and the interleaving output method includes the following steps:
s1, initializing a phase signal to be zero by the phase generator 2, transmitting the phase signal to the phase accumulator 4 according to the sampling period of the sampling clock 1, and transmitting a frequency signal to the phase accumulator 4 according to an output frequency by the frequency generator 3;
s2, the phase accumulator 4 adds the received phase signal and the frequency signal to form a first superposition signal, and the first superposition signal is transmitted to the phase shifter 7;
s3, under the change time of the sampling clock 1, the phase signal output by the phase generator 2 is automatically updated, and the first superposition signal output by the phase accumulator 4 is automatically stored;
s4, if the first superposition signal output by the phase accumulator 4 exceeds a preset upper limit, jumping to the step S1, and re-executing the steps S2, S3 and S4, and if the first superposition signal output by the phase accumulator 4 does not exceed the preset upper limit, executing the next step;
s5, the phase shifter 7 changes the received first superposition signal into a phase-shifting signal after phase staggering, adds the first superposition signal and the phase-shifting signal corresponding to the first superposition signal to form a second superposition signal, and then outputs the second superposition signal to the data selector 6 to finish phase shifting;
s6, the cycle counter 5 calculates the number of the adoption periods of the sampling clock 1 through a cycle, and alternately outputs four frequency division signals of 0,1,2 and 3 to the data selector 6 in a frequency division frequency period of 4;
s7, after the data selector 6 receives the 4 frequency division signals, 4 second superposition signals in the step S5 are alternately selected, and 4 corresponding channels are respectively selected for output, so that staggered sinusoidal signals are formed.
As shown in fig. 2 and 3, in this embodiment, the method for outputting a false intersection further includes step S8: and outputting the sine signal in the step 7 by a table look-up mode.
As shown in fig. 2 and 3, in this embodiment, the table look-up method includes the following steps:
A. uniformly sampling and quantizing a sine signal in a complete period, solidifying quantized values in a memory of the data processor to form a sine wave table 8, and pointing a read pointer to the table head of the sine wave table 8, wherein an index address of the sine wave table 8 is an indication value of the read pointer;
B. and linearly increasing the indication value of the read pointer, looking up the table, outputting a sine signal with a complete period point by point, and when the table tail of the sine wave table 8 is reached, redirecting the read pointer to the table head of the sine wave table 8, and outputting the sine signal continuously in a circulating manner. The indication value of the read pointer is a scanning signal which changes according to sawtooth wave, and the period of the indication value is the period of the output sine wave. In other words, the indication value of the read pointer determines the instantaneous phase of the sine wave at this moment, and the phase of the output sine wave at this moment can be changed by adjusting the indication value of the read pointer.
As shown in fig. 2 and 3, in the present embodiment, the signal generator further includes a digital-to-analog converter 9, and the sampling clock 1 and the data selector 6 are both connected to the digital-to-analog converter 9 in a signal manner; the staggering intersection output method further comprises the step S9: the data selector 6 transmits the sinusoidal signal in step B to the digital-to-analog converter 9, which digital-to-analog converter 9 converts the received sinusoidal signal into an analog signal.
As shown in fig. 2 and 3, in the present embodiment, the signal generator further includes an analog filter 10, and the digital-to-analog converter 9 is signal-connected to the analog filter 10; the staggering intersection output method further comprises the step S10: the digital-to-analog converter 9 transmits the analog signal to the analog filter 10, and after the analog filter 10 receives the analog signal, the image frequency symmetric about the nyquist frequency in the analog signal is filtered out, and finally a sine signal without odd harmonics is output.
As shown in fig. 2 and 3, in the present embodiment, in the step S5, the phase of the phase-shifted signal and the phase of the first superimposed signal are 180 degrees different.
In this embodiment, by adjusting the phase of the first superimposed signal, the phase of the phase-shifted signal after adjustment and the phase of the first superimposed signal before adjustment are just 180 degrees different, and the original first superimposed signal and the phase-shifted signal after adjustment are alternately input into the data selector 6, then the harmonic signals of the first superimposed signal and the phase-shifted signal are superimposed, and because the phases of the two signals are opposite, the harmonic signals can be completely eliminated. Therefore, the invention can effectively improve odd harmonic performance of the existing hardware, is simple to realize by using common arbitrary waveform signal generator and other general instruments in laboratory, and can avoid complex system combination, has low requirement on hardware performance and reduces cost.
As shown in fig. 2 and 3, in this embodiment, for an AWG type of instrument, a DAC is typically used to output an analog signal, and the input signal of the DAC is typically from a DSP or a dedicated DDS chip. And its output would also require the necessary analog filters. In another aspect, both the finished AWG and the two types of chips support the user to modify their internal waveform files to customize the output of arbitrary waveforms.
For an AWG that has been installed in an ATE test system, the foregoing method of eliminating odd harmonics may be implemented by custom waveform functions provided to the user by the AWG. Only the error interleaved sine wave file is needed to be calculated in advance, and the wave table in the AWG is updated through the self-defined waveform function of the AWG, so that hardware is not required to be modified or an additional filter is not required to be added. For a sinusoidal signal of amplitude a and frequency f, the sample values after the interleaving are:
wherein T is S Is the sampling period; the above equation can produce a misinterleaved signal that eliminates the 3 rd and 5 th harmonics common in AWG outputs.
Example two
As shown in fig. 4 and 5, in the present embodiment, the present embodiment is different from the first embodiment in that: the three-part structure of the phase generator 2, the frequency generator 3 and the phase accumulator 4 is replaced by the sine wave generator 11, i.e. the sine wave generator 11 is in signal connection 7 with the phase shifter, the sine wave generator 11 is in signal connection with the sampling clock 1, and the modulus of the cycle counter is 2 and is not provided with the sine wave table 8.
For more versatility, redefining the input signal of the digital-to-analog converter 9 as X 0 、X 1 The interleaved signal is D, and its expression is as follows:
，
where a is the amplitude of the sine wave,is the phase of a sinusoidal signal and satisfies +.>。
The signal interleaving alternately gates the input signals mainly through the data selector 6. The data selector 6 will address-encode each input channel, i.e. each channel corresponds to an address, which will send the input of the corresponding channel to the output port based on the input address signal. The embodiment requires two inputs to be selected, so that only one address line is required, which gates X when 0 0 Strobe X at 1 1 . The digital sampling system will have a said sampling clock 1, the period of which is generally equal to the sampling period T S I.e. the spacing of two adjacent sampling points output by the sine wave generator 11. The sine wave generator 11 generates a sine wave at a sampling rate f S Periodically outputting sinusoidal signal X 0 ，X 0 Phase-shifting by the phase shifter 7 to become X 1 . The modulo-2 cycle counter 5 will be based on f S Signal output sum f S Phase synchronized divide-by-two signal 0.5f S . This frequency division signal controls the data selector 6 to alternately select X 0 、X 1 Thus, an interleaved signal D is realized.
Finally, the interleaved signal D is sent to the digital-to-analog converter 9 and converted to an analog signal. As shown in fig. 5, when the waveforms of the signals of the nodes are observed, compared with the case of directly inputting the sine wave, the output Y of the digital-to-analog converter 9 after the interleaving has no 3 rd order harmonic, but has an image frequency symmetrical about the nyquist frequency, the image frequency needs to be filtered by an analog filter, and the waveform finally outputted after the filter is a pure sine signal without odd order harmonic.
Claims (5)
1. A method of staggering an output of a signal generator, the signal generator applied by the method of staggering an output comprising a data processor and a sampling clock (1), the data processor comprising a phase generator (2), a frequency generator (3), a phase accumulator (4), a cycle counter (5), a data selector (6) and at least one phase shifter (7), the phase generator (2) and the frequency generator (3) being in signal connection with the phase accumulator (4), the phase accumulator (4) being in signal connection with the phase shifter (7), the phase shifter (7) being in signal connection with the data selector (6), the data selector (6) being in signal connection with the cycle counter (5), the cycle counter (5) and the phase generator (2) being in signal connection with the sampling clock (1), characterized in that the method of staggering an output comprises the steps of:
s1, initializing a phase signal to be zero by the phase generator (2), transmitting the phase signal to the phase accumulator (4) according to the sampling period of the sampling clock (1), and transmitting a frequency signal to the phase accumulator (4) according to an output frequency by the frequency generator (3);
s2, adding the received phase signal and the frequency signal by the phase accumulator (4) to form a first superposition signal, and transmitting the first superposition signal to the phase shifter (7);
s3, under the change time of the sampling clock (1), the phase signal output by the phase generator (2) is automatically updated, and the first superposition signal output by the phase accumulator (4) is automatically stored;
s4, if the first superposition signal output by the phase accumulator (4) exceeds a preset upper limit, jumping to the step S1, and re-executing the steps S2, S3 and S4, and if the first superposition signal output by the phase accumulator (4) does not exceed the preset upper limit, executing the next step;
s5, the phase shifter (7) changes the received first superposition signal into a phase-shifting signal after misphasing, adds the first superposition signal and the phase-shifting signal corresponding to the first superposition signal to form a second superposition signal, and then outputs the second superposition signal to the data selector (6) to finish phase shifting; the phase of the phase-shifted signal and the phase of the first superimposed signal are 180 degrees apart;
s6, the cycle counter (5) calculates the number of the adopted cycles of the sampling clock (1) in a circulating way, and alternately outputs a plurality of frequency division signals to the data selector (6) in a certain frequency cycle;
s7, after the data selector (6) receives a plurality of frequency division signals, the second superposition signals in the step S5 are alternately selected, and a plurality of corresponding channels are respectively selected for output, so that staggered sinusoidal signals are formed.
2. A method of staggering output of a signal generator according to claim 1, characterized in that: the staggering intersection output method further comprises the step S8 of: and outputting the sine signal in the step 7 by a table look-up mode.
3. A method of staggering output of a signal generator according to claim 2, characterized in that: the table look-up method comprises the following steps:
A. uniformly sampling and quantizing a sine signal in a complete period, solidifying quantized values in a memory of the data processor to form a sine wave table (8), and pointing a read pointer to a table head of the sine wave table (8), wherein an index address of the sine wave table (8) is an indication value of the read pointer;
B. and linearly increasing the indication value of the read pointer, looking up the table, outputting a sine signal with a complete period point by point, and when the indication value reaches the tail of the sine wave table (8), redirecting the read pointer to the head of the sine wave table (8), and outputting the sine signal continuously in a circulating way.
4. A method of staggering output of a signal generator according to claim 3, characterized in that: the signal generator further comprises a digital-to-analog converter (9), and the sampling clock (1) and the data selector (6) are both in signal connection with the digital-to-analog converter (9); the staggering intersection output method further comprises the step S9: the data selector (6) transmits the sinusoidal signal in step B to the digital-to-analog converter (9), the digital-to-analog converter (9) converting the received sinusoidal signal into an analog signal.
5. A method of staggering output of a signal generator according to claim 4, wherein: the signal generator further comprises an analog filter (10), and the digital-to-analog converter (9) is in signal connection with the analog filter (10); the staggering intersection output method further comprises the step S10: the digital-to-analog converter (9) transmits the analog signal to the analog filter (10), the analog filter (10) filters out the mirror image frequency symmetrical about the Nyquist frequency in the analog signal after receiving the analog signal, and finally outputs the sine signal without odd harmonic.
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