CN117949949B - Pulse radar baseband signal acquisition processing method, device and medium - Google Patents
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Abstract
The invention provides a pulse radar baseband signal acquisition processing method, equipment and medium. Relates to the technical field of synthetic aperture radar signal processing. The method has the function of transmitting the linear frequency modulation pulse signals, and the parameters of the transmitted signals can be flexibly configured by the software of the upper computer. The method also has the functions of echo signal acquisition, demodulation and compression processing, and the data is stored in an upper computer through a PXIe high-speed transmission interface and is provided for subsequent image processing.
Description
Technical Field
The invention relates to the technical field of Synthetic Aperture Radar (SAR) signal processing, in particular to a pulse radar baseband signal acquisition processing method, device and medium.
Background
Baseband signal processing is an important ring in the processing flow of an SAR imaging system, signal indexes influence the resolution of the system, and signal quality can directly influence the imaging effect. The signals used in the SAR imaging system are linear frequency modulation signals, the frequency of the signals changes along with time, different resolutions require different bandwidths, and the system is required to have the capability of flexibly controlling the transmitted signals. The receiving link acquires the echo signal of the target, the data volume of the signal is large, the speed is high, and the rapid demodulation and high-speed transmission and storage of the signal are key of the receiving link.
In the SAR imaging system, the baseband signal processing comprises wideband linear frequency modulation signal generation in a transmitting link, the data processing in a receiving link comprises IQ demodulation, BAQ (Block adaptive Quantization) data compression algorithm and the like, and the waveform control and data storage upper computer system. The upper computer system can flexibly control the bandwidth time width of the waveform in real time and store the acquired data for subsequent image processing, wherein the parameter configuration from the upper computer to the baseband hardware and the high-speed data transmission from the baseband hardware to the upper computer are involved.
Conventional methods of chirp signal generation include analog methods and digital methods. Analog methods are typically implemented by controlling voltage-controlled oscillators with linear sawtooth voltages, but the stability and coherence of the signals are poor. Along with the development of digital signal processing technology, the influence caused by an analog device can be avoided through digital implementation, one method is waveform digital storage direct reading, a digital waveform result of a target waveform to be implemented is stored in a field programmable gate array FPGA (Field Programmable GATE ARRAY), waveform generation is realized through sampling and sending the stored waveform, and the method is simple but has poor flexibility and cannot adapt to application scenes of different signal parameters. Another implementation is a Direct Digital Synthesis (DDS) method, which uses a direct digital synthesis technique to accurately control the frequency, amplitude and phase of the output waveform, and has a high frequency resolution, so that rapid frequency switching can be achieved. The SAR system uses a linear frequency modulation wave signal, the frequency of the signal changes along with time, and in the FPGA system, parameters required by the DDS need to be calculated and input in real time. Parallel-serial conversion is also needed between the low-speed FPGA and the high-speed digital-to-analog converter DAC to realize high-speed large-bandwidth signals.
The key step of signal processing of a receiving link is orthogonal transformation of signals, the orthogonal transformation of the signals is realized by using an analog means in early stage, two analog local oscillation signals which are orthogonal to each other are required to be generated, the consistency of analog devices is difficult to control, and the analog devices are greatly influenced by environment, so that the two signals cannot be guaranteed to be completely orthogonal, errors are easy to generate, false signals are generated after the orthogonal transformation, and the subsequent signal processing is influenced. The digital method is commonly used as a low-pass filtering method, most of the methods relate to different low-pass filters, but are limited by the speed of an analog-to-digital (A/D) sampler, the high-speed analog-to-digital (A/D) sampling data has higher requirements on the low-pass filters, the higher the precision is, the more the number of stages of the filters is required, the more complex the implementation is, and the more the hardware resource consumption is.
Disclosure of Invention
The invention aims to solve the problems in the prior art and provides a method, equipment and medium for acquiring and processing a baseband signal of a pulse radar.
The invention is realized by the following technical scheme, the invention provides a pulse radar baseband signal acquisition processing method, which comprises a transmitting link part and a receiving link part;
The transmitting link part comprises an upper computer and an FPGA; the upper computer is communicated with the FPGA through a PCIe protocol, converts the waveform index into a waveform to generate a required parameter, and transmits the waveform index and the waveform switch control parameter to the FPGA, and the FPGA generates a digital waveform and emits a target waveform through a DAC of a daughter board in the FPGA;
The receiving link part acquires echo signals through band-pass sampling, the signals are subjected to quadrature demodulation to obtain baseband data, the baseband data is subjected to data size reduction through a compression algorithm, the compressed data are transmitted to the upper computer through a high-speed data channel, transmission enabling is controlled by the upper computer, and the upper computer stores the received compressed baseband data into a binary file for subsequent imaging processing.
Further, the implementation method of the transmitting link part specifically comprises the following steps:
Step 1: calculating waveform parameters; the direct digital synthesis technology DDS principle, the linear frequency modulation wave and the parallel-serial conversion principle are used for obtaining a calculation formula of an 8-path DDS input real-time phase value, so that the total is simplified into 5 control parameters, and the control parameters can be transmitted to a lower computer from an upper computer; the upper computer calculates 5 control parameters according to the signal parameters, the 5 control parameters are transmitted to the lower computer through the PCIe transmission channel, and the parameters are updated to the lower computer when the parameters are changed, so that the waveform real-time control is realized;
step 2: the lower computer transmits 5 control parameters of the waveform to the FPGA end through a parameter channel of PCIe communication, calculates 8 paths of parallel DDS real-time phases according to the control parameters, outputs 8 paths of signals according to the parallel DDS, and simultaneously controls the waveform output according to the pulse duration and the pulse interval time;
Step 3: the parallel signals are converted into serial high-speed signals through parallel-serial conversion, and the DAC converts the signals into analog signals according to configuration and transmits the analog signals out, so that the generation of the high-speed broadband signals is realized.
Further, according to the DDS waveform generation principle and the linear frequency modulation wave, an 8-channel initial phase codeword and a phase increment codeword are calculated, wherein the 8-channel initial phase codeword corresponds to the first 8 bits of final serial data, namely:
Where j is the channel number and is the number of channels, For the phase increment of the jth path, the variation over time,/>Representing the starting frequency of the chirp signal,/>Representing the sampling frequency, N representing the DDS phase accumulator data bit width, k representing the chirp frequency modulation factor.
Further, the initial phase codeword and the phase increment codeword are calculated and simplified into 5 control parameters by an upper computer、、/>、/>、/>Transmitting to FPGA;
Under the condition of waveform determination, the 5 control parameters are not changed, and the FPGA only carries out superposition calculation on the phase increment code word at any time; the parameter formula is as follows:
Wherein, Representing the phase increment of the ith data of the jth channel,/>The ith data representing the current channel.
Further, the implementation method of the receiving link part specifically comprises the following steps:
Step one: band-pass sampling, namely determining sampling frequency according to a band-pass sampling principle, and odd-even extracting a sampling sequence;
step two: polyphase filtering quadrature demodulation;
step three: BAQ 8:4 compression;
Step four: and uploading the data to an upper computer, framing the compressed data according to a protocol format, uploading the data to the upper computer through a PCIe high-speed channel when the upper computer requests the data, and storing the data as a binary file by the upper computer.
Further, in step one, a sampling sequence is obtained when the sampling frequency f s= 4f0/(2m+1) (variable m=0, 1,2, …) is based on the bandpass sampling principle：
In the middle of、/>Respectively the sampling sequence/>In-phase and quadrature components of (a), namely:
For sampling sequences Parity extraction is performed to obtain:
The digital spectrum is as follows:
Wherein, Representing a temporal envelope sampling sequence,/>Representing the sampling sequence number,/>Representing the instantaneous initial phase of the received signal,/>Representing an I-way even sequence,/>Representing Q-way odd sequence,/>Representing an even sequence of the sample sequence,Representing the odd sequence of the sampling sequence,/>Representing digital spectrum coordinates,/>Representing the digital spectrum of the even sequence of the I path,Representing Q-way odd sequence number spectrum,/>Representing the frequency.
Further, in the second step, after the sampling sequence is odd-even decimated, a 2-times decimated sequence of the in-phase component and the quadrature component of the sampling sequence is obtained, the 2 components differ in frequency domain by a delay factor, the delay is corrected by adopting two delay filters, and the frequency response of the two delay filters needs to satisfy:
Wherein the method comprises the steps of 、/>The frequency response of the in-phase component and quadrature component filters respectively; through the process of、/>And filtering to obtain the IQ orthogonal signals with the same delay factors, thereby realizing alignment.
Further, in step three, the baseband data after quadrature demodulation is compressed, the compression algorithm uses BAQ compression, echo data is calculated into blocks 32×32 according to azimuth distance, and the compressed data becomes half of the original data.
The invention provides an electronic device, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the pulse radar baseband signal acquisition processing method when executing the computer program.
The invention provides a computer readable storage medium for storing computer instructions which when executed by a processor implement the pulse radar baseband signal acquisition processing method.
Compared with the prior art, the invention has the following advantages:
1. The invention provides a pulse radar baseband signal acquisition processing method for SAR imaging, which has a function of transmitting linear frequency modulation pulse signals, and the parameters of the transmitted signals can be flexibly configured by upper computer software. The method also has the functions of echo signal acquisition, demodulation and compression processing, and the data is stored in an upper computer through a high-speed transmission interface and is provided for subsequent image processing.
2. The invention relates to a baseband signal processing method for realizing high-speed acquisition and storage of a receiving link of a real-time configurable parameter of a transmitting link.
3. According to the invention, the parallel per-branch signal parameters are deduced through the DDS and parallel-serial conversion principle, the calculation formula is simplified, 5 key parameters are obtained, the five parameters can be calculated in real time only through addition to obtain the phase corresponding to the target waveform, the occupied resources in the FPGA are small, and the time sequence is easy to ensure. The key parameters can be flexibly configured in real time by an upper computer through a protocol PCIe channel, and the waveform is rapidly switched in real time by updating the signal pulse gap.
4. The invention uses the multiphase filtering method, the filter coefficient is 1/4 of the prototype filter, the data rate is 1/2 of the original rate, the rapid orthogonal demodulation is realized, the calculated amount is small, and the time sequence is easy to satisfy. For echo data of large data volume, 8:4 BAQ, further reducing the data transmission pressure. The baseband hardware in the invention is an FPGA development board. And the PCIe protocol is adopted for data transmission, so that the high-speed transmission of the data is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a functional block diagram of a transmit chain.
Fig. 2 is a receive link flow diagram.
Fig. 3 is a flow chart of polyphase filtering.
FIG. 4 is a graph of flatness results in the 450-750 MHz chirp band.
Fig. 5 is a schematic diagram of the result of the actual measurement, acquisition and processing of the FPGA by the polyphase filtering method.
Fig. 6 is a comparative diagram of BAQ compression results.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
1-6, The invention provides a pulse radar baseband signal acquisition processing method, which comprises a transmitting link part and a receiving link part;
As shown in fig. 1, the transmitting link part comprises an upper computer and an FPGA; the upper computer is communicated with the FPGA through a PCIe protocol, converts the waveform index into a waveform to generate a required parameter, and transmits the waveform index and the waveform switch control parameter to the FPGA, and the FPGA generates a digital waveform and emits a target waveform through a DAC of a daughter board in the FPGA; the flow realizes flexible control of waveforms; the transmitting link generates a linear frequency modulation wave signal, parameters of the signal are configured to an FPGA end by upper computer software, and the FPGA end generates corresponding waveforms and sends the waveforms to the sub-board DAC for output. The waveform generation employs Direct Digital Synthesis (DDS) techniques. The DDS is known as DIRECT DIGITAL Synthesizer (direct digital synthesis), which is a technology for generating waveforms directly by adopting digital technology from the phase, mapping the phase quantity of the pre-stored waveforms into amplitude measurement by an address table look-up mode and synthesizing the amplitude measurement into an output signal.
Because AD9739 uses dual-port DB0, DB1 to transmit data at the same time, the data parity is staggered, so that the transmission rate of each path of data at the FPGA end can be reduced to 1/2 of the chip clock, the accuracy of data transmission can be improved, and two paths of data can be recombined into one path in the chip. The chip interface collects data in DDR mode, i.e. the data are collected on both rising edge and falling edge of the data clock, so that the serial data clock of the FPGA is 1/4 of the chip clock, i.e. 1/2 of the data transmission rate. Therefore, the working clock of the FPGA can be reduced, and the clock quality is improved.
The DAC sampling rate is 2.4GHz, the FPGA end adopts 8 paths of parallel data to be converted into two paths of odd-even serial data, the DDS working frequency is 300MHz, namely a parallel clock of parallel-serial conversion, and the serial clock is 1/4 of a chip clock, namely 2.4 GHz/4=600 MHz. The two parallel to serial converters OSERDES operate at 4:1 and in DDR (double edge sampling) mode, the parallel clock (CLK DIV) is a divide-by-2 of the serial Clock (CLK). Each channel signal is implemented using a DDS core and the data differential output is sent to the AD9739.
As shown in fig. 2, the receiving link part collects echo signals through bandpass sampling, the signals are subjected to quadrature demodulation to obtain baseband data, the baseband data is reduced in data size through a compression algorithm, the compressed data is transmitted to the upper computer through a high-speed data channel, transmission enabling is controlled by the upper computer, and the upper computer stores the received compressed baseband data into a binary file for subsequent imaging processing.
The implementation method of the transmitting link part specifically comprises the following steps:
Step 1: calculating waveform parameters; the direct digital synthesis technology DDS principle, the linear frequency modulation wave and the parallel-serial conversion principle are used for obtaining a calculation formula of an 8-path DDS input real-time phase value, so that the total is simplified into 5 control parameters, and the control parameters can be transmitted to a lower computer from an upper computer; the upper computer calculates 5 control parameters according to the signal parameters, the 5 control parameters are transmitted to the lower computer through the PCIe transmission channel, and the parameters are updated to the lower computer when the parameters are changed, so that the waveform real-time control is realized;
According to DDS waveform generation principle and linear frequency modulation wave, calculating 8-channel initial phase code words and phase increment code words, wherein the 8-channel initial phase code words correspond to the first 8 bits of final serial data, namely:
Where j is the channel number and is the number of channels, For the phase increment of the jth path, the variation over time,/>Representing the starting frequency of the chirp signal,/>Representing the sampling frequency, N representing the DDS phase accumulator data bit width, k representing the chirp frequency modulation factor.
The initial phase code word and the phase increment code word are calculated and simplified into 5 control parameters by an upper computer、/>、/>、、/>Transmitting to FPGA;
Under the condition of waveform determination, the 5 control parameters are not changed, and the FPGA only carries out superposition calculation on the phase increment code word at any time; the parameter formula is as follows:
Wherein, Representing the phase increment of the ith data of the jth channel,/>The ith data representing the current channel.
It can be seen that this calculation is applicable to the calculation of any waveform parameter. Through communication with the FPGA, the target waveform can be updated by changing the parameters, so that the calculation is concise, and the operation flexibility is strong.
Step 2: the lower computer transmits 5 control parameters of the waveform to the FPGA end through a parameter channel of protocol PCIe communication, calculates 8 paths of parallel DDS real-time phases according to the control parameters, outputs 8 paths of signals according to the parallel DDS, and simultaneously controls waveform output according to pulse duration and pulse interval time;
Step 3: the parallel signals are converted into serial high-speed signals through parallel-serial conversion, and the DAC converts the signals into analog signals according to configuration and transmits the analog signals out, so that the generation of the high-speed broadband signals is realized.
The receiving link part implementation method specifically comprises the following steps:
Step one: band-pass sampling, namely determining sampling frequency according to a band-pass sampling principle, and odd-even extracting a sampling sequence;
step two: polyphase filtering quadrature demodulation;
step three: BAQ 8:4 compression;
Step four: and uploading the data to an upper computer, framing the compressed data according to a protocol format, uploading the data to the upper computer through a PCIe high-speed channel when the upper computer requests the data, and storing the data as a binary file by the upper computer.
In step one, a sampling sequence is obtained when the sampling frequency f s= 4f0/(2m+1) (variable m=0, 1,2, …) is based on the sampling principle：
In the middle of、/>Respectively the sampling sequence/>In-phase and quadrature components of (a), namely:
For sampling sequences Parity extraction is performed to obtain:
The digital spectrum is as follows:
Wherein, Representing a temporal envelope sampling sequence,/>Representing the sampling sequence number,/>Representing the instantaneous initial phase of the received signal,/>Representing an I-way even sequence,/>Representing Q-way odd sequence,/>Representing an even sequence of the sample sequence,Representing the odd sequence of the sampling sequence,/>Representing digital spectrum coordinates,/>Representing the digital spectrum of the even sequence of the I path,Representing Q-way odd sequence number spectrum,/>Representing the frequency.
In the second step, after odd and even extraction, the original sequence is extracted to obtain 2 times of the extraction sequence of the in-phase component and the quadrature component of the original sequence, and the 2 components are different by a delay factor in the frequency domain and are equivalent to a half sampling point in the time domain. The delay of the half sample points is caused by odd and even extraction, and the 'misalignment' in time can be corrected by two delay filters, and the frequency response of the two delay filters needs to meet the following requirements:
Wherein the method comprises the steps of 、/>The frequency response of the in-phase component and quadrature component filters respectively; through the process of、/>And filtering to obtain the IQ orthogonal signals with the same delay factors, thereby realizing alignment. The polyphase filtering flow chart is shown in fig. 3.
Compared with the traditional low-pass filtering method, the multiphase filtering method firstly extracts the sampled data, and the data rate is reduced by 1/2 before filtering. The polyphase filtering method selects 2 out of 4 branch filters of the prototype filter, and the order is 1/4 of the prototype filter. The data calculation amount and the resources are greatly reduced.
The branching filter is obtained according to the polyphase filtering principle. The branch number D is selected to be 4, and two groups of branch filter combinations with time delay difference of 1/2 can be obtained:
Wherein, Representing the frequency response of the Q-way filter of group 1,/>Representing the group 1I filter frequency response,/>Representing the branching filter 0,/>Representing the branching filter 2,/>Representing the 2 nd set of Q-way filter frequency responses,/>Representing the group 2I filter frequency response,/>Representing the branching filter 1,/>A branching filter 3 is shown.
The filter design uses an FIR filter, firstly, the order and the calculation coefficient are determined, the filter coefficient is calculated by using a tool, the filter order and the design method are preset as required, the prototype filter coefficient is quantized and then is exported, the coefficients are divided into 4 groups, the branch filter coefficient can be obtained, and the 4 groups of coefficients respectively represent 4 branch filters. And according to a set of calculated coefficients, the coefficients are quantized, rounded and directly referenced.
In the third step, the baseband data after quadrature demodulation is compressed, the compression algorithm uses BAQ compression, echo data is calculated into blocks 32×32 according to azimuth distance, and the amount of data after compression becomes half of the original amount.
FIG. 4 is a schematic diagram of flatness in a 450-750MHz chirped band, wherein the FPGA working clock is 300MHz, the D/A sampling rate is 2.4GHz, the target output frequency is 450MHz-750MHz, and the flatness in the band is within 2 dB. Fig. 5 is a schematic diagram of the result of actual measurement, acquisition and processing of the FPGA by the polyphase filtering method, where the polyphase filtering method recovers the acquired data into baseband data. Fig. 6 is a schematic diagram showing comparison of the results of BAQ compression processing, in which the FPGA implementation data and matlab algorithm simulation data are completely identical.
The invention provides an electronic device, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the pulse radar baseband signal acquisition processing method when executing the computer program.
The invention provides a computer readable storage medium for storing computer instructions which when executed by a processor implement the pulse radar baseband signal acquisition processing method.
The memory in embodiments of the present application may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a Read Only Memory (ROM), a Programmable ROM (PROM), an erasable programmable ROM (erasable PROM), an electrically erasable programmable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (STATIC RAM, SRAM), dynamic random access memory (DYNAMIC RAM, DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (double DATA RATE SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCHLINK DRAM, SLDRAM), and direct memory bus random access memory (direct rambus RAM, DR RAM). It should be noted that the memory of the methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a high-density digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a solid-state disk (solid-state drive STATE DISC, SSD)), or the like.
In implementation, each step of the method may be implemented by an integrated logic circuit of hardware in a processor or an instruction in a form of a software component. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method. To avoid repetition, a detailed description is not provided herein.
It should be noted that the processor in the embodiments of the present application may be an integrated circuit chip with signal processing capability. In implementation, the steps of the above method embodiments may be implemented by integrated logic circuits of hardware in a processor or instructions in software form. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, or discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.
The above detailed description of the method, the device and the medium for acquiring and processing the baseband signal of the pulse radar is provided, and specific examples are applied to the description of the principle and the implementation mode of the invention, and the description of the above examples is only used for helping to understand the method and the core idea of the invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (7)
1. A pulse radar baseband signal acquisition processing method, characterized in that the method comprises a transmitting link part and a receiving link part;
The transmitting link part comprises an upper computer and an FPGA; the upper computer is communicated with the FPGA through a PCIe protocol, converts the waveform index into a waveform to generate a required parameter, and transmits the waveform index and the waveform switch control parameter to the FPGA, and the FPGA generates a digital waveform and emits a target waveform through a DAC of a daughter board in the FPGA;
The receiving link part acquires echo signals through band-pass sampling, the signals are subjected to quadrature demodulation to obtain baseband data, the baseband data reduce the data size through a compression algorithm, the compressed data are transmitted to the upper computer through a high-speed data channel, transmission enabling is controlled by the upper computer, and the upper computer stores the received compressed baseband data into a binary file for subsequent imaging processing;
the implementation method of the transmitting link part specifically comprises the following steps:
Step 1: calculating waveform parameters; the direct digital synthesis technology DDS principle, the linear frequency modulation wave and the parallel-serial conversion principle are used for obtaining a calculation formula of an 8-path DDS input real-time phase value, so that the total is simplified into 5 control parameters, and the control parameters can be transmitted to a lower computer from an upper computer; the upper computer calculates 5 control parameters according to the signal parameters, the 5 control parameters are transmitted to the lower computer through the PCIe transmission channel, and the parameters are updated to the lower computer when the parameters are changed, so that the waveform real-time control is realized;
step 2: the lower computer transmits 5 control parameters of the waveform to the FPGA end through a parameter channel of PCIe communication, calculates 8 paths of parallel DDS real-time phases according to the control parameters, outputs 8 paths of signals according to the parallel DDS, and simultaneously controls the waveform output according to the pulse duration and the pulse interval time;
Step 3: the parallel signals are converted into serial high-speed signals through parallel-serial conversion, and the DAC converts the signals into analog signals according to configuration and transmits the analog signals out, so that the generation of high-speed broadband signals is realized;
According to DDS waveform generation principle and linear frequency modulation wave, calculating 8-channel initial phase code words and phase increment code words, wherein the 8-channel initial phase code words correspond to the first 8 bits of final serial data, namely:
Where j is the channel number and is the number of channels, For the variation of the phase increment of the jth path along with time, f 0 represents the initial frequency of the chirp signal, f s represents the sampling frequency, N represents the data bit width of the DDS phase accumulator, and k represents the frequency modulation coefficient of the chirp signal;
The initial phase code word and the phase increment code word are calculated and simplified into 5 control parameters by an upper computer Transmitting to FPGA;
Under the condition of waveform determination, the 5 control parameters are not changed, and the FPGA only carries out superposition calculation on the phase increment code word at any time; the parameter formula is as follows:
Wherein, Represents the phase increment of the ith data of the jth channel, i represents the ith data of the current channel.
2. The method for acquiring and processing the baseband signal of the pulse radar according to claim 1, wherein the method for implementing the receiving link part specifically comprises the following steps:
Step one: band-pass sampling, namely determining sampling frequency according to a band-pass sampling principle, and odd-even extracting a sampling sequence;
step two: polyphase filtering quadrature demodulation;
step three: BAQ 8:4 compression;
Step four: and uploading the data to an upper computer, framing the compressed data according to a protocol format, uploading the data to the upper computer through a PCIe high-speed channel when the upper computer requests the data, and storing the data as a binary file by the upper computer.
3. The method according to claim 2, wherein in step one, according to the bandpass sampling principle, when the sampling frequency f s＝4f0/(2m+1), the variable m=0, 1,2, …, a sampling sequence x (n) is obtained:
where x I(n)、xQ (n) is the in-phase and quadrature components of the sample sequence x (n), respectively, i.e.:
parity extraction is performed on the sample sequence x (n), and can be obtained:
The digital spectrum is as follows:
Where a (n) represents the instantaneous envelope sample sequence, n represents the sample sequence number, Representing the instantaneous initial phase of the received signal, X I (2 n) representing the I-way even sequence, X Q (2n+1) representing the Q-way odd sequence, X (2 n) representing the even sequence of the sample sequence, X (2n+1) representing the odd sequence of the sample sequence, e jω representing the digital spectrum coordinates, X I(ejω/2) representing the I-way even sequence digital spectrum, X Q(ejω/2)ejω/2 representing the Q-way odd sequence digital spectrum, ω representing the frequency.
4. The method for acquiring and processing the baseband signal of the pulse radar according to claim 3, wherein in the second step, after the sampling sequence is odd-even decimated, a 2-time decimated sequence of an in-phase component and a quadrature component of the sampling sequence is obtained, the 2 components differ in frequency domain by a delay factor, the delay is corrected by two delay filters, and frequency responses of the two delay filters need to satisfy:
Wherein H I(ejω)、HQ(ejω) is the frequency response of the in-phase component, quadrature component filters, respectively; through H I(ejω)、HQ(ej ω) filtering, IQ orthogonal signals with the same delay factors can be obtained, and alignment is realized.
5. The method of claim 4, wherein in step three, the quadrature-demodulated baseband data is compressed, the compression algorithm uses BAQ compression, echo data is calculated by dividing the echo data into blocks 32×32 according to the azimuth distance, and the amount of the compressed data becomes half of the original amount.
6. An electronic device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor implements a pulsed radar baseband signal acquisition processing method according to any one of claims 1-5 when executing the computer program.
7. A computer readable storage medium storing computer instructions which, when executed by a processor, implement a pulsed radar baseband signal acquisition processing method according to any one of claims 1-5.
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