JPH09135274A - Fading simulator for digital communication - Google Patents

Fading simulator for digital communication

Info

Publication number
JPH09135274A
JPH09135274A JP7311689A JP31168995A JPH09135274A JP H09135274 A JPH09135274 A JP H09135274A JP 7311689 A JP7311689 A JP 7311689A JP 31168995 A JP31168995 A JP 31168995A JP H09135274 A JPH09135274 A JP H09135274A
Authority
JP
Japan
Prior art keywords
signal
modulation
output
noise
fading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7311689A
Other languages
Japanese (ja)
Other versions
JP3557020B2 (en
Inventor
Osamu Watanabe
修 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Original Assignee
Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd filed Critical Japan Radio Co Ltd
Priority to JP31168995A priority Critical patent/JP3557020B2/en
Publication of JPH09135274A publication Critical patent/JPH09135274A/en
Application granted granted Critical
Publication of JP3557020B2 publication Critical patent/JP3557020B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

PROBLEM TO BE SOLVED: To attain miniaturization and low cost by adding a noise for fading to a base band modulation signal for balanced modulation so as to use only one standard orthogonal modulator enough from modulation of carrier till addition of the fading. SOLUTION: An IQ signal generating circuit 2 generates signals I, Q based on a prescribed bit pattern of a digital signal generated by a pattern generator 1. The signals I, Q are base band modulation signals to apply balance modulation to carriers with phase of 0, 90 deg. of the orthogonal modulation system and added to outputs of 1st and 2nd noise generating circuits 41, 42 at 1st and 2nd adders 43, 44 and the result is given to a standard orthogonal modulator 45. A signal generator 3 gives a carrier signal with an intermediate frequency corresponding to an input frequency of a device 5 to be evaluated being an object of evaluation, in which the modulation signals are modulated by the carrier with balanced modulation and the result is given to the device 9 to be evaluated. Thus, only one standard orthogonal modulator conducts from modulation of a carrier till addition of fading, then miniaturization and low cost are attained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、ディジタル通信装
置の性能評価を行うためのシミュレータに関し、特に直
交変調方式を使用するディジタル通信装置における耐フ
ェージング(fading)性能を評価するためのディジタル通
信用フェージングシミュレータに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulator for evaluating the performance of a digital communication device, and more particularly to a fading for digital communication for evaluating the fading resistance performance of a digital communication device using a quadrature modulation method. It is about simulators.

【0002】[0002]

【従来の技術】フェージングとは通信装置の受信アンテ
ナに誘起される無線周波数電圧の時間的変化を言うが、
この種のシミュレータでは無線周波数電圧の時間的変化
を発生させるよりも、信号対雑音比(以下S/N比とい
う)の時間的変化を発生させる方が容易であるので、S
/N比の時間的変化を用いて等価的なフェージングを生
じさせる構成となっている。すなわち、無線通信装置の
受信機には、中間周波数増幅器にAGC(自動利得制
御)が備えられていて、弱い入力に対しては増幅度を上
げ、強い入力に対しては増幅度を下げ、復調器の入力点
ではほぼ一定の振幅になるように制御されている。従っ
て増幅度が上がると雑音が大きくなり、増幅度が下がる
と雑音が小さくなることになるので、逆に、信号に大き
な雑音を付加するとフェージングのために入力信号が小
さくなったことと等価になり、信号に小さな雑音を加え
ると(または全然雑音を加えないと)フェージングが少
なく、あるいは無くなった入力信号と等価になる。
2. Description of the Related Art Fading refers to a change over time in a radio frequency voltage induced in a receiving antenna of a communication device.
In this type of simulator, it is easier to generate a temporal change in the signal-to-noise ratio (hereinafter referred to as S / N ratio) than to generate a temporal change in the radio frequency voltage.
It is configured to generate equivalent fading by using the temporal change of the / N ratio. That is, the receiver of the wireless communication device is equipped with an AGC (automatic gain control) in the intermediate frequency amplifier, which increases the amplification degree for weak inputs and decreases the amplification degree for strong inputs. At the input point of the vessel, the amplitude is controlled to be almost constant. Therefore, if the amplification level increases, the noise increases, and if the amplification level decreases, the noise decreases.Conversely, adding large noise to the signal is equivalent to reducing the input signal due to fading. , Add little noise to a signal (or add no noise at all) to reduce fading or be equivalent to a lost input signal.

【0003】図2は、従来のこの種のシミュレータの構
成の一例を示すブロック図で、1はディジタル信号の所
定のビットパターンを発生するパターン発生器、2はパ
ターン発生器1で発生するビットパターンに基づき、信
号I、信号Qを発生するIQ信号発生回路、3は評価の
対象となる被評価器5の入力周波数に対応する無線周波
数又は中間周波数の搬送波信号を発生させる信号発生器
である。ここで信号発生器3で発生させる信号の角周波
数をωとする。信号Iは、信号発生器3で発生させた0
度位相の搬送波を平衡変調して、Isin ωtの信号を発
生させるためのベースバンドの信号であり、信号Qは信
号発生器3で発生させた90度位相の搬送波を平衡変調
して、Qcos ωtの信号を発生させるためのベースバン
ドの信号であり、6はこのような変調を行う標準直交変
調器である。すなわちS/N比で言えば標準直交変調器
6の出力は信号Sとなる。
FIG. 2 is a block diagram showing an example of the structure of a conventional simulator of this type. Reference numeral 1 is a pattern generator for generating a predetermined bit pattern of a digital signal, and 2 is a bit pattern for the pattern generator 1. Based on the above, the IQ signal generating circuit 3 for generating the signals I and Q is a signal generator for generating a carrier wave signal of a radio frequency or an intermediate frequency corresponding to the input frequency of the device to be evaluated 5 to be evaluated. Here, the angular frequency of the signal generated by the signal generator 3 is ω. The signal I is 0 generated by the signal generator 3.
Is a baseband signal for generating a signal of Isin ωt by balance-modulating a carrier having a phase of 90 degrees. 6 is a standard quadrature modulator for performing such modulation. That is, in terms of S / N ratio, the output of the standard quadrature modulator 6 becomes the signal S.

【0004】図2に示す従来の装置では、標準直交変調
器6の出力である信号Sと同じ形で雑音Nを加える構成
となっている。すなわち、41は第1の雑音(ディジタ
ル)発生回路、42は第2の雑音(ディジタル)発生回
路であり、7は標準直交変調器6と同様な標準直交変調
器で、信号発生器3の出力の0度位相の搬送波を、雑音
発生回路41の出力で平衡変調し、信号発生器3の出力
の90度位相の搬送波を、雑音発生回路42の出力で平
衡変調する。標準直交変調器7の出力がN(雑音)で、
このようにして得られたS/N比の信号が被評価器5に
入力される。パターン発生器1で発生するビットパター
ンは予め定められているので、被評価器5の出力からビ
ット誤り率を測定することができ、例えば雑音発生回路
41、42の出力を漸次増加して、どのようなS/N比
のとき(すなわち、どのようなフェージングのとき)ど
のようなビット誤り率になるかを測定することができ
る。また実際に発生するフェージングの時間的変化をシ
ミュレートするような出力変化を雑音発生回路41、4
2の出力に与えることも容易である。
In the conventional apparatus shown in FIG. 2, noise N is added in the same form as the signal S which is the output of the standard quadrature modulator 6. That is, 41 is a first noise (digital) generation circuit, 42 is a second noise (digital) generation circuit, 7 is a standard quadrature modulator similar to the standard quadrature modulator 6, and the output of the signal generator 3 The 0 ° phase carrier wave is balanced-modulated by the output of the noise generation circuit 41, and the 90 ° phase carrier wave output of the signal generator 3 is balanced-modulated by the noise generation circuit 42 output. The output of the standard quadrature modulator 7 is N (noise),
The signal of the S / N ratio thus obtained is input to the device under evaluation 5. Since the bit pattern generated by the pattern generator 1 is predetermined, the bit error rate can be measured from the output of the device under evaluation 5, and the output of the noise generating circuits 41, 42 is gradually increased to It is possible to measure what kind of bit error rate the S / N ratio has (that is, what kind of fading). In addition, the noise generation circuits 41 and 4 generate output changes that simulate temporal changes in fading that actually occur.
It is easy to give to the output of 2.

【0005】[0005]

【発明が解決しようとする課題】従来のディジタル通信
用フェージングシミュレータは以上のように構成されて
いるので標準直交変調器が2台必要になり、装置の小型
化,低価格化を妨げているという問題点があった。
Since the conventional fading simulator for digital communication is constructed as described above, two standard quadrature modulators are required, which hinders downsizing and cost reduction of the device. There was a problem.

【0006】本発明はかかる問題点を解決するためにな
されたものであり、従来の装置と同等の機能を持つディ
ジタル通信用フェージングシミュレータを標準直交変調
器1台の回路で構成することを目的としている。
The present invention has been made to solve the above problems, and an object of the present invention is to construct a fading simulator for digital communication having a function equivalent to that of a conventional device by a circuit of one standard quadrature modulator. There is.

【0007】[0007]

【課題を解決するための手段】本発明に係わるディジタ
ル通信用フェージングシミュレータは、ベースバンド信
号にフェージング用の雑音を付加し、これを標準直交変
調器の変調信号として入力する構成とした。
A fading simulator for digital communication according to the present invention has a structure in which noise for fading is added to a baseband signal and this is input as a modulation signal of a standard quadrature modulator.

【0008】具体的には、直交変調方式の0度位相の搬
送波を平衡変調するためのベースバンドの変調信号I
と、第1の雑音発生回路の出力とを加算する第1の加算
器、直交変調方式の90度位相の上記搬送波を平衡変調
するためのベースバンドの変調信号Qと、第2の雑音発
生回路の出力とを加算する第2の加算器、信号発生器の
出力の0度位相の搬送波を上記第1の加算器の出力で平
衡変調し、上記信号発生器の出力の90度位相の搬送波
を上記第2の加算器の出力で平衡変調する標準直交変調
器を備えたことを特徴とする。
Specifically, a baseband modulation signal I for balance-modulating a carrier of a 0 ° phase of a quadrature modulation system
And a first adder for adding the output of the first noise generating circuit, a baseband modulation signal Q for balance-modulating the carrier of 90 ° phase of a quadrature modulation method, and a second noise generating circuit And a carrier of 0 degree phase of the output of the signal generator is balanced-modulated by the output of the first adder, and a carrier of 90 degree phase of the output of the signal generator is added. A standard quadrature modulator that performs balanced modulation with the output of the second adder is provided.

【0009】また上記変調信号Iと変調信号Qとは、所
定のビットパターンを発生するパターン発生器の出力を
入力し、この入力を信号Iと信号Qとに変換して出力す
るIQ信号発生回路から入力される構成を特徴とする。
さらに上記第1の雑音発生回路と第2の雑音発生回路で
発生させる雑音出力は、予め定められたプログラムに従
い時間的に変化させる構成を特徴とする。
The modulated signal I and the modulated signal Q are input to the output of a pattern generator that generates a predetermined bit pattern, and the input is converted into the signal I and the signal Q and output. It is characterized by the configuration input from.
Further, the noise output generated by the first noise generating circuit and the second noise generating circuit is characterized by changing with time according to a predetermined program.

【0010】[0010]

【発明の実施の形態】以下、本発明の実施形態を図面を
用いて説明する。図1は、本発明の一実施形態を説明す
るための図であり、図において、1はディジタル信号の
所定のビットパターンを発生するパターン発生器、2は
パターン発生器1で発生するビットパターンに基づき、
信号I、信号Qを発生するIQ信号発生回路、3は評価
の対象となる被評価器5の入力周波数に対応する無線周
波数又は中間周波数の搬送波信号を発生させる信号発生
器である。ここで信号発生器3で発生させる信号の角周
波数をωとする。信号Iは、信号発生器3で発生させた
0度位相の搬送波を平衡変調して、Isin ωtの信号を
発生させるためのベースバンドの信号であり、信号Qは
信号発生器3で発生させた90度位相の搬送波を平衡変
調して、Qcos ωtの信号を発生させるためのベースバ
ンドの信号である。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram for explaining one embodiment of the present invention, in which 1 is a pattern generator for generating a predetermined bit pattern of a digital signal, and 2 is a bit pattern generated by the pattern generator 1. Based on
The IQ signal generating circuit 3 for generating the signals I and Q is a signal generator for generating a carrier signal of a radio frequency or an intermediate frequency corresponding to the input frequency of the device to be evaluated 5 to be evaluated. Here, the angular frequency of the signal generated by the signal generator 3 is ω. The signal I is a baseband signal for balanced-modulating the carrier of 0 degree phase generated by the signal generator 3 to generate a signal of Isin ωt, and the signal Q is generated by the signal generator 3. It is a baseband signal for generating a Qcos ωt signal by balance-modulating a 90 ° phase carrier.

【0011】4は本実施形態におけるフェージングシミ
ュレータであり、41は第1の雑音発生回路、42は第
2の雑音発生回路、43は第1の加算器、44は第2の
加算器、45は標準直交変調器、46は高周波入力端
子、47は高周波出力端子、48,49ははベースバン
ド信号出力端子である。また5は被評価器である。
Reference numeral 4 is a fading simulator in the present embodiment, 41 is a first noise generating circuit, 42 is a second noise generating circuit, 43 is a first adder, 44 is a second adder, and 45 is Standard quadrature modulator, 46 is a high frequency input terminal, 47 is a high frequency output terminal, and 48 and 49 are baseband signal output terminals. Reference numeral 5 is a device to be evaluated.

【0012】図1に示すように本実施形態のフェージン
グシミュレータは、ベースバンド信号にフェージングの
ための雑音を付加する構成とすることで、搬送波の変調
からフェージング付加までを標準直交変調器1台の回路
で構成することができるようになる。なお、第1の雑音
発生回路41と第2の雑音発生回路42とは、図示して
ないが、予め定められたプログラムに従い発生させる雑
音が時間的に変化する構成とすることにより、より適切
にフェージング状態をシミュレートできる構成とするこ
とが可能となる。
As shown in FIG. 1, the fading simulator according to the present embodiment has a configuration in which noise for fading is added to a baseband signal so that a standard quadrature modulator can be used for everything from modulation of a carrier to addition of fading. It can be configured with a circuit. Although not shown, the first noise generation circuit 41 and the second noise generation circuit 42 are more appropriately configured by a configuration in which noise generated according to a predetermined program changes with time. It is possible to have a configuration that can simulate a fading state.

【0013】[0013]

【発明の効果】本発明のディジタル通信用フェージング
シミュレータは以上説明したように、ベースバンド信号
にフェージングのための雑音を付加する構成とすること
で、搬送波の変調からフェージング付加までを標準直交
変調器1台の回路で構成することができ、装置の小型
化,低価格化が図れるという効果がある。
As described above, the fading simulator for digital communication according to the present invention has a configuration in which noise for fading is added to the baseband signal, so that the standard quadrature modulator performs from the modulation of the carrier wave to the addition of fading. Since it can be configured with one circuit, there is an effect that the device can be downsized and the cost can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

【図2】従来のこの種のフェージングシミュレータを示
すブロック図である。
FIG. 2 is a block diagram showing a conventional fading simulator of this type.

【符号の説明】[Explanation of symbols]

1 パターン発生器 2 IQ信号発生回路 3 信号発生器 4 フェージングシミュレータ 5 被評価器 41 第1の雑音発生回路 42 第2の雑音発生回路 43 第1の加算器 44 第2の加算器 45 標準直交変調器 46 高周波入力端子 47 高周波出力端子 48,49 ベースバンド信号出力端子 1 Pattern Generator 2 IQ Signal Generation Circuit 3 Signal Generator 4 Fading Simulator 5 Evaluator 41 First Noise Generation Circuit 42 Second Noise Generation Circuit 43 First Adder 44 Second Adder 45 Standard Quadrature Modulation Instrument 46 High frequency input terminal 47 High frequency output terminal 48,49 Baseband signal output terminal

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 直交変調方式の0度位相の搬送波を平衡
変調するためのベースバンドの変調信号Iと、第1の雑
音発生回路の出力とを加算する第1の加算器、 直交変調方式の90度位相の上記搬送波を平衡変調する
ためのベースバンドの変調信号Qと、第2の雑音発生回
路の出力とを加算する第2の加算器、 信号発生器の出力の0度位相の搬送波を上記第1の加算
器の出力で平衡変調し、上記信号発生器の出力の90度
位相の搬送波を上記第2の加算器の出力で平衡変調する
標準直交変調器を備えたことを特徴とするディジタル通
信用フェージングシミュレータ。
1. A first adder for adding a baseband modulation signal I for balanced modulation of a 0 ° phase carrier of a quadrature modulation system and an output of a first noise generation circuit, and a quadrature modulation system A second adder for adding the baseband modulation signal Q for the balanced modulation of the 90 ° phase carrier and the output of the second noise generation circuit, and the 0 ° phase carrier of the output of the signal generator. A standard quadrature modulator that balance-modulates with the output of the first adder and balance-modulates a 90-degree phase carrier of the output of the signal generator with the output of the second adder is provided. Fading simulator for digital communication.
【請求項2】 上記変調信号Iと変調信号Qとは、所定
のビットパターンを発生するパターン発生器の出力を入
力し、この入力を信号Iと信号Qとに変換して出力する
IQ信号発生回路から入力される構成を特徴とする請求
項第1項記載のディジタル通信用フェージングシミュレ
ータ。
2. The modulated signal I and the modulated signal Q are input to the output of a pattern generator that generates a predetermined bit pattern, and the input is converted into the signal I and the signal Q to output the IQ signal. The fading simulator for digital communication according to claim 1, wherein the fading simulator is configured to be inputted from a circuit.
【請求項3】 上記第1の雑音発生回路と第2の雑音発
生回路で発生させる雑音出力は、予め定められたプログ
ラムに従い時間的に変化させる構成を特徴とする請求項
第1項または第2項記載のディジタル通信用フェージン
グシミュレータ。
3. The noise output generated by the first noise generating circuit and the second noise generating circuit is temporally changed according to a predetermined program, according to claim 1 or 2. A fading simulator for digital communication according to the item.
JP31168995A 1995-11-07 1995-11-07 Fading simulator for digital communication Expired - Fee Related JP3557020B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31168995A JP3557020B2 (en) 1995-11-07 1995-11-07 Fading simulator for digital communication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31168995A JP3557020B2 (en) 1995-11-07 1995-11-07 Fading simulator for digital communication

Publications (2)

Publication Number Publication Date
JPH09135274A true JPH09135274A (en) 1997-05-20
JP3557020B2 JP3557020B2 (en) 2004-08-25

Family

ID=18020287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31168995A Expired - Fee Related JP3557020B2 (en) 1995-11-07 1995-11-07 Fading simulator for digital communication

Country Status (1)

Country Link
JP (1) JP3557020B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000028709A1 (en) * 1998-11-11 2000-05-18 Kabushiki Kaisha Kenwood Dummy error addition circuit
WO2004107695A1 (en) * 2003-05-27 2004-12-09 Nec Corporation Data communication device selecting modulation method with an appropriate threshold value in adaptive modulation
JP2009044746A (en) * 2008-09-03 2009-02-26 Yokogawa Electric Corp Test signal generating apparatus
CN106843310A (en) * 2017-03-20 2017-06-13 南京师范大学 A kind of 0 DEG C of signal generator and its implementation

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000028709A1 (en) * 1998-11-11 2000-05-18 Kabushiki Kaisha Kenwood Dummy error addition circuit
US6772378B1 (en) 1998-11-11 2004-08-03 Kabushiki Kaisha Kenwood Dummy error addition circuit
WO2004107695A1 (en) * 2003-05-27 2004-12-09 Nec Corporation Data communication device selecting modulation method with an appropriate threshold value in adaptive modulation
GB2413250A (en) * 2003-05-27 2005-10-19 Nec Corp Data communication device selecting modulation method with an appropriate threshold value in adaptive modulation
JPWO2004107695A1 (en) * 2003-05-27 2006-07-20 日本電気株式会社 Data communication apparatus for selecting modulation scheme with appropriate threshold in adaptive modulation
GB2413250B (en) * 2003-05-27 2008-04-16 Nec Corp Data communication device selecting modulation method with an appropriate threshold value in adaptive modulation
US7447145B2 (en) 2003-05-27 2008-11-04 Nec Corporation Data communication device selecting modulation method with an appropriate threshold value in adaptive modulation
JP4506979B2 (en) * 2003-05-27 2010-07-21 日本電気株式会社 Data communication apparatus for selecting modulation scheme with appropriate threshold in adaptive modulation
JP2009044746A (en) * 2008-09-03 2009-02-26 Yokogawa Electric Corp Test signal generating apparatus
CN106843310A (en) * 2017-03-20 2017-06-13 南京师范大学 A kind of 0 DEG C of signal generator and its implementation

Also Published As

Publication number Publication date
JP3557020B2 (en) 2004-08-25

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