JP3064979B2 - Dicing method for semiconductor wafer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of dicing a semiconductor wafer in a semiconductor device in which a semiconductor chip having bumps on its main surface is mounted face down.

[0002]

2. Description of the Related Art In a conventional semiconductor device, a large number of elements are formed on a semiconductor wafer (hereinafter, referred to as a wafer), and these are individually separated to form a semiconductor chip, and this chip is mounted on a lead frame or package. To perform required electrical connection and sealing with resin, ceramic, or the like. In manufacturing such a semiconductor device, a dicing step for separating the wafer into individual chips is necessary. Conventionally, one surface of the wafer is attached to an adhesive tape, and the other surface of the wafer is separated from the other surface. A method of cutting and separating with a dicing blade is used, but different methods are proposed depending on whether the surface to which this wafer is attached is on the main surface side where the elements are formed or on the opposite back side. Have been.

For example, in a wafer dicing method disclosed in Japanese Patent Application Laid-Open No. 4-298063, as shown in FIG. 4A, a main surface of a wafer 101 on which elements are formed is bonded to a UV tape to which a frame 103 is attached. A dicing blade 103 from the back side of the wafer 101
And cut into chips 101A. After the separation, the UV tape 102 is irradiated with UV light to weaken the adhesive force, and then the chip 101A mounted by the chip ejector 105 is pushed up from below the UV tape 102 as shown in FIG. The back surface of the chip 101A is sucked by the big collet 106 from above. Thereafter, as shown in FIG. 4C, the chip 101A is attached to the lead frame 107 by the pickup collet 106.
The chip is conveyed upward, pressed onto the lead frame 107, and an electrode (not shown) formed on the main surface of the chip 101A is connected to the lead frame surface by an ultrasonic bonding method or the like.

However, in this dicing method,
Since it is impossible to prevent cutting chips from adhering to the wiring on the chip main surface during dicing, there is a problem in that a chip having a bump on an electrode cannot prevent bump peeling or loose contact. That is, in recent years, consumer electronic devices such as mobile communication devices have been pursued to be smaller and lighter and have been offered to the market at lower prices. Therefore, the semiconductor device mounted inside the semiconductor device is strictly required to be small and thin and to be economical. As such a small and thin semiconductor device, a semiconductor device having a face-down structure using bumps (metal bumps) is preferable. However, bumps of this type have a height of 20-40 μm and a diameter of about 1 μm.
Since a spherical or tab-shaped metal of 00 μm is used, the UV
When the tape is attached and dicing is performed, pure water at the time of dicing enters the space between the UV tape formed by the bumps and the main surface of the wafer, and fine cutting particles enter at the same time. Another reason is that in the drying process after dicing, the space between the tape and the main surface of the chip cannot be sufficiently washed and dried. Furthermore, since a dicing load is applied to the chip or tape to apply dicing or cutting the corner of the chip back by attaching a UV tape to the bump side, stress acts on the interface between the chip and the bump, and chipping is likely to occur. According to

On the other hand, in the wafer dicing method disclosed in Japanese Patent Laid-Open No. 4-58547, as shown in FIG. 5A, a first frame 203 is attached to the back surface of a wafer 201 on which no elements are formed. The wafer 201 is affixed to the first UV tape 202 and full-cut diced from the main surface side of the wafer 201 on which the elements are formed with a dicing blade 204 over the entire thickness.
Separate into A. Thereafter, as shown in FIG.
01 with a second frame 206 attached to the main surface of
While affixing the tape 205, UV light is emitted from the back surface of the wafer 201 to weaken the adhesive force of the first UV tape 202, and then the first UV tape 202 as shown in FIG.
Peel off the UV tape 202. Next, as shown in FIG. 5D, the back surface of the wafer 201 held by the second UV tape 205 is scraped off by a second dicing blade 207 having a thick blade. Thus, chipping X generated on the back surface of the chip 201A formed at the time of the first dicing is removed.

In this dicing method, even when the present invention is applied to a wafer having a bump formed on the main surface, since the main surface side of the wafer is open at the time of dicing, cutting chips are formed on the wiring on the chip main surface as described above. This is effective in preventing adhesion, and is effective in preventing bump peeling and loose contact. However, since chipping is likely to remain on the wafer side, a step of shaving chips with a second dicing blade is required. Since the process time of the second dicing blade is long, manufacturing efficiency is extremely poor. Also, similar to the first prior art, an ineffective chip on the peripheral portion of the wafer, on which no element is formed, is left on the tape, so that the chip is mounted on a lead frame or the like in a later process. When doing, it is necessary to perform the task of handling chips while observing valid chips and invalid chips,
Mounting work tends to be complicated.

As a technique for removing invalid chips, Japanese Patent Laid-Open Publication No. Hei 3-167839 discloses a technique in which first and second UV tapes 302 and 303 are attached to both surfaces of a wafer 301 as shown in FIG. , On one side, here the second UV
Full cut dicing of the wafer 301 together with the UV tape from the tape 303 side by a dicing blade 309,
Separate into individual chips 301A. Thereby, scattering of cutting chips at the time of dicing is prevented. Next, FIG.
As described above, the ultraviolet rays from the first and second ultraviolet alligator lamps 306 and 307 are irradiated through the first and second masks 304 and 305. As a result, the adhesive force of the invalid chip 301B around the wafer 301 of the first UV tape 302 remains, and the adhesive force of the invalid chip 301B of the second UV tape 303 decreases. Next, as shown in FIG.
When the third tape 308 is peeled off after attaching the third tape 308 from above the second UV tape 303, the invalid chip 301B and the cut second UV tape 303 are removed, and the effective chip 301A is attached to the first UV tape 302. It is in a state of being pasted on.

[0008]

In the third technique,
Only one dicing is required as in the first prior art,
In addition, the invalid chips can be removed, but the cost is high because the third tape is required. Further, in the case of a wafer on which bumps are formed, the same problem as in the first related art occurs when dicing the rear surface side of the wafer. Further, when dicing the main surface side of the wafer, chipping residue is apt to occur, and chipping becomes a foreign matter when mounting a chip on a lead frame or the like, which causes an electrical short circuit accident. Further, in each of the prior arts described above, since the chips are arranged in a diced state, an interval between adjacent chips is narrow, and each chip cannot be handled by a pyramid collet or the like. Therefore, there is a problem that it has to be handled by a flat collet, it is difficult to perform ultrasonic bonding at the time of mounting on a lead frame or the like, and it is difficult to perform highly reliable chip bonding.

An object of the present invention is to provide a dicing method capable of preventing occurrence of chipping, preventing peeling of bumps and loose contacts, and removing an invalid chip without complicating a manufacturing process. It is in. Another object of the present invention is to provide a method of dicing a semiconductor wafer, in which the distance between adjacent diced chips is increased, handling by a pyramid collet or the like is enabled, and highly reliable chip bonding can be performed. It is in.

[0010]

According to the present invention, there is provided a process of attaching a first tape to a back surface of a wafer having a main surface on which elements and bumps are formed, and performing a full cut dicing of the wafer from the main surface side. Separating the first tape, so as to lift only the effective chips of the separated chips from the back surface of the first tape, and reducing the adhesive force of the first tape, The method includes a step of attaching a second tape to a main surface of the lifted effective chip, and a step of peeling the first tape from the back surface of each chip.

Further, in the present invention, in the step of stretching the first tape, the cross-sectional shape is inclined toward the outer periphery with the inner periphery being the apex, and the point on the inner periphery is closer to the center of the wafer. Using a stretching ring located at the boundary between the existing valid chips and the invalid chips existing on the peripheral side of the wafer, the first tape was stretched by pressing the stretching ring from the back side of the first tape. At this time, it is preferable that the first tape in a region where the invalid chip exists is inclined with respect to the tape plane direction. Further, in the step of stretching the first tape, a tape holding ring that presses from the surface side of the first tape at an outer peripheral position further than the outer peripheral side of the stretching ring is used, and the tape holding ring and the stretching ring are used. The first
It is preferable to increase the inclination angle of the tape.

When the first tape to which the full-cut dicing wafer is attached is stretched, chipping on the back surface of the chip caused by dicing is separated from the chip. Therefore, when the first tape is peeled off after the second tape is attached to the chip main surface, only the chip moves to the second tape, and the chipping remains on the first tape, and the chipping can be removed. Further, the expansion of the first tape expands the interval between the chips, enables handling with a pyramid collet or the like, and enables highly reliable chip bonding. Furthermore, when the first tape is stretched, the tape is inclined so that the invalid chips are also inclined along the tape, so that the invalid chips can be automatically removed without being attached to the second tape. It becomes possible.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings. 1 (a) to 1 (e) and FIG.
(A)-(d) is sectional drawing which shows 1st Embodiment of this invention in order of a process. First, as shown in FIG. 1A, a wafer 1 on which a large number of elements are formed and bumps 2 are formed corresponding to the respective elements is turned upward with the main surface on which the bumps 2 are formed. Then, it is stuck on the adhesive layer of the first UV tape 3 with the back surface opposite to the lower surface facing down. Further, the first frame 4 is attached to the adhesive layer of the UV tape 3 based on the center of the wafer 1. At this time, the first UV tape 3 protruding from the outer periphery of the first frame 4 is cut off. Next, as shown in FIG. 1B, the wafer 1 and the first UV tape 3 held by the first frame 4 are attached to a chucking table 5 of a dicing apparatus (not shown).
The wafer 1 is fully cut dicing over its entire thickness while being moved on a dicing line (not shown) on the main surface of the wafer 1 while the dicing blade 6 rotating at high speed is moved. The dicing is performed while spraying pure water on the cut portion in order to remove heat radiation and cutting chips. Although not shown, after dicing, washing with pure water,
Dry by centrifugal dehydration.

Next, as shown in FIG. 1C, the stretching ring 7 is pressed from below the first UV tape 3 to the downward main surface of the wafer 1, and in this state, the stretching ring 7 is pressed. Push up to stretch the first UV tape 3. The cross-sectional shape of the stretching ring 7 is inclined such that its outer peripheral surface 7b is expanded in diameter from above to below.
The apex 7a on the inner peripheral side is in contact with the back surface of the first UV tape 3. Further, the above-mentioned point portion 7a of the stretching ring 7
Are located at the boundary between an effective chip 1A on the peripheral portion of the wafer 1 on which elements are formed and an invalid chip 1B on the peripheral portion where no elements are formed. As a result, when the first UV tape 3 is stretched as described above, the cross section of the first UV tape 3 becomes oblique from the inner periphery of the stretching ring 7 to the lower side of the first frame 4, and the invalid chip on the outer periphery of the wafer 1B is inclined along the tape 3. Further, even when chipping X occurs at the back corner of each chip separated individually by the dicing, the chipping X is separated from each chip 1A, 1B by stretching the first UV tape 3.

Next, as shown in FIG. 1D, ultraviolet rays are irradiated from the back side of the first UV tape 2a,
Reduces the adhesive strength of Subsequently, as shown in FIG.
The adhesive layer side of the second UV tape 9 to which the second frame 8 has been attached is brought into contact with the main surface of the chip 1A on the first UV tape 3, and the main surface of the chip 1A is attached to the second UV tape 9. At this time, the second UV tape 9 is not attached to the invalid chip 1B that is inclined with the first UV tape 3. Then, as shown in FIG.
The first UV tape 3 is peeled off. At this time, the invalid chip 1B and the chipping X are peeled off while being bonded to the first UV tape 3, and as a result, the valid chip 1
Only A is transferred to the second UV tape 9 side.

Next, as shown in FIG. 2B, ultraviolet light is irradiated from the back side of the second UV tape 9 to weaken the adhesive force. Next, as shown in FIG. 2C, the second UV tape 9 is set at the chip handling position, and the back surface of the chip 1A on the second UV tape 9 is vacuum-adsorbed and handled by the pyramid collet 10. Then, as shown in FIG. 2D, the chip 1A is transported to the lead frame 11 on the bonding stage 12, and then subjected to face-down bonding using the bumps 2 and mounted. At this time, the pyramid collet 12 is vibrated by the ultrasonic generator 13 to connect the bumps, as in the conventional case.

In this embodiment, the first tape 3 is attached to the back surface of the wafer 1 on which the elements and the bumps 2 are formed on the main surface, and this is separated into individual chips by full-cut dicing. Since the dicing is not performed with the first tape 3 adhered to the main surface of the wafer 1 on which the bumps 2 are formed, and the rear surface of the chip is not cut again after dicing, the dicing is performed on the bumps 2 at the time of dicing. , The bumps can be prevented from peeling, and the manufacturing process can be simplified. Further, after dicing, the first tape 3 is stretched so that only the effective chip 1A is lifted from the back surface of the first tape 3, and the second tape 9 is attached to the main surface of the lifted effective chip 1A. Since the one tape 3 is peeled off from the back surface of the chip, when the first tape 3 to which the plurality of chips 1A and 1B formed by full-cut dicing are adhered is stretched, the back surface of the chip generated by dicing is removed. The chipping X is separated from the chips 1A and 1B, and can be removed. Further, the extension of the first tape 3 enlarges the interval between the chips, enables handling by the pyramid collet 10, and enables highly reliable chip bonding.

Further, in the step of stretching the first tape 3, the cross-sectional shape has an inclined surface 7b extending from the vertex portion 7a on the inner peripheral side to the outer peripheral side, and the terminating portion 7a has the valid chip 1A and the invalid chip When the stretching ring 7 positioned at the boundary with the first tape 3 is pressed from the back surface side of the first tape 3 and the first tape 3 is stretched, the invalid chip 1B is present. Area of the first tape 3
Is inclined with respect to the tape plane direction, so that the invalid chip 1B is also inclined along the tape,
The invalid chip 1B can be automatically removed without being attached to the second tape 9.

Next, a second embodiment of the present invention will be described with reference to FIG. FIGS. 3A to 3C are cross-sectional views showing a part of the process of the second embodiment, and the same reference numerals are given to the portions equivalent to those of the first embodiment. In this embodiment, as shown in FIG.
In the process of stretching the UV tape 3, the first UV tape 3 is sandwiched between the stretching ring 7A and the tape pressing ring 7B. After the first UV tape 3 is stretched by the stretching ring 7A in the same manner as in the first embodiment, the tape pressing ring 7B is pressed from the opposite side of the first UV tape 3 so as to press the first UV tape 3 in the area of the invalid chip 1B around the wafer.
The UV tape 3 is in an oblique state. The expansion ring 7
The cross-sectional shape of A has convex portions 7c and 7d on the inner peripheral portion and the outer peripheral portion, and the thickness of the convex portion 7d on the outer peripheral portion is 0.1% greater than that of the convex portion 7c on the inner peripheral portion.
０．２0.2 mm thick. Therefore, the extension ring 7A
The first UV tape 3 is stretched by the convex portion 7d on the outer peripheral portion of the first UV tape 3. Further, the tip of the convex portion 7c on the inner peripheral portion is located at the boundary between the invalid chip 1B and the valid chip 1A. The tape pressing ring 7B has an outer diameter that extends inside the convex portion 7d on the outer peripheral portion of the ring 7A, and an inner diameter that is sufficiently far from the inner periphery of the ring 7A.

Then, after irradiating ultraviolet rays from the back side of the first UV tape 3, a second UV tape 9 is attached as shown in FIG. 3B, and the first UV tape 3 is further applied as shown in FIG. By peeling off, the invalid chips 1B and chipping X remain on the first UV tape 3, and only the valid chips 1A are stuck to the second UV tape 9. Subsequent steps are the same as in the first embodiment.

In this embodiment as well, similar to the first embodiment, it is possible to prevent the peeling of the bumps, to simplify the process, and to remove chipping and automatically remove invalid chips. Can be. Further, in the second embodiment, the first UV tape 2a is stretched from the outer periphery of the stretching ring 7a as a starting point, so that the stretching area can be made wider, and the stretching ratio can be increased between the central portion and the outer periphery. And the arrangement of chips can be made uniform. There is also an advantage that the tape holding ring 7b can sufficiently separate the invalid chips 10 on the outer peripheral portion of the wafer on which the bumps 6 are not formed.

[0022]

As described above, according to the present invention, the first tape is attached to the back surface of the wafer having the elements and the bumps formed on the main surface, and the first tape is separated into individual chips by full-cut dicing. Stretching the first tape so as to lift only the effective chip from the back surface of the first tape, affixing the second tape to the main surface of the lifted effective chip, and peeling the first tape from the back surface of the chip Therefore, when the first tape to which the full-cut dicing wafer is attached is stretched, chipping on the back surface of the chip caused by dicing is separated from the chip. Therefore, when the first tape is peeled off after the second tape is attached to the chip main surface, only the chip moves to the second tape, and the chipping remains on the first tape, and the chipping can be removed. Further, the expansion of the first tape expands the interval between the chips, enables handling with a pyramid collet or the like, and enables highly reliable chip bonding.

Also, in the present invention, in the step of stretching the first tape, the cross-sectional shape is inclined toward the outer periphery with the inner periphery as the apex, and the point on the inner periphery is closer to the center of the wafer. When using a stretching ring positioned at the boundary between an existing effective chip and an invalid chip existing on the peripheral side of the wafer, and pressing the stretching ring from the back side of the first tape to extend the first tape In addition, by making the first tape in a region where an invalid chip is present inclined with respect to the tape plane direction, the invalid chip is also inclined along the tape, without being attached to the second tape, Invalid chips can be automatically removed.

Furthermore, in the present invention, dicing is not performed with the first tape adhered to the main surface of the wafer on which the bumps are formed, and the back surface of the chip is not cut again after dicing. There is no burden on the bumps at the time, and it is possible to prevent the bumps from peeling,
In addition, the manufacturing process can be simplified.

[Brief description of the drawings]

FIG. 1 is a first sectional view showing a semiconductor wafer dicing method of the present invention in the order of steps.

FIG. 2 is a second sectional view showing the semiconductor wafer dicing method of the present invention in the order of steps;

FIG. 3 is a cross-sectional view showing main steps of another embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a first method of the conventional dicing method in the order of steps.

FIG. 5 is a sectional view showing a second method of the conventional dicing method in the order of steps.

FIG. 6 is a sectional view showing a third method of the conventional dicing method in the order of steps.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wafer 1A Effective chip 1B Invalid chip 2 Bump 3 1st UV tape 4 1st frame 6 Dicing blade 7, 7A Extension ring 7B Holding ring 8 2nd frame 9 2nd UV tape 10 Pyramid collet 11 Lead frame 13 Ultrasonic wave generator

──────────────────────────────────────────────────続 き Continued on the front page (56) References JP-A-58-37932 (JP, A) JP-A-63-286302 (JP, A) JP-A-4-30558 (JP, A) JP-A-59-379 21038 (JP, A) JP-A-6-252262 (JP, A) JP-A-8-195361 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/301 H01L 21 / 68

Claims (5)

(57) [Claims] 1. A step of attaching a first tape to a back surface of a semiconductor wafer having elements and bumps formed on a main surface, and a step of separating the semiconductor wafer into individual chips by full-cut dicing from the main surface side Elongating the first tape so as to lift only effective chips of the separated chips from the back surface of the first tape, reducing the adhesive force of the first tape, and lifting the second tape A dicing method for a semiconductor wafer, comprising: a step of attaching the first tape to a main surface of the obtained effective chip; and a step of peeling the first tape from the back surface of each of the chips. 2. The method according to claim 1, wherein the first tape has an adhesive layer that loses adhesive strength when irradiated with ultraviolet rays, and the step of reducing the adhesive strength is a step of irradiating the first tape with ultraviolet rays. Semiconductor wafer dicing method 3. In the step of stretching the first tape, the cross-sectional shape is inclined toward the outer periphery with the inner periphery being the apex, and the point on the inner periphery is located at the center of the semiconductor wafer. When using a stretching ring positioned at the boundary between an effective chip and an invalid chip present on the peripheral side of the semiconductor wafer, and pressing the stretching ring from the back side of the first tape to stretch the first tape 3. The method for dicing a semiconductor wafer according to claim 1, wherein the first tape in a region where the invalid chip exists is inclined with respect to a tape plane direction. 4. In the step of stretching the first tape, a tape holding ring that presses from a surface side of the first tape at an outer circumferential position further than an outer circumferential side of the stretching ring is used, and the tape holding ring and the pulling ring are used. 4. The method according to claim 3, wherein an inclination angle of the first tape is increased with a stretching ring. 5. The irradiation of the first tape with ultraviolet rays using the stretching ring as a mask and irradiating only the first tape area corresponding to the inner peripheral area of the stretching ring. Semiconductor wafer dicing method.