JP3057225B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field-effect transistor, and more particularly to a field-effect semiconductor device using a compound semiconductor material and used for high-speed semiconductor devices, microwave / millimeter-wave devices, and the like.

The present invention can be applied to any of a field effect transistor, a high electron mobility transistor, and an electrostatic induction transistor, and exhibits the same effect. Therefore, the present invention covers all of these.

[0003]

2. Description of the Related Art In the following description of the prior art, the embodiments of the present invention, etc., and the drawings, like elements are denoted by like reference numerals.

FIG. 7 shows a conventional GaAs-MESFET (G
1 shows a schematic cross-sectional structure of a Schottky barrier gate type field effect transistor using aAs. In FIG.
1 is a semi-insulating GaAs substrate, 2 is a channel layer made of n-type GaAs, 3 is a contact layer made of n-type high impurity concentration GaAs, 4 is a source electrode making ohmic contact with the contact layer, and 5 is a A gate electrode 6 that makes a Schottky contact and a drain electrode 6 that makes an ohmic contact with the contact layer. In this transistor, in use, a bias is applied such that the gate electrode 5 is negative and the drain electrode 6 is positive with respect to the source electrode 4, and the flow of electrons indicated by the arrow 7 is controlled by the gate voltage. Works in form.

FIG. 8 is a schematic sectional view of a conventional GaAs high electron mobility transistor. In this case, the semiconductor device further includes a channel layer made of GaAs having an intrinsic property shown by 8 and an n-type A1GaAs electron supply layer shown by 9, and the electrons of the electron supply layer 9 are transferred to the i-type channel layer having almost no impurities. It has a structure in which electrons are dropped and electrons flow as shown by arrow 7.
In the case of FIG. 8, since electrons flow through the i-type channel having almost no impurities that hinder the traveling of electrons, there is an advantage that a higher-speed transistor can be easily obtained as compared with the case of FIG.

[0006]

However, the conventional transistor has problems from the viewpoint of maximizing the product of the response frequency and the breakdown voltage or securing the required breakdown voltage even at an ultra-high frequency. The problem will be described below.

The response time of these transistors is governed by the time for opening and closing the gate by charging or discharging the capacitance between the gate and the channel, and the time for electrons to travel through the depletion layer extending from the gate to the drain. Of these times, the charge / discharge time of the gate-channel capacitance is mainly determined by the product of the gate-source capacitance and the resistance. Therefore, if the capacitance is the same, the shorter the resistance, the shorter the time. Under the condition of a constant electron density or a constant impurity density, the higher the electron mobility, the lower the resistance value. Therefore, using a semiconductor material with a high electron mobility for the channel layer leads to an increase in speed.

However, since a material having a narrow bandgap has a higher electron mobility, a material having a high electron mobility necessarily leads to a material having a narrow bandgap.

On the other hand, the breakdown electric field due to the semiconductor avalanche is substantially proportional to the forbidden band width. FIG. 9 is a diagram showing the relationship between the forbidden band width and the breakdown field strength of some materials mainly including III-V compounds. In FIG. 9, the plot shows the impact ionization coefficient 1
When the breakdown electric field strength is defined by × 10 ⁴ / cm, the top of the upward arrow indicates the relationship between the breakdown electric field strength and the forbidden band width when the breakdown electric field strength is defined by the impact ionization coefficient 1 × 10 ⁵ / cm. Selection of a material having such a narrow bandgap (high electron mobility) leads to a decrease in breakdown electric field strength, which causes a problem that the breakdown voltage between the gate and the drain is reduced. If the breakdown voltage between the gate and the drain is to be kept constant, a wider depletion layer width is required to keep the electric field low. Therefore, the electron transit time of the depletion layer between the gate and the drain becomes longer.

Here, considering the cause of the above-mentioned problem in the conventional transistor, the electric field applied to the inside of the transistor varies depending on the location, but in the conventional transistor, the channel layer 2 (FIG. 7) or the channel layer 2 is not formed. It can be seen that the electron supply layer 9 (FIG. 8) is made of a uniform material from the source side to the drain side, so that the breakdown field strength is also uniform.

An object of the present invention is to solve the above-mentioned problems of the conventional transistor, improve the response frequency and breakdown voltage product of the transistor, and extend the upper limit of the response frequency while maintaining a practical breakdown voltage. Therefore, the performance of the ultra-high speed communication / information system will be improved (especially, the upper limit operation speed) and the quality will be improved through the performance improvement of the ultra-high speed transistor.

[0012]

According to the present invention, there is provided a semiconductor device comprising:
In a field-effect semiconductor device in which a source region, a gate region, and a drain region are formed in a base including a semiconductor layer, and a channel layer of the gate region is controlled by a gate electrode formed in the gate region, a forbidden band of the channel layer is provided. A semiconductor device having a width smaller than a forbidden band width of a drain region.

Further, the semiconductor device of the present invention is characterized in that the forbidden band width of the channel layer gradually changes so as to be narrow near the source region and wide near the drain region so as to be smoothly connected therebetween. Semiconductor device. Further, the semiconductor layer is a semi-insulating semiconductor substrate,
The channel layer is made of an n-type semiconductor material and is in contact with the base directly or via a buffer layer. The gate electrode in contact with the channel layer and an n-type contact layer formed in the source region and the drain region A semiconductor device having: Further, the present invention is a semiconductor device having an n-type electron supply layer which is in direct contact with the channel layer or via a spacer layer.

A semiconductor device according to the present invention includes a first n-type semiconductor layer having a first forbidden band width, a second n-type semiconductor layer provided so as to be in contact with the first semiconductor layer, and a second n-type semiconductor layer. An electric field having a third n-type semiconductor layer having a second forbidden band width provided so as to be in contact with the semiconductor layer and having a Schottky barrier gate in contact with at least a part of a side surface of the second semiconductor layer An effect-type semiconductor device, wherein the forbidden band width of the second n-type semiconductor layer is smaller than the first or second forbidden band width.

Further, in the semiconductor device according to the present invention, the first bandgap is wider than the second bandgap, and the bandgap of the second semiconductor layer is equal to the first and second bandgap. The semiconductor device is characterized by gradually changing so as to be smoothly connected to the semiconductor device.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to specific embodiments described below, but the present invention is not limited to the embodiments described herein. It goes without saying that those skilled in the art can make various modifications within the technical scope of the present invention.

An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a cross-sectional structure diagram for explaining the concept of the present invention, and FIG. 2 is a diagram showing a distribution of a forbidden band width of the channel material of the present invention.

The problem of the conventional transistor is, as described above, structurally because the material from the source side to the drain side is made of a uniform material. Unlike the conventional example shown in FIG. 7, the present invention does not use a material having a uniform band gap for the source region B1, the gate region B2, and the drain region B3 of the channel region shown in FIG. Required drain region B3
Is made of a material having a large forbidden band, and at least the source region B1 is made of a semiconductor material having a high forbidden band having a high electron mobility.

In the present invention, as shown in FIG. 2, the source side region B1 of the channel region is preferably made of a material having a small bandgap but high electron mobility, and the drain region B3 is formed with a bandgap. And a channel region B2 under the gate connecting B1 and B3 is forbidden band width so as to be smoothly connected to the channel region B1 on the source side and to the channel region B3 on the drain side. Is distributed. Therefore, the electrons are in the B1 region where the mobility is high, the region B2 where the forbidden band width is gradually changing,
And it flows through the region B3 where the forbidden band width is wide and the breakdown field strength is high.

FIG. 1 shows the case of a lateral transistor in which a current flows in parallel to the wafer surface. FIG. 3 shows a conceptual diagram of the case where the present invention is applied to a vertical transistor. The channel region 11 is formed in the vertical direction as shown by B1, B2, and B3, and the electron flow 12 goes from the upper part to the lower part as shown by the arrow. This transistor is configured as a vertical transistor in which a channel region B2 serving as a gate portion and a channel region B1 serving as a source portion are formed on a drain layer 10 made of, for example, n-type InP which itself forms a channel region B3. Is done. Then, a source electrode 4 and a drain electrode 6 are formed via the contact layer 3 respectively. Gate electrode 5 is formed on the side wall of channel region B2. The gate electrode 5 can be formed, for example, by depositing an electrode material on the front surface of the substrate and leaving the metal in the corner portion by utilizing the low etching rate in the corner portion.

FIGS. 1 and 3 show an example of a structure to which the present invention can be applied to a MESFET or an electrostatic induction transistor. As shown in FIG. 4, the application of the present invention to a high electron mobility transistor is similarly performed. be able to. In FIG. 4, reference numeral 9 denotes an electron supply layer, and the electron supply layer is desirably made of a material having a forbidden band width equal to or larger than that of the drain-side region B3 of the channel layer.

Here, a description will be given of an epitaxial growth technique which is particularly preferable for implementing the present invention. In epitaxial growth, it is desirable that the lattice constant of the crystal does not change with growth so that stress does not occur in the growth layer even if the composition changes. However, for example, InGaAs
In a method in which In is gradually replaced with Ga to increase the forbidden band width using a systemic compound semiconductor, the lattice constant decreases as the forbidden band increases as shown in FIG.

In practicing the present invention, it is desirable to change the forbidden band width while keeping the lattice constant constant as described above. Regarding how to keep the lattice constant constant,
The case of the vertical MESFET of FIG. 3 will be described. For this purpose, for example, an InP substrate is used. The source side region B1 of the channel is In _0.5 Ga _0.5 As, the drain side region B3 of the channel is InP, and the region B2 between them is I _0.5 Ga _0.5 As.
In _x Ga _{(1-x) Py} As gradually changing from n _0.5 Ga _0.5 As to InP along the line shown by the thick broken line in FIG.
_This is solved by _(1-y) .

Although the combination of In _0.5 Ga _0.5 As and InP has been described above, the present invention relates to a combination of other III-V compounds, for example, a combination of AlAs and GaAs.
Needless to say, the present invention can be applied to a combination of 1Sb and GaSb, a combination of AlP and GaP, and the like.

Next, an example of a method for manufacturing the channel region of the lateral transistor shown in FIG. 1 will be described. Generally, in the case of the lateral transistor shown in FIG. 1, it is difficult to change the forbidden band width in the horizontal direction on a flat wafer. However, as shown in FIG. 6, a selective mask 13 made of, for example, SiO _{2 is} used.
This can be realized by performing epitaxial growth after etching the semi-insulating InP substrate 14 by using. The etching is performed under such a condition that the etching rate in the horizontal direction with respect to the substrate is higher than the etching rate in the vertical direction so that a concave portion is formed below the mask 13. An epitaxial growth layer 15 is formed in the recess below the mask.

In FIG. 6, the portion where the epitaxial growth proceeds in the lateral direction from the plane PQ as indicated by the arrow _Vgl , and the plane QR
From the vertical direction as shown by the arrow V _gv , the growth rate ratio V _gl / V _gv can be obtained by changing the plane orientation of the plane PQ or OR, the temperature of epitaxial growth, and the gas supply rate.
Can be controlled. Sources actually required
Since the drain-to-drain dimension is about 1 to 2 μm, the selective epitaxial growth shown in FIG. 6 using the mask 13 is widely performed in ordinary semiconductor laser manufacturing and the like except that the forbidden band width is changed in the horizontal direction. Any of the selective epitaxial growth techniques can be used. Thus, channel regions B3, B2, B1 are formed in epitaxial growth layer 15.
Are sequentially formed in the horizontal direction.

The embodiments of the present invention described herein are merely examples, and the embodiments of the present invention can be variously modified. Note that, in the above embodiment, application to a field effect transistor and a high electron mobility transistor has been described. However, the invention can be applied to other field effect devices such as an electrostatic induction transistor. Demonstrate the effect of. In the above description, a transistor having a Schottky barrier gate has been described.
Metal / insulating film / semiconductor type with insulating film (MIS structure)
It goes without saying that a similar effect can be obtained even when applied to a transistor. Therefore, the present invention covers all semiconductor devices included in the technical scope of the present invention.

[0028]

As described above, according to the present invention, by using a material having a wide bandgap for the drain side region B3 of the channel, the breakdown voltage can be reduced without increasing the width of the depletion layer between the gate and the drain. As a result, the electron transit time of the depletion layer can be shortened. In addition, since a material having a narrow forbidden band width and a high electron mobility can be used on the source side without considering the restriction of the withstand voltage, the charge / discharge time of the gate can be shortened more than before.

[Brief description of the drawings]

FIG. 1 is a sectional structural view for explaining the concept of the present invention.

FIG. 2 is a diagram showing a distribution of a forbidden band width of the channel material of the present invention.

FIG. 3 is a sectional structural view of a vertical MESFET according to the present invention.

FIG. 4 is a diagram showing an application example of the present invention to a high electron mobility transistor.

FIG. 5 is a diagram showing a lattice constant and a forbidden band width of a III-V compound semiconductor.

FIG. 6 is a diagram showing selective epitaxial growth on a selectively etched semiconductor.

FIG. 7 is a schematic diagram of a cross-sectional structure of a conventional GaAs-MESFET.

FIG. 8 is a schematic sectional view of a conventional GaAs high electron mobility transistor.

FIG. 9: Forbidden band width and breakdown field strength of materials

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semi-insulating GaAs substrate 2 channel layer 3 contact layer 4 source electrode 5 gate electrode 6 drain electrode 7 electron flow 8 channel layer 9 electron supply layer 10 non-doped drain layer 11 channel region 12: electron flow 13: mask 14: semi-insulating InP substrate 15: epitaxial growth layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 21/336 H01L 29/78 H01L 29/80 H01L 29/812

Claims (6)

(57) [Claims] 1. A source region to the substrate including the semiconductor layer, a gate region, and a drain region is formed, in a field effect semiconductor device controlled by a gate electrode to the channel layer formed on a surface of said gate region, The game
The bandgap of the channel layer under the gate electrode is
Between the side and the channel under the gate electrode
A semiconductor device, wherein the forbidden band width of the layer is smaller than the forbidden band width of the drain region. 2. The device according to claim 1, wherein the forbidden band width of the channel layer is gradually changed so as to be narrow near the source region and wide near the drain region so as to be smoothly connected therebetween. Semiconductor device. 3. The semiconductor layer is a semi-insulating semiconductor substrate, the channel layer is made of an n-type semiconductor material and is in contact with the substrate directly or through a buffer layer, and a gate is in contact with the channel layer. 3. An electrode according to claim 1, further comprising an n-type contact layer formed in said source region and said drain region.
3. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 1, further comprising an n-type electron supply layer in contact with said channel layer directly or via a spacer layer. 5. A first n-type semiconductor layer having a first forbidden band width and a second n-type semiconductor layer provided on and in contact with the first semiconductor layer.
And a third n-type semiconductor layer having a second bandgap provided so as to be in contact with the second semiconductor layer, and a shot is formed on at least a part of the side surface of the second semiconductor layer. In the field effect type semiconductor device having a key barrier type gate extending , the forbidden band width of the second n-type semiconductor layer is the above-mentioned shot width.
From the source side to the drain side along the key barrier type gate
A semiconductor device wherein the forbidden band width of the second n-type semiconductor layer varies, and the forbidden band width is smaller than the first or second forbidden band width. 6. The first forbidden band width is wider than the second forbidden band width, and the forbidden band width of the second semiconductor layer gradually changes so as to be smoothly connected to the first and second forbidden band widths. The semiconductor device according to claim 5, wherein: