JP3411511B2 - Heterojunction field effect transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultra-high speed integrated circuit,
Regarding compound semiconductor field-effect transistors used as active elements such as millimeter-wave / microwave integrated circuits,
The present invention relates to a hetero-junction field-effect transistor that suppresses the accumulation of minority carriers generated by impact ionization in a compound semiconductor field-effect transistor, improves withstand voltage, characteristics stability, and reduces gate leakage current. 2. Description of the Related Art FIG. 5 shows a cross-sectional structure of a conventional heterojunction field effect transistor (HEMT) in which the layer structure is the same as the heterojunction field effect transistor of the present invention. 5, a buffer layer of a semi-insulating InP substrate an In _0.52 Al _0.48 As (thickness 2000 Å), an In _0.53 Ga _0.47 channel layer of As (thickness 150 angstroms), In _0.52 Al _0.48 As
(30 angstrom thick) spacer layer, In _0.52 Al _0.48 A doped with 1 × 10 ¹⁹ cm ⁻³ of Si as an impurity
s (50 angstrom thick) carrier supply layer, In
_{A 0.52} Al _0.48 As (100 angstrom thick) Schottky barrier layer and an InP (50 angstrom thick) etching stop layer are sequentially epitaxially grown by metal organic chemical vapor deposition or the like. In addition, S
In _0.52 Al _0.48 As doped with 6 × 10 ¹⁸ cm ^{-3 of} i
(150 angstrom thickness), 1 × Si as impurity
10 ¹⁹ cm ^-3 doped In _0.53 Ga _0.47 As (120 angstrom thick) is epitaxially grown as a cap layer, and the source and drain ohmic contact electrodes are formed by depositing Ti / Pt / Au or the like on the surface thereof. Formed, and these electrodes are electrically connected to a two-dimensional electron gas formed in the channel layer. In the gate region, the cap layer is removed by wet etching using a solution containing a redox agent, and Ti / Pt / Au is sequentially formed as a gate electrode on the surface of the etching stop layer or the surface of the Schottky barrier layer. The transistor operation is obtained by changing the concentration of the two-dimensional electron gas with a voltage applied to the gate electrode and controlling the current flowing between the source and the drain. The above-mentioned etching stop layer is for facilitating the etching operation in the process of manufacturing the transistor, and this layer becomes a part of the Schottky barrier layer according to the first aspect. In the HEMT having the above structure, InGaAs is used for a channel layer in which carriers travel. InGaAs has a small effective mass of electrons,
Although high mobility can be realized, it is advantageous for the high-frequency characteristics of a transistor. Electron-hole pairs are generated when impact ionization occurs. Among them, electrons flow to the drain electrode like other carrier electrons, but holes cannot flow to the source / drain electrodes due to the existence of the energy barrier.
There is also an energy barrier for holes between the channel layer and the buffer layer, and holes generated in the channel by impact ionization are likely to accumulate in the channel.
Further, as the frequency of impact ionization increases, the hole concentration increases, and some holes flow to the gate electrode, which is one of the causes of gate leakage current. Further, holes accumulated in the channel change the potential distribution in the transistor, change the source resistance and the threshold voltage, and as a result, the output characteristics of the transistor become unstable. In addition, changes in those properties can cause an increase in drain current, which can lead to transistor breakdown by increasing impact ionization. That is, the withstand voltage of the transistor is significantly reduced by the accumulation of holes. An object of the present invention is to provide a heterojunction field-effect transistor which solves the above-mentioned problems, has excellent withstand voltage and stable characteristics, and has a reduced gate leak current. [0005] All of the above problems result from the fact that holes generated by impact ionization accumulate in the channel. Therefore, the problem can be solved by extracting the generated holes to the outside of the transistor through a path other than the gate electrode. Therefore, what is considered is to adopt a structure suitable for allowing holes to pass through electrodes other than the gate electrode, that is, a part of the source / drain electrodes. Generally, the source / drain electrodes are provided with an n-type heavily doped layer at the uppermost portion of the epitaxial layer in order to realize an ohmic junction. This serves as a high energy barrier for holes. On the other hand, if the highly doped layer is removed and the electrode metal is deposited, as in the case of a gate electrode, a Schottky junction is formed, making it difficult for electrons to pass, so that contact resistance increases but holes easily pass. Therefore, by alternately arranging fine ohmic junctions and Schottky junctions in parallel with the traveling direction of electrons, it is possible to form a hole escape hole while suppressing an increase in contact resistance of the source / drain electrodes. FIG. 1 shows an embodiment of the present invention. 1A is a top view of a transistor having this structure, and FIG. 1B is a cross-sectional view perpendicular to the length direction of the gate electrode having the same structure. C) shows the ohmic electrode portion in the same structure (S- in FIG. 1B).
S ′) shows a vertical sectional view parallel to the length direction of the gate electrode. The structure of the epitaxial layer of the transistor having this structure is as described in the section of the prior art. FIG. 2 is a plan view showing the process from the epitaxial growth to the electrode formation in the manufacturing process of the transistor having the present structure, when the transistor is viewed from above. In FIG. 2, after the epitaxial growth is completed, first, the elements are separated by mesa etching or the like to obtain a state shown in FIG. 2A (a state in which the n-type heavily doped cap layer of one transistor is viewed from above). . Next, a fine line-shaped resist pattern is formed on the n-type high-concentration dope cap layer using an electron beam drawing technique or the like, and the n-type high-concentration dope cap layer is formed by wet etching or the like using the resist pattern as a mask. The etching is performed up to the etching stop layer to obtain the state shown in FIG. Next, a source / drain ohmic electrode (Ti / Pt / Au) is deposited by vapor deposition lift-off or the like to obtain the state shown in FIG. Next, a gate pattern of a resist is formed by using an electron repetitive drawing technique or the like, and using the resist as a mask, the n-type heavily doped cap layer in the gate region is etched to the etching stop layer to obtain the state of FIG. Next, a gate electrode (Ti / Pt / Au) is formed by vapor deposition lift-off or the like to obtain the state shown in FIG. At this time, the width (L ₁ in FIG. ₁ ) and the interval (FIG.
L ₂₎ in the ohmic portion (reduced L ₁ so holes are not accumulated in the R ₁₎ in FIG. 1, to reduce the L ₂ so as to suppress the increase of the contact resistance as much as possible is desirable.
In this example, although the etching stop layer is used,
Even if this is not used, the same structure and effect can be obtained if the etching of the n-type high-concentration doped cap layer is stopped when the Schottky barrier layer is exposed. Next, a description will be given of a mechanism by which the desired effect can be obtained by the above structure. FIG. 3A shows a cross-sectional view in the direction parallel to the gate of the ohmic electrode portion (the etching stop layer is omitted in the following figures). The part where the n-type heavily doped cap layer is on the surface (R ₁ ) is the part where the same layer is removed (R ₂ )
, The electrostatic potential for electrons is lower. Accordingly, the shape of the potential of the conduction band (Ec) and the valence band (Ev) in the horizontal direction along AA ′ of the channel layer in which electrons travel is as shown in FIG. That is, electrons exist in the R ₁ region and holes exist in the R ₂ region at a higher concentration. FIG. 4A is a sectional view in the direction parallel to the gate of the same ohmic electrode portion as FIG. 3A. R
Vertical potential shape along the S ₁ -S ₁ 'in the _first region in FIG. 4 (B), also, S in R ₂ region ₂
FIG. 4C shows the potential profile in the vertical direction along −S ₂ ′. In the R ₁ region, the presence of the heavily doped cap layer on the surface of the epitaxial layer lowers the potential barrier for electrons and keeps it thin. Therefore, an ohmic junction is realized for electrons, but a large potential barrier for holes. To prevent holes from passing from the channel to the electrode.
However, in the R ₂ region, a Schottky junction is formed with respect to the electrons, thereby preventing the electrons from being injected from the electrode into the channel. However, the potential barrier for the hole is reduced, and the hole is promoted to escape from the channel to the electrode. . As described above, the holes generated by impact ionization move below the source / drain electrodes, and then move to the R ₂ region due to the horizontal potential shape of the channel layer, and can escape to the electrodes. The accumulation of holes inside is suppressed. As a result, the problems in the prior art, that is, problems such as an increase in the gate leakage current of the transistor, instability of the output characteristics, and poor withstand voltage are solved. As described above, by implementing the present invention, it is possible to provide a hetero-junction field effect transistor having excellent withstand voltage and characteristic stability and reduced gate leak current.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a structure of a transistor according to the present invention. (A) is a top view of a transistor having this structure, (B) is a cross-sectional view in a direction perpendicular to a gate of the structure, and (C) is an ohmic electrode ((B) of the same structure).
3 is a cross-sectional view in the direction parallel to the gate SS ′ of FIG. FIG. 2 is a plan view of a transistor showing a process from epitaxial growth to electrode formation in a process for manufacturing a transistor according to the present invention. FIG. 3 is a diagram illustrating an effect provided by the present invention.
(A) is a sectional view in a direction parallel to the gate of the ohmic electrode in the structure of the transistor according to the present invention,
(B) is a diagram showing a potential shape in a cross section along AA ′ of (A). FIG. 4 is a diagram illustrating an effect provided by a structure of a transistor according to the present invention. (A) is a sectional view in the direction parallel to the gate of the ohmic electrode in the present structure,
(B) is a diagram showing a potential shape in a cross section along S ₁ -S ₁ ′ of (A), and (C) is a diagram showing S ₂ ,
It is a diagram showing the potential shape in cross-section along one S ₂ '. FIG. 5 shows a conventional heterojunction field effect transistor (H
FIG. 3 is a cross-sectional view illustrating a cross-sectional structure of (EMT).

Claims (1)

(57) [Claim 1] A buffer layer, a channel layer, a spacer layer, a carrier supply layer, a Schottky barrier layer, and a cap layer which is a high concentration impurity layer on a semiconductor substrate. Are sequentially deposited, a source electrode and a drain electrode are formed on the surface of the cap layer, an opening reaching the Schottky barrier layer is formed in the cap layer between the source electrode and the drain electrode, and the opening is formed in the opening. exposed a said Schottky barrier layer Ruhe hetero junction field effect transistor has a gate electrode is formed on the surface, the cap layer is composed of a plurality of thin lines, the groove bottom between said sub line
The Schottky barrier layer is exposed on the surface, the cap layer composed of the source electrode and the drain electrode in the thin line
In contact with the source electrode and the drain electrode.
The pole contacts the Schottky barrier layer exposed at the bottom of the groove between the fine wires to form a Schottky junction at the contact portion.
Heterojunction field effect transistor, characterized in that that.