JP3046193B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3046193B2
JP3046193B2 JP904994A JP904994A JP3046193B2 JP 3046193 B2 JP3046193 B2 JP 3046193B2 JP 904994 A JP904994 A JP 904994A JP 904994 A JP904994 A JP 904994A JP 3046193 B2 JP3046193 B2 JP 3046193B2
Authority
JP
Japan
Prior art keywords
filler
semiconductor element
semiconductor device
insulating substrate
weight
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP904994A
Other languages
Japanese (ja)
Other versions
JPH07221226A (en
Inventor
省吾 松尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP904994A priority Critical patent/JP3046193B2/en
Publication of JPH07221226A publication Critical patent/JPH07221226A/en
Application granted granted Critical
Publication of JP3046193B2 publication Critical patent/JP3046193B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Compositions Of Macromolecular Compounds (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はコンピューター等の情報
処理装置に搭載される半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounted on an information processing device such as a computer.

【0002】[0002]

【従来の技術】従来、コンピューター等の情報処理装置
に搭載されるプリモールドタイプ、或いはモールドタイ
プの半導体装置は、例えばプリモールドタイプの場合、
エポキシ樹脂から成り、上面に半導体素子を収容するた
めの凹部を有する絶縁基体と、前記絶縁基体の凹部内側
から外側にかけて導出する複数個の外部リード端子と、
前記絶縁基体の上面に封止材を介して取着され、絶縁基
体の凹部を塞ぐ蓋体とから構成される半導体素子収納用
パッケージを準備し、次に前記絶縁基体の凹部底面に半
導体素子を樹脂製接着材を介して取着するとともに該半
導体素子の各電極を外部リード端子の一端にボンディン
グワイヤを介して電気的に接続し、しかる後、前記絶縁
基体の上面に蓋体を樹脂製封止材を介して接合させ、半
導体素子を絶縁基体と蓋体とから成る容器内部に気密に
収容することによって製作され、またモールドタイプの
場合には、半導体素子と、ASTM Fー15(Feー
NiーCo合金)や42アロイ(FeーNi合金)等の
金属材料から成る基体及び複数個の外部リード端子と、
エポキシ樹脂等から成る被覆材とから構成されており、
前記基体上に半導体素子を金ーシリコン共晶合金等のロ
ウ材を介して固定するとともに半導体素子の各電極を外
部リード端子にボンディングワイヤを介して電気的に接
続し、しかる後、前記半導体素子、基体及び外部リード
端子の一部を被覆材で被覆することによって製作されて
いる。
2. Description of the Related Art Conventionally, a pre-mold type or a mold type semiconductor device mounted on an information processing device such as a computer is, for example, a pre-mold type semiconductor device.
An insulating base made of epoxy resin and having a concave portion for accommodating a semiconductor element on an upper surface, and a plurality of external lead terminals extending from the inside to the outside of the concave portion of the insulating base,
A semiconductor element housing package is prepared, comprising a lid attached to the upper surface of the insulating substrate via a sealing material and closing the concave portion of the insulating substrate, and then a semiconductor element is mounted on the bottom surface of the concave portion of the insulating substrate. Each electrode of the semiconductor element is electrically connected to one end of the external lead terminal via a bonding wire, and then a lid is sealed on the upper surface of the insulating base with a resin. It is manufactured by joining the semiconductor element through a stopper and hermetically housing the semiconductor element inside a container composed of an insulating base and a lid. In the case of a mold type, the semiconductor element is assembled with an ASTM F-15 (Fe- A base made of a metal material such as Ni-Co alloy) or 42 alloy (Fe-Ni alloy) and a plurality of external lead terminals;
And a coating material made of epoxy resin or the like,
A semiconductor element is fixed on the base via a brazing material such as a gold-silicon eutectic alloy, and each electrode of the semiconductor element is electrically connected to an external lead terminal via a bonding wire. It is manufactured by coating a part of the base and the external lead terminals with a coating material.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、この従
来の半導体装置においては、プリモールドタイプの場合
は絶縁基体が、またモールドタイプの場合は被覆材が夫
々、エポキシ樹脂から成り、該エポキシ樹脂等の樹脂材
は耐湿性に劣り水分を通し易いため、大気中に含まれる
水分が絶縁基体もしくは被覆材を通して内部に容易に浸
入し、その結果、半導体素子の電極やボンディングワイ
ヤ等に水分接触に起因する酸化腐食が発生するとともに
半導体素子の電極やボンディングワイヤに断線を招来し
て半導体装置としての機能が喪失するという欠点を有し
ていた。
However, in this conventional semiconductor device, the insulating substrate in the case of the pre-mold type and the coating material in the case of the mold type are each made of an epoxy resin. Since the resin material is inferior in moisture resistance and easily penetrates moisture, moisture contained in the air easily penetrates into the inside through the insulating base or the covering material, and as a result, the resin material comes into contact with electrodes, bonding wires, and the like due to moisture contact. Oxidative corrosion occurs, and the electrodes of the semiconductor element and the bonding wires are disconnected, so that the function as a semiconductor device is lost.

【0004】そこで、上記欠点を解消するために絶縁基
体、もしくは被覆材に水分の浸入を防止するためシリカ
やアルミナ等の粒子から成るフィラーを埋入させておく
ことが考えられる。
[0004] Therefore, in order to solve the above-mentioned drawbacks, it is conceivable to embed a filler composed of particles such as silica or alumina in order to prevent infiltration of moisture into the insulating substrate or the coating material.

【0005】しかしながら、絶縁基体もしくは被覆材に
シリカやアルミナ等から成るフィラーを埋入させた場
合、絶縁基体もしくは被覆材の成形性を考慮するとその
埋入量は最大で約95重量%であり、5重量%程度は依
然としてエポキシ樹脂等の樹脂材が存在するため、絶縁
基体や被覆材における水分の浸入は完全に遮断されず、
その結果、半導体素子の電極等に依然として酸化腐食が
発生するという欠点を有する。
However, when a filler made of silica, alumina, or the like is embedded in the insulating substrate or the covering material, the amount of embedding is up to about 95% by weight in consideration of the moldability of the insulating substrate or the covering material. Since about 5% by weight still contains a resin material such as an epoxy resin, infiltration of moisture into the insulating base and the coating material is not completely blocked,
As a result, there is a disadvantage that oxidative corrosion still occurs on the electrodes and the like of the semiconductor element.

【0006】[0006]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は、半導体素子の電極やボンディングワイ
ヤ等に酸化腐食による断線を発生することがなく、半導
体素子を長期間にわたり正常、且つ安定に作動させるこ
とができ、同時に絶縁基体や被覆材の成形性を良好とし
た半導体装置を提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to prevent disconnection of an electrode or a bonding wire of a semiconductor element due to oxidative corrosion and to maintain a semiconductor element for a long period of time. Another object of the present invention is to provide a semiconductor device which can be operated stably and at the same time has good moldability of an insulating substrate and a covering material.

【0007】[0007]

【課題を解決するための手段】本発明の半導体装置は樹
脂製絶縁基体と蓋体とから成る容器内部に半導体素子を
気密に収容してなる半導体装置であって、前記樹脂製絶
縁基体中にフィラーを60乃至95重量%埋入させると
ともに5乃至30重量%のフィラーに対し、容積が0.
1乃至2.0ml/gの細孔を形成したことを特徴とす
るものである。
A semiconductor device according to the present invention is a semiconductor device in which a semiconductor element is hermetically accommodated in a container formed of a resin insulating base and a lid, wherein the semiconductor element is contained in the resin insulating base. The filler is embedded in an amount of 60 to 95% by weight, and the volume of the filler is 0.5 to 30% by weight.
It is characterized in that pores of 1 to 2.0 ml / g are formed.

【0008】また本発明の半導体装置は、基体と、前記
基体上に固定される半導体素子と、前記半導体素子の電
極が接続される外部リード端子と、前記半導体素子、基
体及び外部リード端子の一部を被覆する樹脂製被覆材と
から成る半導体装置であって、前記樹脂製被覆材中にフ
ィラーを60乃至95重量%埋入させるとともに5乃至
30重量%のフィラーに対し、容積が0.1乃至2.0
ml/gの細孔を形成したことを特徴とするものである。
Further, the semiconductor device of the present invention comprises a base, a semiconductor element fixed on the base, an external lead terminal to which an electrode of the semiconductor element is connected, and one of the semiconductor element, the base and the external lead terminal. A resin coating material for covering a portion, wherein the filler is embedded in the resin coating material in an amount of 60 to 95% by weight, and the volume is 0.1% with respect to 5 to 30% by weight of the filler. To 2.0
It is characterized by forming pores of ml / g.

【0009】[0009]

【作用】本発明の半導体装置によれば、半導体素子を収
容する容器の樹脂製絶縁基体、あるいは半導体素子を被
覆する樹脂製被覆材にシリカ等から成るフィラーを60
乃至95重量%埋入させたことから絶縁基体や被覆材へ
の水分の浸入が、大幅に阻止され、また5乃至30重量
%のフィラーに対し、容積が0.1乃至2.0ml/gの細
孔を形成したことから絶縁基体や被覆材に浸入した少量
の水分は該細孔内に完全に吸着されることとなって半導
体素子やボンディングワイヤに水分が浸入到達すること
はなく、その結果、半導体素子の電極やボンディングワ
イヤに酸化腐食に起因する断線が発生することは一切な
く、半導体素子を長期間にわたり正常、安定に作動させ
ることができる。
According to the semiconductor device of the present invention, the filler made of silica or the like is added to the resin insulating base of the container for housing the semiconductor element or the resin coating material for coating the semiconductor element.
To 95% by weight, the penetration of moisture into the insulating substrate and the coating material is largely prevented, and the volume of 0.1 to 2.0 ml / g for 5 to 30% by weight of the filler. Due to the formation of the pores, a small amount of water that has penetrated into the insulating substrate or the coating material is completely adsorbed in the pores, and does not penetrate into the semiconductor element or the bonding wire. In addition, there is no occurrence of disconnection due to oxidation corrosion in the electrodes and bonding wires of the semiconductor element, and the semiconductor element can be operated normally and stably for a long period of time.

【0010】また本発明の半導体装置によれば絶縁基体
や被覆材に埋入されるフィラーの量が95重量%以下で
あることから絶縁基体や被覆材の成形性も極めて優れた
ものとなる。
Further, according to the semiconductor device of the present invention, since the amount of the filler embedded in the insulating substrate and the covering material is 95% by weight or less, the moldability of the insulating substrate and the covering material is also extremely excellent.

【0011】[0011]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。
BRIEF DESCRIPTION OF THE DRAWINGS FIG.

【0012】図1は本発明の半導体装置としてプリモー
ルドタイプを例に採った一実施例を示し、1は絶縁基
体、2は蓋体である。この絶縁基体1と蓋体2とで半導
体素子3を収容するための容器4が構成される。
FIG. 1 shows an embodiment in which a pre-mold type is taken as an example of a semiconductor device according to the present invention, wherein 1 is an insulating base, and 2 is a lid. The insulating base 1 and the lid 2 constitute a container 4 for housing the semiconductor element 3.

【0013】前記絶縁基体1はその上面中央部に半導体
素子3を収容するための凹部1aを有し、該凹部1a底
面には半導体素子3が樹脂製接着剤を介して接着固定さ
れる。
The insulating substrate 1 has a concave portion 1a for accommodating the semiconductor element 3 at the center of the upper surface thereof, and the semiconductor element 3 is bonded and fixed to the bottom surface of the concave portion 1a via a resin adhesive.

【0014】前記絶縁基体1はエポキシ樹脂等の樹脂か
ら成り、例えば所定型内にタブレット状に成形された粉
末のエポキシ樹脂をセットして注入するとともにこれを
150〜200℃の温度で熱硬化させることによって製
作される。
The insulating substrate 1 is made of a resin such as an epoxy resin. For example, a tablet-like powdered epoxy resin is set and injected into a predetermined mold, and is thermally cured at a temperature of 150 to 200 ° C. Produced by

【0015】また前記絶縁基体1はその内部にシリカ等
から成るフィラーが埋入されており、該フィラーは絶縁
基体1に大気中に含まれる水分が浸入しようとするのを
有効に阻止する作用を為す。
The insulating base 1 has a filler made of silica or the like embedded therein, and the filler has an effect of effectively preventing moisture contained in the air from entering the insulating base 1. Do

【0016】前記絶縁基体1に埋入されるフィラーはそ
の埋入量が60重量%未満となると絶縁基体1への水分
の浸入を有効に阻止できず、また95重量%を越えると
金型を用いて絶縁基体1を形成する際の成形性が悪くな
って所定形状の絶縁基体1が得られなくなる。従って、
前記絶縁基体1に埋入されるフィラーはその量が60乃
至95重量%の範囲に特定される。
If the amount of the filler to be embedded in the insulating substrate 1 is less than 60% by weight, it is not possible to effectively prevent moisture from penetrating into the insulating substrate 1; The moldability when forming the insulating substrate 1 by using the insulating substrate 1 is deteriorated, and the insulating substrate 1 having a predetermined shape cannot be obtained. Therefore,
The amount of the filler embedded in the insulating base 1 is specified in the range of 60 to 95% by weight.

【0017】尚、前記フィラーは所定型内に注入された
エポキシ樹脂を熱硬化させることによって絶縁基体1を
形成する際、型内に注入されたエポキシ樹脂に予めシリ
カ等から成る粉末を添加混合しておくことによって絶縁
基体1に埋入される。
When the insulating substrate 1 is formed by thermosetting the epoxy resin injected into a predetermined mold, the filler is mixed with a powder made of silica or the like in advance to the epoxy resin injected into the mold. By doing so, it is embedded in the insulating base 1.

【0018】また前記フィラーは直径が1乃至10μm
の球状と成しておくと、絶縁基体1への埋入が絶縁基体
1の全体にわたって均一、且つ高密度となり、これによ
って絶縁基体1全体における水分の浸入を有効に阻止す
ることが可能となる。従って、前記絶縁基体1に埋入さ
れるフィラーは直径が1乃至10μmの球状と成してお
くことが好ましい。
The filler has a diameter of 1 to 10 μm.
When the shape is formed into a spherical shape, the embedding into the insulating substrate 1 becomes uniform and dense over the entire insulating substrate 1, whereby it is possible to effectively prevent the penetration of moisture into the entire insulating substrate 1. . Therefore, it is preferable that the filler to be embedded in the insulating substrate 1 is formed in a spherical shape having a diameter of 1 to 10 μm.

【0019】更に前記絶縁基体1に埋入されたフィラー
はその5乃至30重量%に対し、容積が0.1乃至2.
0ml/gの細孔が形成されており、該細孔によって絶縁基
体1に浸入した少量の水分を完全に吸着し、水分が半導
体素子3や後述するボンディングワイヤ6にまで浸入
し、半導体素子3等に水分が接触するのを防止する。
Further, the volume of the filler embedded in the insulating substrate 1 is 0.1 to 2% with respect to 5 to 30% by weight of the filler.
The pores of 0 ml / g are formed, and the pores completely adsorb a small amount of water penetrating into the insulating base 1, and the water penetrates into the semiconductor element 3 and a bonding wire 6 described later, and the semiconductor element 3 Prevent moisture from coming into contact with etc.

【0020】前記フィラーの細孔は、例えばまず、珪酸
アルカリ金属、アルミン酸アルカリ金属、シリカゾル等
の出発原料を混合するとともにこれを約80〜120℃
の温度で水熱反応を起こさせてゼオライト(アルミニウ
ムとシリコンから成る)の結晶を析出させ、次に前記ゼ
オライトと珪酸アルカリ金属とを含有する水性スラリー
を作成するとともに該スラリーに酸を添加してゼオライ
トから成る芯体に非晶質シリカから成る多孔質の被覆層
を被着させた被覆粒子を形成し、しかる後、前記被覆粒
子に更に酸を作用させ、被覆粒子のゼオライト中のアル
カリ金属成分及びアルミニウム成分の一部を溶出させる
ことによって形成される。
The pores of the filler are first mixed with starting materials such as alkali metal silicate, alkali metal aluminate, silica sol and the like, and heated to about 80 to 120 ° C.
A hydrothermal reaction is caused at the temperature to precipitate crystals of zeolite (composed of aluminum and silicon), and then an aqueous slurry containing the zeolite and the alkali metal silicate is prepared, and an acid is added to the slurry. Forming coated particles in which a porous coating layer made of amorphous silica is applied to a core made of zeolite, and thereafter, an acid is further applied to the coated particles, and an alkali metal component in the zeolite of the coated particles is formed. And a part of the aluminum component is eluted.

【0021】尚、前記細孔を有するフィラーは絶縁基体
1に埋入させたフィラーに対し、5重量%未満であると
絶縁基体1に浸入した水分の半導体素子3等への到達を
完全に防止することができず、また30重量%を越える
と金型を用いて絶縁基体1を形成する際の成形性が悪く
なって所定形状の絶縁基体1が得られなくなる。従っ
て、細孔を有するフィラーは絶縁基体1に埋入させたフ
ィラーに対し、5乃至30重量%の範囲に特定される。
If the amount of the filler having the pores is less than 5% by weight of the filler embedded in the insulating substrate 1, it is possible to completely prevent the moisture penetrating the insulating substrate 1 from reaching the semiconductor element 3 and the like. If it exceeds 30% by weight, the moldability of forming the insulating substrate 1 using a mold deteriorates, and the insulating substrate 1 having a predetermined shape cannot be obtained. Therefore, the filler having pores is specified in the range of 5 to 30% by weight based on the filler embedded in the insulating substrate 1.

【0022】また前記フィラーに形成する細孔はその容
積が0.1ml/g未満であると絶縁基体1に浸入した水分
を完全に吸着させることができず、また2.0ml/gを越
えると金型を用いて絶縁基体1を形成する際の成形性が
悪くなって所定形状の絶縁基体1が得られなくなる。従
って、フィラーに形成する細孔はその容積が0.1乃至
2.0ml/gの範囲に特定される。
If the volume of the pores formed in the filler is less than 0.1 ml / g, it is not possible to completely adsorb moisture penetrating into the insulating substrate 1, and if it exceeds 2.0 ml / g. The moldability when forming the insulating base 1 using a mold is deteriorated, and the insulating base 1 having a predetermined shape cannot be obtained. Therefore, the pores formed in the filler have a volume specified in the range of 0.1 to 2.0 ml / g.

【0023】更に前記フィラーに形成する細孔はその孔
径を直径3乃至200オングストロームの範囲としてお
くと絶縁基体1内に浸入してきた少量の水分は細孔に完
全に吸着保持され、これによって水分が半導体素子3等
にまで浸入するのをより確実に防止することが可能とな
る。従って、前記フィラーに形成する細孔はその孔径を
直径3乃至200オングストロームの範囲としておくこ
とが好ましい。
Further, if the pores formed in the filler have a pore diameter in the range of 3 to 200 angstroms, a small amount of water that has penetrated into the insulating substrate 1 is completely adsorbed and held by the pores. It is possible to more reliably prevent intrusion into the semiconductor element 3 and the like. Therefore, it is preferable that the pores formed in the filler have a pore diameter in a range of 3 to 200 angstroms.

【0024】前記フィラーが埋入された絶縁基体1はま
たその凹部1a内側から外側にかけて複数個の外部リー
ド端子5が取着されており、該外部リード端子5の凹部
1a内側に露出する各々の部位には半導体素子3の各電
極がボンディングワイヤ6を介して電気的に接続され、
また外側に露出する部位には外部電気回路が接続され
る。
The insulating substrate 1 in which the filler is embedded has a plurality of external lead terminals 5 attached from the inside to the outside of the recess 1a, and each of the external lead terminals 5 is exposed inside the recess 1a. Each electrode of the semiconductor element 3 is electrically connected to the site via a bonding wire 6,
An external electric circuit is connected to a portion exposed to the outside.

【0025】前記外部リード端子5はASTM Fー1
5(FeーNiーCo合金)や42アロイ(FeーNi
合金)等の金属材料から成り、ASTM Fー15等の
インゴット(塊)を圧延加工法や打ち抜き加工法等、従
来周知の金属加工法を採用することによって所定の板状
に形成される。
The external lead terminal 5 is ASTM F-1.
5 (Fe-Ni-Co alloy) and 42 alloy (Fe-Ni
Alloy) or the like, and is formed into a predetermined plate shape by adopting a conventionally known metal working method such as a rolling method or a punching method on an ingot (lump) such as ASTM F-15.

【0026】前記外部リード端子5はタブレット状に成
形された粉末のエポキシ樹脂を所定型内にセットし注入
することによって絶縁基体1を製作する際、所定型内の
所定位置に予めセットしておくことによって絶縁基体1
の凹部1a内側から外側にかけて一体的に取着される。
The external lead terminals 5 are previously set at predetermined positions in the predetermined mold when the insulating base 1 is manufactured by setting and injecting a tablet-like powdered epoxy resin into a predetermined mold. Insulating substrate 1
Are integrally attached from the inside to the outside of the concave portion 1a.

【0027】尚、前記外部リード端子5はその露出する
表面にニッケル、金等の耐蝕性に優れ、且つロウ材と濡
れ性の良い金属を0.1乃至20μmの厚みに層着させ
ておくと外部リード端子5の酸化腐食を有効に防止する
ことができるとともに外部リード端子5とボンディング
ワイヤ6の接続及び外部リード端子5と外部電気回路と
の接続を強固となすことができる。従って、前記外部リ
ード端子5はその露出する表面にニッケル、金等を0.
1乃至20μmの厚みに層着させておくことが好まし
い。
The external lead terminal 5 is preferably formed by coating a metal having excellent corrosion resistance such as nickel and gold and having good wettability with a brazing material to a thickness of 0.1 to 20 μm on the exposed surface. Oxidation corrosion of the external lead terminal 5 can be effectively prevented, and the connection between the external lead terminal 5 and the bonding wire 6 and the connection between the external lead terminal 5 and the external electric circuit can be made strong. Therefore, the external lead terminal 5 is coated with nickel, gold, or the like on the exposed surface of the external lead terminal 5.
It is preferable to coat the layer to a thickness of 1 to 20 μm.

【0028】前記外部リード端子5が取着された絶縁基
体1は更にその上面にガラス、セラミック、金属、樹脂
等の板材から成る蓋体2が樹脂製封止材を介して取着さ
れ、蓋体2で絶縁基体1の凹部1aを塞ぎ、絶縁基体1
と蓋体2とから成る容器4の内部を気密に封止し、容器
4内部に半導体素子3を気密に収容することによって最
終製品としての半導体装置となる。
The insulating substrate 1 to which the external lead terminals 5 are attached is further provided with a lid 2 made of a plate material such as glass, ceramic, metal, or resin via a resin sealing material. The body 2 closes the concave portion 1a of the insulating base 1, and the insulating base 1
The inside of the container 4 composed of the container 2 and the lid 2 is hermetically sealed, and the semiconductor element 3 is hermetically accommodated inside the container 4 to obtain a semiconductor device as a final product.

【0029】また図2は本発明の半導体装置の他の実施
例を示し、ASTM Fー15(FeーNiーCo合
金)や42アロイ(FeーNi合金)等の金属材料から
成る基体11と、複数個の外部リード端子13を準備
し、基体11上に半導体素子12を金ーシリコン共晶合
金等のロウ材を介して固定するとともに半導体素子12
の各電極を外部リード端子13にボンディングワイヤ1
4を介して電気的に接続し、しかる後、前記半導体素子
12、基体11及び外部リード端子13の一部をエポキ
シ樹脂等の樹脂材から成る被覆材15で被覆することに
よって製作したものである。この場合、被覆材15に前
述の実施例と同様、シリカ等から成るフィラーを60乃
至95重量%埋入させ、且つそのうちの5乃至30重量
%のフィラーに対し、容積を0.1乃至2.0ml/gとす
る細孔を形成しておくと大気中に含まれる水分が被覆材
15に浸入して、半導体素子12等に水分が接触するの
が皆無となり、その結果、半導体素子12の電極等に酸
化腐食を発生することはなく半導体素子12を長期間に
わたり正常、且つ安定に作動させることができる。
FIG. 2 shows another embodiment of the semiconductor device according to the present invention, in which a base 11 made of a metal material such as ASTM F-15 (Fe-Ni-Co alloy) or 42 alloy (Fe-Ni alloy) is used. A plurality of external lead terminals 13 are prepared, and the semiconductor element 12 is fixed on the base 11 via a brazing material such as a gold-silicon eutectic alloy.
Bonding wires 1 to the external lead terminals 13
4 and then a part of the semiconductor element 12, the base 11, and the external lead terminals 13 is covered with a covering material 15 made of a resin material such as an epoxy resin. . In this case, similarly to the above-described embodiment, 60 to 95% by weight of a filler made of silica or the like is embedded in the coating material 15, and the volume of 0.1 to 2.% is added to 5 to 30% by weight of the filler. If pores having a concentration of 0 ml / g are formed, moisture contained in the air penetrates into the coating material 15 and the moisture does not come into contact with the semiconductor element 12 or the like. For example, the semiconductor element 12 can be operated normally and stably for a long time without causing oxidative corrosion.

【0030】また前記被覆材15に埋入させるフィラー
の量は95重量%以下であることから半導体素子12が
固定された基体11及び外部リード端子13を所定の治
具内にセットするとともに治具内にエポキシ等の液状樹
脂を適下注入し、しかる後、注入した樹脂を180℃程
度の温度、100kgf/mm2 程度の圧力を加え熱硬
化させることによって前記基体11、半導体素子12及
び外部リード端子13の一部を被覆材15で被覆する
際、被覆材15の成形性が極めて優れたものとなって所
定形状に成形することが可能となる。
Since the amount of the filler to be embedded in the coating material 15 is 95% by weight or less, the base 11 to which the semiconductor element 12 is fixed and the external lead terminals 13 are set in a predetermined jig, and A liquid resin such as epoxy is appropriately injected into the inside, and then the injected resin is thermally cured by applying a temperature of about 180 ° C. and a pressure of about 100 kgf / mm 2 , thereby forming the base 11, the semiconductor element 12, and the external leads. When a part of the terminal 13 is covered with the covering material 15, the formability of the covering material 15 is extremely excellent, and it is possible to mold the terminal 13 into a predetermined shape.

【0031】[0031]

【発明の効果】本発明の半導体装置によれば、半導体素
子を収容する容器の樹脂製絶縁基体あるいは半導体素子
を被覆する樹脂製被覆材にシリカ等から成るフィラーを
60乃至95重量%埋入させたことから絶縁基体や被覆
材への水分の浸入が、大幅に阻止され、また5乃至30
重量%のフィラーに対し、容積が0.1乃至2.0ml/g
のの細孔を形成したことから絶縁基体や被覆材に浸入し
た少量の水分は該細孔内に完全に吸着されることとなっ
て半導体素子やボンディングワイヤに水分が浸入到達す
ることはなく、その結果、半導体素子の電極やボンディ
ングワイヤに酸化腐食に起因する断線が発生することは
一切なく、半導体素子を長期間にわたり正常、安定に作
動させることができる。
According to the semiconductor device of the present invention, 60 to 95% by weight of a filler made of silica or the like is embedded in a resin insulating base of a container for housing a semiconductor element or a resin coating material for coating the semiconductor element. Therefore, infiltration of moisture into the insulating substrate and the coating material is largely prevented, and 5 to 30
The volume is 0.1 to 2.0 ml / g with respect to the filler by weight.
Since a small amount of water has penetrated into the insulating substrate or the coating material since the pores were formed, the water did not penetrate into the semiconductor element or the bonding wire without reaching the semiconductor element or the bonding wire. As a result, there is no disconnection of the electrodes and bonding wires of the semiconductor element due to oxidative corrosion, and the semiconductor element can be operated normally and stably for a long period of time.

【0032】また本発明の半導体装置によれば絶縁基体
や被覆材に埋入されるフィラーの量が95重量%以下で
あることから絶縁基体や被覆材の成形性も極めて優れた
ものとなる。
Further, according to the semiconductor device of the present invention, since the amount of the filler embedded in the insulating substrate and the covering material is 95% by weight or less, the moldability of the insulating substrate and the covering material is extremely excellent.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の一実施例を示す断面図で
ある。
FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention.

【図2】本発明の半導体装置の他の実施例を示す断面図
である。
FIG. 2 is a sectional view showing another embodiment of the semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

1・・・絶縁基体 2・・・蓋体 3・・・半導体素子 4・・・容器 5・・・外部リード端子 DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Lid 3 ... Semiconductor element 4 ... Container 5 ... External lead terminal

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】樹脂製絶縁基体と蓋体とから成る容器内部
に半導体素子を気密に収容してなる半導体装置であっ
て、前記樹脂製絶縁基体中にフィラーを60乃至95重
量%埋入させるとともに5乃至30重量%のフィラーに
対し、容積が0.1乃至2.0ml/gの細孔を形成し
たことを特徴とする半導体装置。
1. A semiconductor device in which a semiconductor element is hermetically housed in a container comprising a resin insulating base and a lid, wherein a filler is embedded in the resin insulating base in an amount of 60 to 95% by weight. A semiconductor device characterized by forming pores having a volume of 0.1 to 2.0 ml / g with respect to 5 to 30% by weight of a filler.
【請求項2】基体と、前記基体上に固定される半導体素
子と、前記半導体素子の電極が接続される外部リード端
子と、前記半導体素子、基体及び外部リード端子の一部
を被覆する樹脂製被覆材とから成る半導体装置であっ
て、前記樹脂製被覆材中にフィラーを60乃至95重量
%埋入させるとともに5乃至30重量%のフィラーに対
し、容積が0.1乃至2.0ml/gの細孔を形成した
ことを特徴とする半導体装置。
2. A base, a semiconductor element fixed on the base, an external lead terminal to which an electrode of the semiconductor element is connected, and a resin made of resin covering a part of the semiconductor element, the base and the external lead terminal. A semiconductor device comprising a coating material, wherein 60 to 95% by weight of a filler is embedded in the resinous coating material, and a volume of 0.1 to 2.0 ml / g with respect to 5 to 30% by weight of the filler. A semiconductor device comprising:
【請求項3】前フィラーを直径が1乃至10μmの球
状としたことを特徴とする請求項1又は請求項2に記載
の半導体装置。
3. A pre-Symbol semiconductor device according to claim 1 or claim 2 filler diameter is characterized in that a 1 to 10μm spherical.
【請求項4】前記フィラーに形成する細孔の孔径を直径
3乃至200オングストロームとしたことを特徴とする
請求項1又は請求項2に記載の半導体装置。
4. The semiconductor device according to claim 1, wherein the diameter of the pores formed in the filler is 3 to 200 Å.
JP904994A 1994-01-31 1994-01-31 Semiconductor device Expired - Lifetime JP3046193B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP904994A JP3046193B2 (en) 1994-01-31 1994-01-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP904994A JP3046193B2 (en) 1994-01-31 1994-01-31 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH07221226A JPH07221226A (en) 1995-08-18
JP3046193B2 true JP3046193B2 (en) 2000-05-29

Family

ID=11709790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP904994A Expired - Lifetime JP3046193B2 (en) 1994-01-31 1994-01-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3046193B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110199368B (en) * 2017-01-31 2022-04-26 松下知识产权经营株式会社 Electrolytic capacitor

Also Published As

Publication number Publication date
JPH07221226A (en) 1995-08-18

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