JP2538845Y2 - Package for storing semiconductor elements - Google Patents

Package for storing semiconductor elements

Info

Publication number
JP2538845Y2
JP2538845Y2 JP1991038422U JP3842291U JP2538845Y2 JP 2538845 Y2 JP2538845 Y2 JP 2538845Y2 JP 1991038422 U JP1991038422 U JP 1991038422U JP 3842291 U JP3842291 U JP 3842291U JP 2538845 Y2 JP2538845 Y2 JP 2538845Y2
Authority
JP
Japan
Prior art keywords
metal layer
semiconductor element
insulating base
concave portion
lid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1991038422U
Other languages
Japanese (ja)
Other versions
JPH04131947U (en
Inventor
貢 浦谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP1991038422U priority Critical patent/JP2538845Y2/en
Publication of JPH04131947U publication Critical patent/JPH04131947U/en
Application granted granted Critical
Publication of JP2538845Y2 publication Critical patent/JP2538845Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Die Bonding (AREA)

Description

【考案の詳細な説明】[Detailed description of the invention]

【0001】[0001]

【産業上の利用分野】本考案は半導体素子を収容するた
めの半導体素子収納用パッケージの改良に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor device housing package for housing a semiconductor device.

【0002】[0002]

【従来の技術】従来、半導体素子、特にLSI等の半導
体集積回路素子を収容するための半導体素子収納用パッ
ケージはアルミナセラミックス等の電気絶縁材料から成
り、中央部に半導体素子を収容する空所を形成するため
の凹部を有し、上面に封止用の低融点ガラス層が被着さ
れた絶縁基体と、同じくアルミナセラミックス等の電気
絶縁材料から成り、中央部に半導体素子を収容する空所
を形成するための凹部を有し、下面に封止用の低融点ガ
ラス層が被着された蓋体と、内部に収容する半導体素子
を外部の電気回路に電気的に接続するための外部リード
端子とから構成されており、絶縁基体の上面に外部リー
ド端子を載置させるとともに予め被着させておいた封止
用の低融点ガラス層を溶融させることによって外部リー
ド端子を絶縁基体に仮止めし、次に前記絶縁基体の凹部
底面に予め層着させておいた金属層に接着材を介して半
導体素子を取着するとともに該半導体素子の各電極をボ
ンディングワイヤを介して外部リード端子に接続し、し
かる後、絶縁基体と蓋体とをその相対向する各々の主面
に被着させておいた封止用の低融点ガラス層を溶融一体
化させ、絶縁基体と蓋体とから成る容器を気密に封止す
ることによって製品としての半導体装置となる。
2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element, particularly a semiconductor integrated circuit element such as an LSI, is made of an electrically insulating material such as alumina ceramics, and has a central space for housing the semiconductor element. An insulating base having a concave portion for forming, a low-melting glass layer for sealing is adhered on the upper surface, and a cavity for accommodating a semiconductor element in the center portion also made of an electrically insulating material such as alumina ceramics. A lid having a concave portion for forming, a lower-melting glass layer for sealing attached to the lower surface, and an external lead terminal for electrically connecting a semiconductor element housed therein to an external electric circuit An external lead terminal is placed on the upper surface of the insulating base and the sealing is performed on the external lead terminal by melting the low-melting glass layer for sealing which has been applied in advance. The semiconductor element is temporarily fixed, and then a semiconductor element is attached via an adhesive to a metal layer previously layered on the bottom of the concave portion of the insulating base, and each electrode of the semiconductor element is connected to an external lead terminal via a bonding wire. After that, a low-melting glass layer for sealing, in which the insulating base and the lid are adhered to the respective main surfaces facing each other, is melted and integrated, and the insulating base and the lid are separated from each other. A semiconductor device as a product is obtained by hermetically sealing the container.

【0003】尚、前記絶縁基体の凹部底面に層着させた
金属層は平均粒径1.0 乃至3.0 μmの銀粉末に適当な有
機溶剤、溶媒を添加混合して成る導電ペーストを絶縁基
体の凹部底面に滴下し、約10〜15μm の均一厚みに拡散
させた後、約900 ℃の温度で焼成することによって絶縁
基体の凹部底面に層着される。
The metal layer deposited on the bottom surface of the concave portion of the insulating substrate is formed by adding a conductive paste obtained by adding a suitable organic solvent and a solvent to silver powder having an average particle size of 1.0 to 3.0 μm and mixing the conductive paste. And diffused to a uniform thickness of about 10 to 15 μm, and then fired at a temperature of about 900 ° C. to be layered on the bottom surface of the concave portion of the insulating substrate.

【0004】また前記半導体素子を金属層上に取着する
接着材は金たは金 シリコン共晶半田等の薄板から成
り、該接着材を絶縁基体に設けた凹部底面の金属層と半
導体素子との間に介在させ、しかる後、これを加熱溶融
させることによって半導体素子を絶縁基体の凹部底面に
取着する。
The adhesive for attaching the semiconductor element to the metal layer is made of a thin plate such as gold or gold-silicon eutectic solder. Then, the semiconductor element is attached to the bottom surface of the concave portion of the insulating base by heating and melting the semiconductor element.

【0005】[0005]

【考案が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージにおいては、絶縁基体
の凹部底面に層着される金属層が銀から成り、該銀は酸
化され易い金属であることから絶縁基体の凹部底面に金
属層を層着させた場合、該金属層にはその表面に極めて
短時間に酸化物膜が形成されてしまい、一旦、表面に酸
化物膜が形成されると金属層上に半導体素子を金たは金
シリコン共晶半田等から成る接着材を介して取着する
際、接着材の金属層に対する接合強度が金属層表面の酸
化物膜によって極めて弱いものとなり、その結果、半導
体素子に外力が印加されると該外力によって半導体素子
が金属層より極めて容易に外れてしまうという欠点を有
していた。
However, in this conventional package for housing a semiconductor element, the metal layer deposited on the bottom of the concave portion of the insulating base is made of silver, which is a metal that is easily oxidized. When a metal layer is deposited on the bottom surface of the concave portion of the insulating base, an oxide film is formed on the surface of the metal layer in a very short time, and once the oxide film is formed on the surface, the metal layer is formed. When a semiconductor element is mounted on an adhesive made of gold or gold silicon eutectic solder, etc., the bonding strength of the adhesive to the metal layer becomes extremely weak due to the oxide film on the metal layer surface. However, when an external force is applied to the semiconductor element, the semiconductor element is very easily detached from the metal layer due to the external force.

【0006】また前記銀から成る金属層は絶縁基体の凹
部底面に焼き付けによって層着されているものの銀と絶
縁基体とは反応性が弱いため両者の接合強度は極めて弱
く、その結果、金属層上に半導体素子を接着材を加熱溶
融させることによって取着する際、半導体素子の形状が
大型化し、接着材の量が多くなると該接着材による引っ
張り力によって金属層が半導体素子とともに絶縁基体よ
り剥離してしまうという欠点も有していた。
Although the metal layer made of silver is deposited on the bottom surface of the concave portion of the insulating base by baking, the bonding strength between the silver and the insulating base is very weak because the reactivity between the silver and the insulating base is very low. When the semiconductor element is attached by heating and melting the adhesive, the shape of the semiconductor element becomes large, and when the amount of the adhesive increases, the metal layer peels off from the insulating base together with the semiconductor element due to the tensile force of the adhesive. Had the disadvantage that

【0007】[0007]

【課題を解決するための手段】本考案は半導体素子を収
容するための凹部を有する絶縁基体と蓋体とから成る半
導体素子収納用パッケージにおいて、前記絶縁基体の凹
部底面に、銀に銅を0.3 乃至1.0 重量%、白金を0.2 重
量%以上含有させて成る金属層を層着させたことを特徴
とするものである。
According to the present invention, there is provided a semiconductor device housing package comprising a cover and an insulating base having a recess for housing a semiconductor element. A metal layer containing at least 1.0% by weight and at least 0.2% by weight of platinum.

【0008】[0008]

【実施例】次に本考案を添付図面に基づき詳細に説明す
る。図1 は本考案の半導体素子収納用パッケージの一実
施例を示し、1 はアルミナセラミックス等の電気絶縁材
料から成る絶縁基体、2 は同じく電気絶縁材料から成る
蓋体である。この絶縁基体1 と蓋体2 とで半導体素子3
を収容する容器が構成される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a package for accommodating a semiconductor device according to the present invention, wherein 1 is an insulating base made of an electrically insulating material such as alumina ceramics, and 2 is a lid made of the same electrically insulating material. The semiconductor element 3 is formed by the insulating base 1 and the lid 2.
Is configured.

【0009】前記絶縁基体1 及び蓋体2 にはそれぞれの
中央部に半導体素子3 を収容する空所を形成するための
凹部が設けてあり、絶縁基体1 の凹部1a底面には金属層
4 が層着されている。
The insulating base 1 and the lid 2 are provided with a concave portion for forming a space for accommodating the semiconductor element 3 at the center thereof, and a metal layer is formed on the bottom of the concave portion 1a of the insulating base 1.
4 is layered.

【0010】前記絶縁基体1 及び蓋体2 は従来周知のプ
レス成形法を採用することによって形成され、例えば絶
縁基体1 及び蓋体2 がアルミナセラミックスから成る場
合には図1 に示すような絶縁基体1 または蓋体2 に対応
した形状を有するプス型内にアルミナセラミックスの原
料粉末を充填させるとともに一定圧力を印加して成形
し、しかる後、成形品を約1500℃の温度で焼成すること
によって製作される。
The insulating substrate 1 and the lid 2 are formed by employing a conventionally known press molding method. For example, when the insulating substrate 1 and the lid 2 are made of alumina ceramic, the insulating substrate 1 and the lid 2 are formed as shown in FIG. The raw material powder of alumina ceramics is filled in a mold having the shape corresponding to 1 or lid 2 and molded by applying a certain pressure, and then the molded product is fired at a temperature of about 1500 ° C. Is done.

【0011】また前記絶縁基体1 の凹部1a底面に層着さ
せた金属層4 は、銀に銅を0.3 乃至1.0 重量%、白金を
0.2 重量%以上含有させた金属から成り、該金属層4 は
半導体素子3 を絶縁基体1 の凹部1a底面に取着する際の
下地金属として作用し、金属層4 上には半導体素子3 が
金、金 シリコン共晶半田等の接着材5 を介し取着され
る。
The metal layer 4 layered on the bottom surface of the concave portion 1a of the insulating base 1 has a silver content of 0.3 to 1.0% by weight of copper and platinum.
The metal layer 4 serves as a base metal when the semiconductor element 3 is attached to the bottom surface of the concave portion 1a of the insulating substrate 1, and the semiconductor element 3 is formed on the metal layer 4. Is attached via an adhesive 5 such as gold-silicon eutectic solder.

【0012】前記金属層4 は銀粉末に銅粉末を0.3 乃至
1.0 重量%、白金を0.2 重量%以上添加し、更にこれら
に有機溶剤、溶媒を添加混合して導電ペーストを得ると
ともに該導電ペーストを絶縁基体1 の凹部1a底面に滴下
させ、約25μm 以上の均一厚みに拡散させた後、約950
℃の高い温度で焼成することよって絶縁基体1 の凹部1a
底面に被着される。
The metal layer 4 is formed by adding copper powder to silver powder in an amount of 0.3 to 0.3.
1.0 wt% and platinum are added in an amount of 0.2 wt% or more, and an organic solvent and a solvent are further added and mixed to obtain a conductive paste. After spreading to thickness, about 950
By firing at a temperature as high as
It is attached to the bottom.

【0013】前記金属層4 はその内部に銅が0.3 乃至1.
0 重量%含有されていることから絶縁基体1 の凹部1a底
面に導電ペーストを滴下するとともに高温で焼成して金
属層4 を層着させる際、絶縁基体1 の凹部1a底面と金属
層4 の界面には酸化銅とアルミナのスピネル構造の反応
層が形成されることとなって金属層4 の絶縁基体1 に対
する層着強度が極めて強固なものとなる。そのため金属
層4 上に半導体素子3を接着材5 を加熱溶融させること
によって取着する場合、半導体素子3 の形状が大型化
し、接着材5 の量が多くなって該接着材5 による金属層
4 の引っ張り力が大きなものになったとしても金属層4
は半導体素子3 とともに絶縁基体1 より剥離することは
皆無となり、半導体素子3 を絶縁基体1 の凹部1a底面に
強固に取着させておくことが可能となる。
The metal layer 4 contains 0.3 to 1.
When the conductive paste is dropped onto the bottom surface of the concave portion 1a of the insulating substrate 1 and fired at a high temperature to deposit the metal layer 4 on the bottom surface of the insulating substrate 1, the interface between the concave portion 1a of the insulating substrate 1 and the metal layer 4 is contained. In this case, a reaction layer having a spinel structure of copper oxide and alumina is formed, and the adhesion strength of the metal layer 4 to the insulating base 1 becomes extremely strong. Therefore, when the semiconductor element 3 is attached to the metal layer 4 by heating and melting the adhesive 5, the shape of the semiconductor element 3 becomes large, the amount of the adhesive 5 increases, and the metal layer formed by the adhesive 5 becomes large.
Even if the tensile force of 4 becomes large, the metal layer 4
Does not peel off from the insulating substrate 1 together with the semiconductor element 3, and the semiconductor element 3 can be firmly attached to the bottom surface of the concave portion 1 a of the insulating substrate 1.

【0014】尚、前記金属層4 に含有させる銅はその含
有量が0.3 重量%未満であると金属層4 と絶縁基体1 の
凹部1a底面との界面に形成される反応層( 酸化銅とアル
ミナのスピネル構造の反応層) の量が少なくなって金属
層4 を絶縁基体1 の凹部1a底面に強固に層着することが
できなくなり、また銅の含有量が1.0 重量%を越えると
金属層4 の表面に銅が析出して金属層4 上に半導体素子
3 を強固に取着できなくなる。従って、金属層4 に含有
させる銅はその含有量が0.3 乃至1.0 重量%の範囲に特
定される。
If the content of copper contained in the metal layer 4 is less than 0.3% by weight, a reaction layer (copper oxide and alumina) formed at the interface between the metal layer 4 and the bottom surface of the concave portion 1a of the insulating substrate 1 is formed. The reaction layer having a spinel structure), the metal layer 4 cannot be firmly deposited on the bottom surface of the concave portion 1a of the insulating base 1, and if the copper content exceeds 1.0% by weight, the metal layer 4 Deposits on the surface of the semiconductor layer on the metal layer 4
3 cannot be firmly attached. Therefore, the content of copper contained in the metal layer 4 is specified in the range of 0.3 to 1.0% by weight.

【0015】また前記金属層4 には白金が0.2 重量%以
上含有されており、該白金は金属層4 の表面が酸化され
るのを有効に防止する作用を為す。
The metal layer 4 contains 0.2% by weight or more of platinum, and the platinum has an effect of effectively preventing the surface of the metal layer 4 from being oxidized.

【0016】前記白金を含有する金属層4 はその白金の
作用によって表面に酸化物膜が形成されることは殆どな
く、その結果、金属層4 上に半導体素子3 を接着材5 を
加熱溶融させることによって取着する際、金属層4 と接
着層5 とを接合強度を大として接合させることができ、
半導体素子3 を金属層4 上に強固に取着することが可能
となる。
An oxide film is hardly formed on the surface of the metal layer 4 containing platinum by the action of the platinum. As a result, the semiconductor element 3 is melted on the metal layer 4 by heating the adhesive 5. By doing so, it is possible to join the metal layer 4 and the adhesive layer 5 with high joining strength,
The semiconductor element 3 can be firmly attached on the metal layer 4.

【0017】尚、前記金属層4 に含有させる白金はその
含有量が0.2 重量%未満であると金属層4 の表面に短時
間に酸化物膜が形成されて金属層4 上に半導体素子3 を
強固に取着できなくなる。従って、前記金属層4 に含有
される白金はその含有量が0.2 重量%以上に特定され、
製品のコストを考慮すると0.2 〜2.0 重量%の範囲とす
るのが良い。
If the content of platinum contained in the metal layer 4 is less than 0.2% by weight, an oxide film is formed on the surface of the metal layer 4 in a short time, and the semiconductor element 3 is formed on the metal layer 4. It cannot be firmly attached. Therefore, the content of platinum contained in the metal layer 4 is specified to be 0.2% by weight or more,
Considering the cost of the product, the content is preferably in the range of 0.2 to 2.0% by weight.

【0018】また前記金属層4 に含有される銅及び白金
はその粒径を銀の粒径に対し10〜30% 程度としておく
と、銅及び白金が銀の粉末粒子間に均等に分散し、その
結果、金属層4 を絶縁基体1 の凹部1a底面により強固に
層着させることができるとともに金属層4 表面に酸化物
膜が形成されるのをより有効に防止することができる。
If the particle size of copper and platinum contained in the metal layer 4 is set to about 10 to 30% with respect to the particle size of silver, copper and platinum are uniformly dispersed between silver powder particles, As a result, the metal layer 4 can be more firmly deposited on the bottom surface of the concave portion 1a of the insulating base 1, and the formation of an oxide film on the surface of the metal layer 4 can be more effectively prevented.

【0019】更に前記金属層4 は取着する半導体素子3
の寸法が6.0mm ×8.0mm 程度の大きなものと成って絶縁
基体1 に設けた凹部1aの底面積が80mm2 以上となったと
きその厚みを25μm 以上の厚いものとしておくと半導体
素子3 を絶縁基体1 の凹部1a底面に被着させた金属層4
上に接着材5 を介して取着する際、金属層4 が半導体素
子3 と絶縁基体1 との熱膨張係数の相違に起因して発生
する熱応力を該金属層4 が変形することによって吸収
し、半導体素子3 に半導体素子3 と絶縁基体1 との間に
発生する熱応力によってクラックや割れ等が生じるのを
有効に防止することもできる。従って、金属層4 は取着
する半導体素子3 の寸法が6.0mm ×8.0mm程度の大きな
ものと成って絶縁基体1 に設けた凹部1aの底面積が80mm
2 以上となったときその厚みを25μm 以上の厚いものと
しておくことが好ましい。
The metal layer 4 further comprises a semiconductor element 3 to be attached.
When the bottom area of the concave portion 1a provided in the insulating base 1 is 80 mm 2 or more, the semiconductor element 3 is insulated if the thickness is set to 25 μm or more when the size of the concave portion 1a is as large as about 6.0 mm × 8.0 mm. Metal layer 4 adhered to the bottom of concave portion 1a of base 1
When the metal layer 4 is attached via the adhesive 5, the metal layer 4 absorbs the thermal stress caused by the difference in the coefficient of thermal expansion between the semiconductor element 3 and the insulating base 1 by deforming the metal layer 4. However, it is possible to effectively prevent the semiconductor element 3 from being cracked or broken due to thermal stress generated between the semiconductor element 3 and the insulating base 1. Therefore, the metal layer 4 has a large dimension of the semiconductor element 3 to be attached, which is about 6.0 mm × 8.0 mm, and the bottom area of the concave portion 1 a provided in the insulating base 1 is 80 mm.
When the thickness is 2 or more, it is preferable to set the thickness to 25 μm or more.

【0020】また更に前記金属層4 はそれを構成する銀
の結晶粒径を焼成温度を約950 ℃の若干高めとすること
によって7.0 乃至14.0μm の大きさとすると銀結晶間の
間隙が少なくなるとともに金属層4 の表面粗さが中心線
平均粗さRaでRa=0.55 μm 程度の滑らかなものとなり、
その結果、金属層4 上に接着材5 を介して半導体素子3
を取着する際、接着材5 の金属層4 上での拡がりが極め
て良くなり、半導体素子3 を金属層4 に極めて強固に取
着することが可能となる。従って、金属層4 はそれを構
成する銀の結晶粒径を7.0 乃至14.0μm の大きさとして
おくことが好ましい。
Further, when the metal layer 4 is made to have a crystal grain size of 7.0 to 14.0 μm by slightly increasing the crystal grain size of silver constituting the metal layer to a firing temperature of about 950 ° C., the gap between silver crystals is reduced, and The surface roughness of the metal layer 4 becomes smooth with a center line average roughness Ra of about Ra = 0.55 μm,
As a result, the semiconductor element 3 is placed on the metal layer 4 via the adhesive 5.
When attaching, the spread of the adhesive 5 on the metal layer 4 becomes extremely good, and the semiconductor element 3 can be attached to the metal layer 4 very firmly. Therefore, it is preferable that the metal layer 4 has a crystal grain size of silver constituting it of 7.0 to 14.0 μm.

【0021】前記絶縁基体1 及び蓋体2 にはまたその相
対向する各々の主面に封止用の低融点ガラス層6a、6bが
予め被着形成されており、該絶縁基体1 及び蓋体2 の各
々に被着されている封止用の低融点ガラス層6a、6bを加
熱溶融させ、一体化させることにより絶縁基体1 と蓋体
2 とから成る容器内部に半導体素子3 を気密に封止す
る。前記絶縁基体1 及び蓋体2 の相対向する主面に被着
される封止用の低融点ガラス層6a、6bは、例えば酸化鉛
75.0重量%、酸化チタン9.0 重量%、酸化ホウ素7.5 重
量%、酸化亜鉛2.0 重量%等のガラスから成り、該ガラ
ス粉末に適当な有機溶剤、溶媒を添加混合して得たガラ
スペーストを従来周知のスクリーン印刷等の厚膜手法を
採用することにより絶縁基体1 及び蓋体2 の相対向する
各々の主面に被着される。
The insulating base 1 and the lid 2 are also provided with sealing low-melting glass layers 6a and 6b on their opposing main surfaces in advance. The insulating low-melting glass layers 6a and 6b attached to each of 2 are heated and melted and integrated to form the insulating base 1 and the lid.
The semiconductor element 3 is hermetically sealed in the container formed by the steps 2 and 3. The sealing low-melting glass layers 6a and 6b that are adhered to the opposing main surfaces of the insulating base 1 and the lid 2 are made of, for example, lead oxide.
A glass paste obtained by adding a suitable organic solvent and a solvent to the glass powder and mixing the glass paste with a glass paste of 75.0% by weight, 9.0% by weight of titanium oxide, 7.5% by weight of boron oxide, and 2.0% by weight of zinc oxide. By employing a thick film technique such as screen printing, the insulating substrate 1 and the lid 2 are attached to the opposing main surfaces of the cover 2 and the lid 2, respectively.

【0022】尚、前記封止用の低融点ガラス層6a、6bは
その熱膨張係数を絶縁基体1 及び蓋体2 の熱膨張係数に
近似した値にしておくと絶縁基体1 と蓋体2 とを封止用
低融点ガラス層6a、6bを介して接合し、容器を気密に封
止する際、絶縁基体1 及び蓋体2 と封止用低融点ガラス
層6a、6bとの間には両者の熱膨張係数の相違に起因する
熱応力が発生することは殆どなく、絶縁基体1 と蓋体2
とを封止用低融点ガラス層6a、6bを介し強固に接合する
ことが可能となる。従って、封止用低融点ガラス層6a、
6bはその熱膨張係数を絶縁基体1 及び蓋体2 の熱膨張係
数に合わせておくことが好ましい。
If the thermal expansion coefficients of the low melting glass layers 6a and 6b for sealing are set to values close to the thermal expansion coefficients of the insulating base 1 and the lid 2, the insulating base 1, the lid 2 When the container is air-tightly sealed through the low melting point glass layers 6a and 6b for sealing, the insulating base 1 and the lid 2 and the low melting point glass layers 6a and 6b Almost no thermal stress occurs due to the difference in thermal expansion coefficient between the insulating base 1 and the lid 2.
Can be firmly joined via the low-melting glass layers 6a and 6b for sealing. Therefore, the sealing low melting point glass layer 6a,
It is preferable that the thermal expansion coefficient of 6b is adjusted to the thermal expansion coefficients of the insulating base 1 and the lid 2.

【0023】また前記絶縁基体1 と蓋体2 との間には導
電性材料、例えばコバール(Fe-Ni-C合金) や42アロイ(F
e-Ni合金) 等の金属から成る外部リード端子7 が配され
ており、該外部リード端子7 は半導体素子3 の各電極が
ボンディングワイヤ8 を介して電気的に接続され、外部
リード端子7 を外部電気回路に接続することによって半
導体素子3 は外部電気回路と接続されることとなる。
A conductive material such as Kovar (Fe--Ni--C alloy) or 42 alloy (F) is provided between the insulating base 1 and the lid 2.
An external lead terminal 7 made of a metal such as e-Ni alloy) is provided, and the external lead terminal 7 is electrically connected to each electrode of the semiconductor element 3 via a bonding wire 8. By connecting to the external electric circuit, the semiconductor element 3 is connected to the external electric circuit.

【0024】前記外部リード端子7 は、絶縁基体1 と蓋
体2 とから成る容器を封止用の低融点ガラス層6a、6bを
溶融一体化させて気密封止する際に同時に絶縁基体1 と
蓋体2 の間に取着固定される。
The external lead terminals 7 are simultaneously sealed with the insulating base 1 when the container comprising the insulating base 1 and the lid 2 is hermetically sealed by melting and integrating the low-melting glass layers 6a and 6b for sealing. It is attached and fixed between the lids 2.

【0025】尚、前記外部リード端子7 は外部電気回路
との電気的導通を良好とするために、また酸化腐食する
のを有効に防止するためにその外表面にニッケル、金等
の良導電性で、且つ耐蝕性に優れた金属を1.0 乃至20.0
μm の厚みにメッキにより層着させておくことが好まし
い。
The external lead terminal 7 has a good conductivity such as nickel, gold or the like on its outer surface in order to improve the electrical continuity with an external electric circuit and to effectively prevent oxidation and corrosion. 1.0 to 20.0 of metal with excellent corrosion resistance
It is preferable that the layer is deposited by plating to a thickness of μm.

【0026】かくしてこの半導体素子収納用パッケージ
によれば、絶縁基体1 に設けた凹部1a底面の金属層4 上
に金、金 シリコン共晶半田等から成る接着材5 を介し
て半導体素子3 を取着固定するとともに該半導体素子3
の各電極をボンディングワイヤ8 により外部リード端子
7 に接続させ、しかる後、絶縁基体1 と蓋体2 とをその
両者の相対向する主面に予め被着させておいた封止用低
融点ガラス層6a、6bを溶融一体化させることによって接
合すると絶縁基体と蓋体とから成る容器内部に半導体素
子3 が気密に封止されて最終製品としての半導体装置と
なる。
Thus, according to the semiconductor device housing package, the semiconductor device 3 is mounted on the metal layer 4 on the bottom surface of the concave portion 1a provided on the insulating base 1 via the adhesive 5 made of gold, gold silicon eutectic solder or the like. Attach and fix the semiconductor element 3
External terminals with bonding wires 8
7, and then the insulating base 1 and the lid 2 are fused and integrated with the sealing low-melting glass layers 6a and 6b, which are previously adhered to the opposing main surfaces thereof. Upon joining, the semiconductor element 3 is hermetically sealed inside a container formed of an insulating base and a lid, and a semiconductor device as a final product is obtained.

【0027】尚、本考案は上述の実施例に限定されるも
のではなく、本考案の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば低融点ガラスによって絶
縁基体と蓋体とから成る容器を気密封止するガラス封止
型の半導体素子収納用パッケージの他に複数枚の未焼成
セラミックシートを積層し、焼結一体化させて成るマル
チレイヤーの半導体素子収納用パッケージにも適用可能
である。
It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. In addition to a glass-sealed semiconductor element storage package that hermetically seals a container made of It is possible.

【0028】[0028]

【考案の効果】本考案の半導体素子収納用パッケージに
よれば、パッケージの容器を構成する絶縁基体の凹部底
面に銀に銅を0.3 乃至1.0 重量%、白金を0.2 重量%以
上含有させて成る金属層を層着させたことから金属層を
絶縁基体の凹部底面に層着させる際その層着の強度を極
めて強固とするとともに金属層表面に酸化物膜が形成さ
れるのを有効に防止して金属層上に半導体素子を極めて
強固に取着することが可能となる。
According to the package for housing a semiconductor element of the present invention, a metal comprising 0.3 to 1.0% by weight of copper and 0.2% by weight or more of platinum in silver on the bottom surface of a concave portion of an insulating base constituting a package container. When the metal layer is layered on the bottom of the concave portion of the insulating substrate, the strength of the layering is extremely increased and the oxide film is effectively prevented from being formed on the surface of the metal layer. The semiconductor element can be very firmly attached on the metal layer.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本考案の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view illustrating an embodiment of a package for housing a semiconductor device according to the present invention;

【符号の説明】[Explanation of symbols]

1・・・絶縁基体 1a・・凹部 2・・・蓋体 3・・・半導体素子 4・・・金属層 5・・・接着材 7・・・外部リード端子 DESCRIPTION OF SYMBOLS 1 ... Insulating base 1a ... Depression 2 ... Lid 3 ... Semiconductor element 4 ... Metal layer 5 ... Adhesive 7 ... External lead terminal

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭60−121731(JP,A) 特開 平2−238640(JP,A) 特開 平3−19246(JP,A) 特開 昭63−229843(JP,A) 特開 昭63−54755(JP,A) 特開 平2−7534(JP,A) 特開 平4−323853(JP,A) 特開 昭56−167339(JP,A) 特開 昭61−150352(JP,A) 特開 昭60−189954(JP,A) ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-121731 (JP, A) JP-A-2-238640 (JP, A) JP-A-3-19246 (JP, A) JP-A-63-1988 229843 (JP, A) JP-A-63-54755 (JP, A) JP-A-2-7534 (JP, A) JP-A-4-323385 (JP, A) JP-A-56-167339 (JP, A) JP-A-61-150352 (JP, A) JP-A-60-189954 (JP, A)

Claims (1)

(57)【実用新案登録請求の範囲】(57) [Scope of request for utility model registration] 【請求項1】半導体素子を収容するための凹部を有する
絶縁基体と蓋体とから成る半導体素子収納用パッケージ
において、前記絶縁基体の凹部底面に、銀に銅を0.3 乃
至1.0 重量%、白金を0.2 重量%以上含有させて成る金
属層を層着させたことを特徴とする半導体素子収納用パ
ッケージ。
1. A semiconductor device housing package comprising a cover and an insulating base having a recess for housing a semiconductor element, wherein 0.3 to 1.0% by weight of copper and platinum are coated on the bottom of the recess of the insulating base. A package for accommodating a semiconductor element, wherein a metal layer containing 0.2% by weight or more is deposited.
JP1991038422U 1991-05-28 1991-05-28 Package for storing semiconductor elements Expired - Fee Related JP2538845Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1991038422U JP2538845Y2 (en) 1991-05-28 1991-05-28 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1991038422U JP2538845Y2 (en) 1991-05-28 1991-05-28 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH04131947U JPH04131947U (en) 1992-12-04
JP2538845Y2 true JP2538845Y2 (en) 1997-06-18

Family

ID=31919931

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1991038422U Expired - Fee Related JP2538845Y2 (en) 1991-05-28 1991-05-28 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP2538845Y2 (en)

Also Published As

Publication number Publication date
JPH04131947U (en) 1992-12-04

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