JP3021792B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an interlayer insulating film for a multilayer wiring.

[0002]

2. Description of the Related Art FIG. 2 is a sectional view showing an example of a conventional semiconductor device.

As shown in FIG. 2, a silicon oxide film 2 having a thickness of 0.8 μm is formed on a silicon substrate 1, and a lower layer of aluminum having a thickness of 0.5 μm is formed on the silicon oxide film 2. The wiring 3 is formed. Next, a first silicon oxide film 4 is formed to a thickness of 0.4 μm on the surface including the aluminum wiring 3, a coating film 4 is applied thereon, and the silicon oxide film 4 is etched back. Only in the recess of
The upper surface is flattened by etching back so that the coating film 7 remains. Next, a second silicon oxide film 6 is deposited on the surface including the coating film 7. Next, the silicon oxide films 6 and 4 above the aluminum wiring 3 are isotropically etched and anisotropically etched in order to form a contact hole 9 and to connect with the lower aluminum wiring layer 3 through the contact hole 9. The upper aluminum wiring 8 to be formed is formed on the silicon oxide film 6 to a thickness of 1.0 μm.

[0004]

In this conventional semiconductor device, the shape of the through hole is tapered at the top by combining isotropic etching and anisotropic etching so that the aluminum wiring in the upper layer does not break. Although provided, if the thickness of the interlayer insulating film is increased so as to reduce the parasitic capacitance between the lower aluminum wiring and the upper aluminum wiring, a long time is applied so that the upper aluminum wiring is not disconnected. Isotropic etching is required. But,
Since the etching rate of the coating film 7 with respect to the hydrofluoric acid-based etching solution is very fast, there is a problem that the coating film is etched to form a cavity 10 and disconnection of the upper wiring, as shown in FIG. .

[0005]

According to the present invention, there is provided a semiconductor device comprising:
A lower wiring provided on the semiconductor substrate, a first interlayer insulating film provided on a surface including the lower wiring, a coating film provided only in a concave portion on the first interlayer insulating film and having a flat upper surface, A second interlayer insulating film provided on the surface including the coating film; and an upper layer connected to the lower wiring via a through hole formed by opening the first and second interlayer insulating films on the lower wiring. The first and second interlayer insulating films including a lower surface and an upper surface of the coating film and provided between the first interlayer insulating film and the second interlayer insulating film. Also has a third interlayer insulating film having a low etching rate with respect to a hydrofluoric acid-based etching solution.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention.

As shown in FIG. 1, a 0.8 μm-thick silicon oxide film 2 is formed on a silicon substrate 1, and a lower aluminum wiring 3 is selectively formed on the silicon oxide film 2. Next, CV is applied to the surface including the aluminum wiring 3.
A first silicon oxide film 4 mainly composed of SiO ₂ is deposited to a thickness of 0.4 μm by the method D, and then the composition ratio of silicon and oxygen is changed from 1: 2 to 1: 1 on the silicon oxide film 4. 1
The silicon oxide film 5 mainly composed of SiO having a low etching rate with respect to a hydrofluoric acid-based etching solution is changed to 0.2 μm.
m. Here, the etching rate of the silicon oxide film 5 is lower by about 30% than that of the silicon oxide film 4. Next, an SOG film 7 is formed on the silicon oxide film 5 and etched back, and the upper surface is planarized so that the SOG film 7 remains only in the concave portions. Next, the silicon oxide film 5a having the same composition as the silicon oxide film 5 is
A silicon oxide film 6 mainly composed of SiO ₂ is deposited on the silicon oxide film 5a to a thickness of 0.4 μm. Next, the silicon oxide films 6, 5a, 5, 4 on the aluminum wiring 3 are sequentially etched to form contact through holes 9. This through hole 9 is etched to a middle of the silicon oxide film 5a having a low etching rate with respect to a hydrofluoric acid-based etching solution, and then anisotropically etched by RIE or the like.
The cups 5 and 4 are sequentially etched to form cup-shaped through holes 9. Next, an aluminum layer is deposited to a thickness of 1.0 μm on the surface including the through-hole 9 and patterned to form an upper aluminum wiring 8 connected to the aluminum wiring 3.

In this embodiment, the aluminum wiring 8 in the through hole 9 is formed while forming a thicker interlayer insulating film than in the prior art.
Can be prevented from being disconnected.

Here, a BSG film or a BPSG film containing boron may be used instead of the silicon oxide films 5 and 5a.
There is an advantage of preventing cracks that easily occur in the OG film.

[0011]

As described above, according to the present invention, a third interlayer insulating film having a low etching rate with respect to a hydrofluoric acid-based etchant is provided between the first and second interlayer insulating films to cover the coating film. This has the effect of preventing the coating film from being etched in the etching step for forming the contact through-hole, and preventing the disconnection of the wiring even if a thick interlayer insulating film is formed.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip showing an example of a conventional semiconductor device.

FIG. 3 is a cross-sectional view of a semiconductor chip for describing a problem of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2,4,5a, 5b, 6 Silicon oxide film 3,8 Aluminum wiring 7 Coating film 9 Through hole 10 Cavity

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768

Claims (2)

(57) [Claims] A first wiring provided on a semiconductor substrate, a first interlayer insulating film provided on a surface including the lower wiring, and a recess provided on the first interlayer insulating film to flatten an upper surface; And a second interlayer insulating film provided on a surface including the coating film, and a lower layer via a through hole provided by opening the first and second interlayer insulating films on the lower wiring. In a semiconductor device having an upper layer wiring connected to a wiring, the first and second layers include a lower surface and an upper surface of the coating film and are provided between the first interlayer insulating film and the second interlayer insulating film.
A third interlayer insulating film having a lower etching rate with respect to a hydrofluoric acid-based etchant than the third interlayer insulating film. 2. The semiconductor device according to claim 1, wherein said third interlayer insulating film is a silicon oxide film containing boron.