JPH0611043B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0611043B2 JPH0611043B2 JP62041883A JP4188387A JPH0611043B2 JP H0611043 B2 JPH0611043 B2 JP H0611043B2 JP 62041883 A JP62041883 A JP 62041883A JP 4188387 A JP4188387 A JP 4188387A JP H0611043 B2 JPH0611043 B2 JP H0611043B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- interlayer insulating
- layer
- forming
- layer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体装置の製造方法に関し、特にアルミ多層
配線における層間絶縁膜の形成方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming an interlayer insulating film in an aluminum multi-layer wiring.
（従来の技術） 従来、アルミ多層配線半導体装置における層間絶縁膜に
は耐湿性が重視される場合はシリコン窒化膜（Si3N4）
が、また、配線の層間容量が問題となる場合はシリコン
酸化膜（SiO2）或いはポリミィド系の有機性樹脂膜が使
用される。(Prior Art) Conventionally, a silicon nitride film (Si 3 N 4 ) is used for an interlayer insulating film in an aluminum multilayer wiring semiconductor device when moisture resistance is important.
However, if the inter-layer capacitance of the wiring becomes a problem, a silicon oxide film (SiO 2 ) or a polyimide-based organic resin film is used.
（発明が解決しようとする問題点） ところで、この層間絶縁膜の全てに要求される材質上の
条件は、良好な平坦面が容易に得られること、スルー・
ホール形成のための加工が容易であること、耐湿性にす
ぐれていることおよび誘電率が小さいことなどである
が、一般にはこれらの全てを満足できるものはないので
通常２つ以上を組合せた複合膜が採用される。例えば、
リフローし難いシリコン窒化膜の凹所をシリカ塗布膜ま
たは有機シロキ酸系の樹脂溶液で埋めることによって平
坦性を確保しそのすぐれた耐湿性を活かすよう工夫され
る。また、平坦性に限って見ればポリミィド系の有機性
樹脂膜などはきわめて良好な絶縁膜であるが耐湿性に問
題があるので場合により他の膜質のものと適宜複合され
る。(Problems to be Solved by the Invention) By the way, the material conditions required for all the interlayer insulating films are that a good flat surface can be easily obtained, and
Although it is easy to process for hole formation, has excellent moisture resistance, and has a low dielectric constant, etc. Generally, there is no one that can satisfy all of these, so it is usually a composite that combines two or more. Membrane is adopted. For example,
By burying the recess of the silicon nitride film, which is difficult to reflow, with a silica coating film or an organic siloic acid-based resin solution, the flatness is secured and the excellent moisture resistance is utilized. In addition, if viewed only in terms of flatness, a polyimide-based organic resin film or the like is an extremely good insulating film, but it has a problem in moisture resistance, so it may be appropriately combined with another film having a different film quality.
しかしながら、この複合膜は層内に有機性樹脂膜を含む
場合であるとスルー・ホールを形成した際この開口部に
有機性樹脂膜を露出せしめることとなるのでスルー・ホ
ールの耐湿性に問題が生じるようになる。従って、この
ような場合には有機性樹脂膜はアルミ配線間の段差を埋
めるだけの使用に止どめアルミ配線上には形成しないよ
う工夫される。また、シリカ塗布膜の如き無機質でシリ
コン窒化膜の平坦化をはかった場合ではスルー・ホール
の形成上に大きな問題を生じることはないが、アルミ配
線間の段差平坦化能力は有機性樹脂膜程ではないので特
に第１層アルミ配線の配線間隔が微細になると第２層ア
ルミ配線に断線事故が発生するようになる。この傾向は
半導体装置の集積度および微細化の進展と共に有機性樹
脂膜を用いた場合でも例外なく一層強まっており微細化
高集積度半導体装置の製造をきわめて困難ならしめてい
る。However, in the case where this composite film includes an organic resin film in the layer, when the through hole is formed, the organic resin film is exposed in this opening, so that there is a problem in moisture resistance of the through hole. Will occur. Therefore, in such a case, the organic resin film is devised so that it is used only to fill the step between the aluminum wirings and is not formed on the aluminum wirings. In addition, when an inorganic material such as a silica coating film is used to planarize the silicon nitride film, no major problem occurs in forming the through hole, but the ability to planarize the level difference between the aluminum wirings is as high as that of the organic resin film. Therefore, especially if the wiring interval of the first layer aluminum wiring becomes fine, a disconnection accident will occur in the second layer aluminum wiring. This tendency is intensified even if an organic resin film is used with the progress of integration and miniaturization of semiconductor devices, which makes it extremely difficult to manufacture miniaturized high integration semiconductor devices.
（発明の目的） 本発明の目的は、上記の情況に鑑み、きわめて微細間隔
のアルミ配線段差に良好な平坦性を与えると共にアルミ
配線上に耐湿性のスルー・ホールを容易に形成し得る複
合層間絶縁膜を備えた半導体装置の製造方法を提供する
ことである。(Object of the Invention) In view of the above circumstances, an object of the present invention is to provide a composite interlayer capable of forming a moisture-resistant through hole on an aluminum wiring while providing good flatness to an aluminum wiring step with extremely fine spacing. It is an object of the present invention to provide a method for manufacturing a semiconductor device including an insulating film.
（問題点を解決するための手段） 前記目的を達成するため、本発明に係る半導体装置の製
造方法は、第１層配線形成工程と、第１の層間絶縁膜形
成工程と、第２の層間絶縁膜形成工程と、第２層間絶縁
膜加工工程と、平坦化処理工程と、第３の層間絶縁膜形
成工程と、第２層配線形成工程とを有する半導体装置の
製造方法であって、 第１層配線形成工程は、半導体基板の絶縁膜上に複数の
第１層配線を形成する工程であり、 第１の層間絶縁膜形成工程は、露出した前記第１層配線
の表面と、前記第１層配線間の露出した絶縁膜の表面と
を連続的に被覆する第１の層間絶縁膜を形成する工程で
あり、 第２の層間絶縁膜形成工程は、前記第１の層間絶縁膜上
に、第１の層間絶縁膜とは異なる材料の第２の層間絶縁
膜を形成する工程であり、 第２層間絶縁膜加工工程は、前記第２の層間絶縁膜を異
方性エッチングすることにより、該第２の層間絶縁膜を
部分的に除去し、第１層配線間に形成された凹所の内側
壁部にのみ第２の層間絶縁膜をテーパ状に残留させ、そ
れ以外の領域での第１の層間絶縁膜を外部に露出させる
工程であり、 平坦化処理工程は、前記第１層配線間の凹所内に絶縁膜
を第１層配線の段差分に相当する深さまで塗布法により
充填し、絶縁膜全体の高さを平坦化する工程であり、 第３の層間絶縁膜形成工程は、平坦化された前記絶縁膜
上に第３の層間絶縁膜を平坦に形成する工程であり、 第２層配線形成工程は、前記第３の層間絶縁膜上に第２
層配線を形成する工程であり、 第２層配線は、前記絶縁膜を貫通して形成されたスルー
ホールを介して第１層配線に適宜接続されるものであ
る。(Means for Solving Problems) In order to achieve the above-mentioned object, a method for manufacturing a semiconductor device according to the present invention includes a first layer wiring forming step, a first interlayer insulating film forming step, and a second interlayer insulating film forming step. A method of manufacturing a semiconductor device, comprising: an insulating film forming step, a second interlayer insulating film processing step, a flattening processing step, a third interlayer insulating film forming step, and a second layer wiring forming step. The first-layer wiring forming step is a step of forming a plurality of first-layer wirings on the insulating film of the semiconductor substrate, and the first interlayer insulating-film forming step includes the exposed surface of the first-layer wiring and the first layer wiring. The step of forming a first interlayer insulating film continuously covering the exposed surface of the insulating film between the first-layer wirings, and the step of forming the second interlayer insulating film is performed on the first interlayer insulating film. , A step of forming a second interlayer insulating film made of a material different from that of the first interlayer insulating film, In the interlayer insulating film processing step, the second interlayer insulating film is anisotropically etched to partially remove the second interlayer insulating film, and inside the recess formed between the first layer wirings. The second interlayer insulating film remains in a tapered shape only on the wall portion, and the first interlayer insulating film in the other regions is exposed to the outside. Is a step of filling the insulating film in the concave portion to a depth corresponding to the step difference of the first layer wiring by a coating method to flatten the height of the entire insulating film, and the third interlayer insulating film forming step is a flattening step. Forming a third interlayer insulating film evenly on the patterned insulating film, and forming the second interlayer wiring on the third interlayer insulating film.
This is a step of forming a layer wiring, and the second layer wiring is appropriately connected to the first layer wiring through a through hole formed through the insulating film.
（作用） 本発明においては、第１層アルミ配線導体を含む基板全
面はまず無機絶縁物からなる第１の層間絶縁膜で被覆さ
れ、ついでこの基板全面に厚膜形成した無機絶縁膜の異
方性エッチング工程によってアルミ配線導体の側壁面の
みを被覆するテーパ状の第２の層間絶縁膜が形成され
る。ここで、従来技術に做って第１および第２の層間絶
縁膜には無機または有機の絶縁膜を用いた塗布法による
第１の平坦化工程が行なわれ、更にアルミ配線導体の上
面からこの塗布膜を除去する第２の平坦化工程が行なわ
れた後これら全面に第３の無機層間絶縁膜が形成され
る。(Function) In the present invention, the entire surface of the substrate including the first-layer aluminum wiring conductor is first covered with the first interlayer insulating film made of an inorganic insulating material, and then the anisotropically-formed anisotropic inorganic insulating film is formed on the entire surface of the substrate. By the conductive etching process, a tapered second interlayer insulating film that covers only the side wall surface of the aluminum wiring conductor is formed. Here, in comparison with the prior art, the first and second interlayer insulating films are subjected to a first planarization step by a coating method using an inorganic or organic insulating film, and further from the upper surface of the aluminum wiring conductor. After the second flattening step of removing the coating film is performed, a third inorganic interlayer insulating film is formed on these entire surfaces.
本発明によれば、第１および第２の無機層間絶縁膜には
２度の平坦化工程が行なわれるので第３の無機層間絶縁
膜を含めてもきわめて平坦性に富む層間絶縁膜の構造を
与える。また、第２の層間絶縁膜はアルミ配線間を下か
ら上に向かって拡がる形状で埋めるよう形成されるので
配線間隔が微細な場合であっても無機または有機の絶縁
膜を基板面に達する深さまで充分進入せしめるよう働
く。すなわち、塗布法による平坦化効果を著しく高める
よう機能する。更にアルミ配線導体の上表面には比較的
薄い第１の無機層間絶縁膜と厚い第３の無機層間絶縁膜
が積層されているのみであるのできわめて良好な耐湿性
とカバレージ性とを備えたスルー・ホールを容易に形成
せしめ得る。以下図面を用いて詳細に説明する。According to the present invention, since the first and second inorganic interlayer insulating films are subjected to the flattening step twice, even if the third inorganic interlayer insulating film is included, the structure of the interlayer insulating film having an extremely high flatness can be obtained. give. Further, since the second interlayer insulating film is formed so as to fill the space between the aluminum wirings in a shape expanding from the bottom to the top, even if the wiring spacing is fine, the depth of reaching the substrate surface with the inorganic or organic insulating film is large. By the way, it works so that it can enter sufficiently. That is, it functions to remarkably enhance the flattening effect by the coating method. Further, since the relatively thin first inorganic interlayer insulating film and the thick third inorganic interlayer insulating film are laminated on the upper surface of the aluminum wiring conductor, the through hole having extremely good moisture resistance and coverage is provided. -Hole can be easily formed. The details will be described below with reference to the drawings.
（実施例） 第１図(a)〜(d)は本発明の一実施例を示す工程順序図で
ある。本実施例によれば半導体基板１のフィールド絶縁
膜２上には第１図(a)に示す如く第１層アルミ配線３が
通常の技術に従いまずパターニング形成され、ついで第
１および第２の無機層間絶縁膜４および５がそれぞれ被
覆形成される。ここで、第１の無機層間絶縁膜４は比較
的薄い（例えば0.１〜0.５μｍ）のシリコン窒化膜で形
成されることが好ましく、また、第２の無機層間絶縁膜
５の材質にはシリコン酸化膜が適当し且つこの段階では
第１のアルミ配線３の膜厚（通常0.５〜1.５μｍ）より
も厚い膜厚に形成される。ついでこの第２の無機層間絶
縁膜５は下層に位置する第１の無機層間絶縁膜４の被覆
面が露出するまで異方性エッチングされる。このエッチ
ングには例えばリアクティブ・イオン・エッチング技術
(RIE)を用いることができる。この異方性エッチング段
階が終わると第２の無機層間絶縁膜５は第１のアルミ配
線３の側壁面のみを被覆するテーパ形状に形成される
（第１図（ｂ）参照）。ここで、この第１および第２の
無機層間絶縁膜４および５は従来技術に做いシリカまた
はシロキ酸系ポリマー等の無機または有機の絶縁膜６の
塗布法により平坦化される。この際、アルミ配線間を埋
める第２の無機層間絶縁膜５は下から上に拡がるテーパ
状を形成しているのでこの塗布膜は基板面に達する深さ
まで充分進入する。例えば配線間隔が1.０μｍ程度に微
細化された場合でもこの配線段差は充分平坦化される。
ついでこの塗布膜を第１層アルミ配線３の上面を被覆す
る第１の無機層間絶縁膜４の被覆面が再び露出するまで
等方性エッチングしたうえ第３の無機層間絶縁膜７をシ
リコン窒化膜を用いて形成すれば第１図(c)の構造を得
る。この場合第１および第２の無機層間絶縁膜４および
５は第１および第２の平坦化工程で充分平坦化されてい
るので第３の無機層間絶縁膜７の平坦度もまたきわめて
良好である。従って、この上面には第２層アルミ配線８
を第１図(d)に示す如く容易に形成することができ、ま
た、アルミ配線３上には耐湿性およびカバレージ性のき
わめて良好なスルー・ホール９を形成することができる
ので上層配線に断線事故発生の憂い少なき多層アルミ配
線半導体装置を高密度に信頼性高く且つ歩留りより生産
することができる。(Embodiment) FIGS. 1A to 1D are process sequence diagrams showing an embodiment of the present invention. According to the present embodiment, the first layer aluminum wiring 3 is first formed by patterning on the field insulating film 2 of the semiconductor substrate 1 according to a usual technique as shown in FIG. 1 (a), and then the first and second inorganic layers are formed. Interlayer insulating films 4 and 5 are formed by coating. Here, the first inorganic interlayer insulating film 4 is preferably formed of a relatively thin (for example, 0.1 to 0.5 μm) silicon nitride film, and the second inorganic interlayer insulating film 5 is made of a material. Is a silicon oxide film, and at this stage, it is formed to have a thickness larger than that of the first aluminum wiring 3 (usually 0.5 to 1.5 μm). Then, the second inorganic interlayer insulating film 5 is anisotropically etched until the covering surface of the first inorganic interlayer insulating film 4 located below is exposed. For this etching, for example, reactive ion etching technology
(RIE) can be used. When this anisotropic etching step is completed, the second inorganic interlayer insulating film 5 is formed in a tapered shape that covers only the side wall surface of the first aluminum wiring 3 (see FIG. 1 (b)). Here, the first and second inorganic interlayer insulating films 4 and 5 are flattened by a coating method of an inorganic or organic insulating film 6 such as silica or siloic acid-based polymer, which is a conventional technique. At this time, since the second inorganic interlayer insulating film 5 filling the space between the aluminum wirings has a taper shape that spreads from bottom to top, this coating film sufficiently penetrates to a depth reaching the substrate surface. For example, even when the wiring interval is reduced to about 1.0 μm, this wiring step is sufficiently flattened.
Next, this coating film is isotropically etched until the coating surface of the first inorganic interlayer insulating film 4 covering the upper surface of the first layer aluminum wiring 3 is exposed again, and the third inorganic interlayer insulating film 7 is formed into a silicon nitride film. The structure shown in FIG. 1 (c) is obtained by using In this case, since the first and second inorganic interlayer insulating films 4 and 5 are sufficiently flattened in the first and second flattening steps, the flatness of the third inorganic interlayer insulating film 7 is also very good. . Therefore, the second layer aluminum wiring 8 is formed on this upper surface.
Can be easily formed as shown in FIG. 1 (d), and the through hole 9 having excellent moisture resistance and coverage can be formed on the aluminum wiring 3, so that the upper wiring can be disconnected. It is possible to produce a multi-layered aluminum wiring semiconductor device in which an accident is less likely to occur, with high density, high reliability, and high yield.
（発明の効果） 以上詳細に説明したように、本発明によれば、複数の第
１層配線の側壁面には、第１の層間絶縁膜を介してテー
パ状の第２の層間絶縁膜が形成されるので、その後、第
２の絶縁膜を塗布したときには、複数の第１層配線間の
段差が第２の絶縁膜で十分に埋めることができるから、
複合膜でできた層間絶縁膜を十分に平坦化することがで
き、第２層配線の段切れを防止することができる。しか
も、本発明によって形成された層間絶縁膜では、複数の
第１層配線の上面に位置する部分で、第１の層間絶縁膜
と第３の層間絶縁膜との間には、塗布して形成された第
２の絶縁膜が残っていないため、第１層配線と第２層配
線とを接続すべくスルーホールを開口しても、耐湿性の
悪化を防止することができる。(Effect of the Invention) As described in detail above, according to the present invention, the tapered second interlayer insulating film is provided on the side wall surfaces of the plurality of first layer wirings via the first interlayer insulating film. Since the second insulating film is formed, when the second insulating film is applied thereafter, the steps between the plurality of first layer wirings can be sufficiently filled with the second insulating film.
The interlayer insulating film made of the composite film can be sufficiently flattened and the disconnection of the second layer wiring can be prevented. Moreover, in the interlayer insulating film formed according to the present invention, it is formed by coating between the first interlayer insulating film and the third interlayer insulating film at the portion located on the upper surface of the plurality of first layer wirings. Since the removed second insulating film does not remain, even if a through hole is opened to connect the first layer wiring and the second layer wiring, deterioration of moisture resistance can be prevented.
また、第２の絶縁膜として平坦化特性に優れた有機塗布
膜を用いれば、平坦性をさらに向上させることができ、
スルーホールが形成される第１層配線の上方の層間絶縁
膜には第２の絶縁膜が残っていないので、従来有機塗布
膜を用いたときに問題となっていた、スルーホール部分
での耐湿性をも向上させることもでき、平坦性と耐湿性
とを同時に改善することができる。If an organic coating film having excellent flattening characteristics is used as the second insulating film, the flatness can be further improved,
Since the second insulating film does not remain in the interlayer insulating film above the first-layer wiring in which the through hole is formed, the moisture resistance in the through hole portion, which has been a problem when using the organic coating film in the past, is a problem. The flatness and moisture resistance can be improved at the same time.
したがって、下層アルミ配線が微小間隔を以って形成さ
れた場合でもきわめて良好な平坦性とスルー・ホール形
成のためのすぐれた加工性とを兼備した層間絶縁膜が容
易に形成できるので多層アルミ配線半導体装置の高集積
化、高信頼性化に顕著なる効果をあげることができる。Therefore, even when the lower layer aluminum wiring is formed with a minute interval, it is possible to easily form an interlayer insulating film having extremely good flatness and excellent workability for forming a through hole. It is possible to achieve a remarkable effect in high integration and high reliability of the semiconductor device.
第１図(a)〜(d)は本発明の一実施例を示す工程順序図で
ある。 １……半導体基板、２……フィールド絶縁膜、３……第
１層アルミ配線、４，５……第１および第２の無機層間
絶縁膜、６……無機または有機の絶縁塗布膜、７……第
３の無機層間絶縁膜、８……第２層アルミ配線、９……
スルー・ホール。1 (a) to 1 (d) are process sequence diagrams showing one embodiment of the present invention. 1 ... Semiconductor substrate, 2 ... Field insulating film, 3 ... First layer aluminum wiring, 4, 5 ... First and second inorganic interlayer insulating film, 6 ... Inorganic or organic insulating coating film, 7 ...... Third inorganic interlayer insulating film, 8 ...... Second layer aluminum wiring, 9 ......
Through hole.
Claims (1)
形成工程と、第２の層間絶縁膜形成工程と、第２層間絶
縁膜加工工程と、平坦化処理工程と、第３の層間絶縁膜
形成工程と、第２層配線形成工程とを有する半導体装置
の製造方法であって、 第１層配線形成工程は、半導体基板の絶縁膜上に複数の
第１層配線を形成する工程であり、 第１の層間絶縁膜形成工程は、露出した前記第１層配線
の表面と、前記第１層配線間の露出した絶縁膜の表面と
を連続的に被覆する第１の層間絶縁膜を形成する工程で
あり、 第２の層間絶縁膜形成工程は、前記第１の層間絶縁膜上
に、第１の層間絶縁膜とは異なる材料の第２の層間絶縁
膜を形成する工程であり、 第２層間絶縁膜加工工程は、前記第２の層間絶縁膜を異
方性エッチングすることにより、該第２の層間絶縁膜を
部分的に除去し、第１層配線間に形成された凹所の内側
壁部にのみ第２の層間絶縁膜をテーパ状に残留させ、そ
れ以外の領域での第１の層間絶縁膜を外部に露出させる
工程であり、 平坦化処理工程は、前記第１層配線間の凹所内に絶縁膜
を第１層配線の段差分に相当する深さまで塗布法により
充填し、絶縁膜全体の高さを平坦化する工程であり、 第３の層間絶縁膜形成工程は、平坦化された前記絶縁膜
上に第３の層間絶縁膜を平坦に形成する工程であり、 第２層配線形成工程は、前記第３の層間絶縁膜上に第２
層配線を形成する工程であり、 第２層配線は、前記絶縁膜を貫通して形成されたスルー
ホールを介して第１層配線に適宜接続されるものである
ことを特徴とする半導体装置の製造方法。1. A first layer wiring forming step, a first interlayer insulating film forming step, a second interlayer insulating film forming step, a second interlayer insulating film processing step, a flattening processing step, and a third step. Is a method of manufacturing a semiconductor device having an interlayer insulating film forming step and a second layer wiring forming step, wherein the first layer wiring forming step forms a plurality of first layer wirings on an insulating film of a semiconductor substrate. In the first interlayer insulating film forming step, the first interlayer insulating film is formed by continuously covering the exposed surface of the first layer wiring and the exposed surface of the insulating film between the first layer wirings. The second interlayer insulating film forming step is a step of forming a second interlayer insulating film of a material different from that of the first interlayer insulating film on the first interlayer insulating film. The second interlayer insulating film processing step is performed by anisotropically etching the second interlayer insulating film. The second interlayer insulating film is partially removed, the second interlayer insulating film is left in a tapered shape only on the inner side wall of the recess formed between the first layer wirings, and the second interlayer insulating film in the other regions is removed. 1 is a step of exposing the interlayer insulating film to the outside. In the flattening step, the insulating film is filled in the recesses between the first layer wirings to a depth corresponding to the step difference of the first layer wirings by a coating method. A step of flattening the entire height of the insulating film, and a step of forming a third interlayer insulating film is a step of flattening a third interlayer insulating film on the flattened insulating film. The two-layer wiring forming step is performed by forming a second layer on the third interlayer insulating film.
It is a step of forming a layer wiring, wherein the second layer wiring is appropriately connected to the first layer wiring through a through hole formed through the insulating film. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62041883A JPH0611043B2 (en) | 1987-02-24 | 1987-02-24 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62041883A JPH0611043B2 (en) | 1987-02-24 | 1987-02-24 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63208243A JPS63208243A (en) | 1988-08-29 |
| JPH0611043B2 true JPH0611043B2 (en) | 1994-02-09 |
Family
ID=12620673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62041883A Expired - Lifetime JPH0611043B2 (en) | 1987-02-24 | 1987-02-24 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0611043B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3128811B2 (en) * | 1990-08-07 | 2001-01-29 | セイコーエプソン株式会社 | Method for manufacturing semiconductor device |
| US5514624A (en) * | 1990-08-07 | 1996-05-07 | Seiko Epson Corporation | Method of manufacturing a microelectronic interlayer dielectric structure |
| JP4527948B2 (en) * | 2003-05-23 | 2010-08-18 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5886746A (en) * | 1981-11-19 | 1983-05-24 | Nec Corp | Semiconductor device |
| JPS60210851A (en) * | 1984-04-05 | 1985-10-23 | Toshiba Corp | Semiconductor device and manufacture thereof |
-
1987
- 1987-02-24 JP JP62041883A patent/JPH0611043B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63208243A (en) | 1988-08-29 |
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