JP3020533B2 - Crystal oscillator frequency adjustment device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a frequency adjusting device by time-division switching of an oscillation capacitor attached to a crystal oscillator.

[Conventional technology]

Conventionally, it is well known that frequency adjustment is performed by switching the capacitors of a crystal oscillator in a time-division manner.
No. 50-131747) As shown in FIG. 5, an oscillation circuit 1 configured to adjust an oscillation frequency by switching an oscillation capacitor connected to an oscillator in a time-division manner, and an oscillation signal from the oscillation circuit 1 being input. And a frequency generating means 4 for outputting a frequency-divided signal.

The frequency adjusting means 4 outputs an adjustment setting circuit 6 which outputs temperature information output from the temperature sensor as an adjustment setting value.
And a frequency adjustment circuit 5 for controlling the oscillation capacitor of the oscillation circuit 1 in a time-division manner by inputting an adjustment set value from the adjustment setting circuit 6 and a frequency-divided signal from the signal generation circuit 2 for a certain period. Have been. Reference numeral 3 denotes a clock circuit that outputs time information according to a clock signal from the signal generation circuit 2.

[Problems to be solved by the invention]

In the above-described conventional example, the oscillation capacitor of the oscillation circuit 1 is controlled in a time-division manner for a certain period based on the set value from the adjustment setting circuit 6. Due to the variation, the characteristic of the frequency change amount with respect to the capacitance of the capacitor is changed. Therefore, even if the frequency is adjusted by controlling the capacitor in a time-division manner as originally set at the time of design, an adjustment error due to the variation occurs. As a result, there has been a problem that high-precision frequency adjustment cannot be performed because the process variation is not considered.

In order to solve the above-mentioned problem, the present invention always provides a frequency adjustment coefficient correcting means for correcting a process variation with respect to the configuration of the conventional example, thereby always reducing the frequency.
It is an object of the present invention to provide a crystal oscillator frequency adjustment device capable of improving the frequency adjustment accuracy by keeping the relationship of capacitance characteristics constant.

[Means for solving the problem]

In order to achieve the above object, the present invention has the following configuration. That is, an oscillation circuit, a signal generation circuit that outputs clock information and the like, and a clock circuit that outputs time information, time-division switching of the capacitor of the oscillation circuit,
Alternatively, in an electronic timepiece provided with frequency adjusting means for adjusting the frequency for selecting the capacitance value, the relationship between df / dc, which is the capacitance-frequency characteristic of the oscillation circuit, is switched by switching the output resistance value of the oscillation circuit. It is characterized in that a frequency adjusting coefficient correcting means for correcting is provided.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of an electronic timepiece provided with a crystal oscillator according to the present invention, FIG. 1 is a circuit block diagram showing a specific configuration, FIG. 3 is a main voltage waveform diagram, and FIG. FIG. 3 is a frequency-capacity characteristic diagram of a crystal oscillator.

Reference numeral 1 denotes an oscillation circuit provided with a crystal oscillator. Reference numeral 2 denotes a signal generation circuit that receives an oscillation signal from the oscillation circuit 1 and outputs time information and the like. Reference numeral 3 denotes time information according to a clock signal from the signal generation circuit 2. Is a clock circuit that outputs

Numeral 4 denotes a frequency adjusting means, which comprises a frequency adjusting circuit 5 and an adjustment setting circuit 6;
Is to adjust the frequency by switching the oscillation capacitor of the oscillation circuit 1 in a time-division manner for a certain period in accordance with the adjustment amount set value from the adjustment circuit 6. The above configuration is the same as the conventional example shown in FIG.

Reference numeral 7 denotes a frequency adjustment coefficient correction unit, which includes a coefficient correction circuit 8 and a coefficient correction setting circuit 9.

The coefficient correction circuit 8 selectively switches the output resistance value of the oscillation circuit 1 according to the coefficient correction setting value from the coefficient correction setting circuit 9 to correct the frequency-capacitance characteristics.

 Next, a specific configuration will be described with reference to FIG.

The oscillation circuit 1 includes an oscillation inverter 10, oscillation capacitors 11 and 13, a crystal oscillator 12, an output resistor 14, a feedback resistor 26, and a switching transistor 15 connected between the oscillation capacitor 13 and a power supply.

The inverter 10 is connected in parallel to a feedback resistor 26, and one input terminal is connected to an oscillation capacitor 11 which is connected to a power supply on one side, and the crystal resonator 12
Are connected to one terminal. The output terminal is connected to the signal generating circuit 2 and to one terminal of the output resistor 14. The other terminal of the output resistor 14 is connected to the other terminal of the crystal unit 12 and to one terminal of the oscillation capacitor 13. Further, the output resistor 14 is an N-channel transistor (hereinafter abbreviated as N-Tr) of the frequency adjustment coefficient correction means 7 described later.
The drain terminals of the N-Trs 16, 17 are connected to the intermediate tap terminal (A) of the output resistor 14,
(B).

The other terminal of the oscillation capacitor 13 is a capacitor time-division switching N-Tr having one connected to a power supply.
Connected to the other 15 terminals. The control signal (PC) from the frequency adjusting means 4 is input to the gate terminal of the switching N-Tr 15.

The signal generating circuit 2 includes a frequency dividing circuit 18, a waveform shaping circuit 19
It is composed of

The frequency dividing circuit 18 performs a frequency dividing operation by using the oscillation signal from the oscillation circuit 1 as an input, and performs frequency dividing signals (Pf1), (Pf2),
(F3) is output. The waveform shaping circuit 19 receives the frequency-divided signal (f3) from the frequency-divider circuit 18 and outputs a driving pulse.

The clock circuit 3 includes a drive circuit 20 and a display device 21.

The drive circuit 20 receives the drive pulse from the waveform shaping circuit 19 and outputs time information, and the display device 21 displays time.

The frequency adjusting means 4 includes a frequency adjusting circuit 5 and an adjustment setting circuit 6.

The frequency adjustment circuit 5 includes a counter 22 and a coincidence detection circuit.
The clock input terminal (CL) of the counter 22 comprises a latch circuit 24, an AND gate 25, and receives a frequency-divided signal (Pf1) from the frequency-divider circuit 18 to perform a count operation. The frequency-divided signal (Pf2) is input to the reset terminal (), and the frequency-divided signal (Pf2) is The counter 22 operates only during the level period, and counts the frequency-divided signal (Pf1).

The coincidence detection circuit 23 detects coincidence between the count information (PF) of the counter 22 and the frequency adjustment information (PL) from the latch circuit 24, and outputs a coincidence detection signal (PK) from an output terminal (). The reset terminal of the match detection circuit 23
The frequency-divided signal (Pf2) is also input to the Operates only during the level period.

A frequency-divided signal (Pf2) is input to the set terminal () of the latch circuit 24, and the frequency-divided signal (Pf2) is At the time of level, the adjustment setting information (PSW) from the adjustment setting circuit 6 is latched. At this time, the adjustment setting information (PSW) is not set. In the case of, the zero detection signal (PZ) is output from the output terminal ().

The AND gate 25 outputs the divided signals (Pf1), (Pf2),
A time-division control signal (PC) is output by inputting the zero detection signal (PZ) and the coincidence detection signal (PK) from the latch circuit.

The adjustment setting circuit 6 is constituted by a storage element such as a nonvolatile memory, and inputs a frequency adjustment set value by external writing.

Reference numeral 7 denotes frequency adjustment coefficient correction means, and a coefficient correction circuit 8
And a coefficient correction setting circuit 9. The coefficient correction circuit 8 includes N-Trs 16 and 17, the source terminals of the N-Trs 16 and 17 are connected to the output terminal of the inverter 10 of the oscillation circuit 1 and one terminal of the output resistor 14, and the N-Tr 16 The drain terminal is connected to the intermediate tap terminal (A) of the output resistor 14, and the gate terminal is connected to the switch output terminal of the setting switch (S1) of the coefficient correction setting circuit 9. or,
The drain terminal of the N-Tr 17 is connected to the intermediate tap terminal (B) of the output resistor 14, and the gate terminal is connected to the switch output terminal of the setting switch (S2) of the coefficient correction setting circuit 9.

The setting switches (S1) and (S1) of the coefficient correction setting circuit 9
When any of 2) is turned ON, coefficient correction setting signals (PS1) and (PS2) are output from each switch output terminal.
The coefficient correction setting signal (PS1) When the level signal is output, the N-Tr of the coefficient correction circuit 8 is output.
16 is turned on, the intermediate tap terminal (A) of the output resistor 14 of the oscillation circuit 1 and the output terminal of the inverter 10 are short-circuited, and the resistance value of the output resistor 14 is reduced to half. Similarly, the coefficient correction setting signal (PS2) When a level signal is output, the N-Tr 17 is turned on, so that the output resistor 14 is short-circuited between the intermediate tap terminal (B) and the output terminal of the inverter 10 and the resistance value of the output resistor 14 becomes 2/3. .

Next, the frequency adjustment operation of the electronic timepiece having the above configuration will be described.

Before the frequency adjustment, the memory of the adjustment setting circuit 6 is not written, so that the frequency adjustment setting information (PS
W) is It has been. Therefore, from the output terminal () of the latch circuit 24 connected to the frequency adjustment circuit 5, The level zero detection signal (PZ) is output. The zero detection signal (PZ) When it is at the level, the time division control signal (PC) from the AND gate 25 is also Level.

At this time, the setting switches (S1) and (S2) of the coefficient correction setting circuit 9 of the frequency adjustment coefficient correcting means 7 are not set, and the coefficient correction setting means from each of the switches (S1) and (S2) is not set. (PS1) and (PS2) are both Outputs a level signal. Therefore, the N-Trs 16 and 17 of the coefficient correction circuit 8 are both in the OFF state, and the output resistance 14 of the oscillation circuit 1 has a resistance value of 1/1.

Therefore, the oscillating operation is performed in a state where the switching Tr 15 of the oscillation circuit 1 is in an OFF state, that is, the oscillation capacitor 13 is not connected and the output resistor 14 has a resistance value of 1/1. The signal generation circuit 2 operates with the oscillation signal as input, outputs a driving pulse, and the time information is displayed on the display device 21 via the driving circuit 20.

At this point, the oscillation frequency (fs) is measured using a measuring instrument, and the frequency adjustment amount is determined.

Frequency adjustment amount of the time setting (f _T) is the difference between the frequency (f _Z) to be the narrowing actually combined with the measured frequency (f _S) frequency adjustment factor (f _T) = Measurement Frequency (f _S ) −the matching frequency (f _Z ). In order to adjust and set the frequency adjustment amount (f _T ), the oscillation capacitor is designed by design.
13 is calculated from the time ratio of the connection of the capacitor 13 within a specific time on the premise of the frequency change (f _C ) between the time of connection and the time of non-connection. That is, the frequency adjustment set value (f _M ) = the frequency adjustment amount (f _T ) / the frequency change amount (f _C ), but the time-division control signal (PC) input to the switching Tr 15
Is a pulse having a duty of 50%, so that the value of the frequency adjustment set value (f _M ) / 2 is actually written in the storage element of the adjustment setting circuit 6.

Therefore, the adjustment setting information (PSW) is output from the adjustment setting circuit 6 and the zero detection signal (P
Z) is Output level.

The frequency division signal (Pf2) from the frequency division circuit 18 is When a level signal arrives, the adjustment setting information (PSW) from the adjustment setting circuit 6 is latched by the latch circuit 24, and frequency adjustment information (PL) is output.

At this time, the frequency-divided signal (Pf
2) Period T ₁ in the level counter of the frequency adjusting circuit 16
22 and the match detection circuit 23 are in a non-operating state, and the AND gate 25 is also closed. A level-division control signal (PC) is output, and the oscillation capacitor 13 of the oscillation circuit 1 oscillates in a non-connected state.

Next, the divided signal (Pf2) Period T ₂ becomes level the counter 22 and the coincidence detection circuit
23 is set in an operating state, and the counter 22 outputs the frequency-divided signal (Pf
As shown in FIG. 3D, a time-division control signal (PC) is output through the AND gate 25 and the oscillation capacitor 13 is connected in a time-division manner and oscillates, as shown in FIG. When the count information (PF) of the counter 22 matches the frequency adjustment information (PL) from the latch circuit 24,
From the match detection circuit 23 The level match is output, the AND gate 25 is closed again, and the time-division control signal (PC) The oscillation capacitor 13 is set to the level and the oscillation capacitor 13 is again disconnected, and the oscillation is continued.

Thereafter, the same operation as described above is repeated, but the oscillation frequency of the oscillation circuit 1 is one cycle (T ₁ + T ₁ ) of the frequency-divided signal (Pf2).
_The frequency obtained by averaging ₂ ) is the frequency after the frequency adjustment by the frequency adjustment means 4. However, this is the case where the output resistors 14 and the oscillating capacitors 11 and 13 are exactly the same as the design values, and correction is necessary if the built values do not match the design values. Become.
Here, the principle of the coefficient correction circuit 8 constituting the frequency adjustment coefficient correction means 7 used in the embodiment of the present invention will be described with reference to FIG.

FIG. 4 is a capacitance-frequency characteristic diagram of the oscillation circuit 1. The horizontal axis indicates the capacitance value (0 to 0) of the oscillation capacitor 13.
10PF) and the vertical axis shows the amount of change (df) in each frequency depending on the resistance value of the output resistor 14.

Therefore, the setting switch (PS) of the coefficient correction setting circuit 9
1) When (PS2) is not set, the resistance value of the output resistor 14 is not changed and a capacitance such as C1 shown in FIG.
It shows frequency characteristics, and the amount of frequency change (df) by switching connection / disconnection of the capacitance of the oscillation capacitor 13 is (df)
1). When the setting switch (PS2) is set, the resistance value of the output resistor 14 is reduced to 2/3 to show the capacitance-frequency characteristic of C2 in FIG. (Df) becomes (df2).
Further, when the setting switch (PS1) is set, the resistance value of the output resistor 14 is reduced by half, and
The figure shows the capacitance-frequency characteristic of C3 in the figure, and the frequency change (df) by switching the capacitance is (df3). The frequency adjustment coefficient correction means 7 of the present embodiment focuses on the fact that the capacitance-frequency characteristics change by changing the resistance value of the output resistor 14 of the oscillation circuit 1 as described above.

That is, in the case of the designed value, the frequency change amount (f) when the oscillation capacitor 13 is connected or disconnected as shown by C1 in FIG.
Although (c) changes (df1), normal adjustment can be performed, but normal frequency adjustment cannot be performed unless the oscillation capacitor 11 or 13 is made as designed. For example, if the capacitance of the oscillation capacitor 11 or 13 becomes smaller than a design value, the frequency change (fc) when the oscillation capacitor 13 is connected or disconnected is reduced, and the adjustment setting circuit 6
When the frequency is adjusted according to the value set in the above, the frequency after the frequency adjustment becomes a low frequency.

Therefore, in the present invention, the setting switch (S1) or (S2) of the coefficient correction circuit 9 is used to correct the coefficient of the frequency variation (fc) for the deviation of the frequency adjustment so as to adjust the frequency to the normal frequency. ) In the ON state, the value of the output resistor 14 is set to 1/1, 1/2, 2/3 as shown in FIG. 4 to change the characteristic of the capacitance-frequency change amount. When the resistance value of the output resistor 14 is 1/1, the frequency variation (df) is d
f1 changes to df2 when the output resistance 14 is 2/3, and changes to df3 when the output resistance value is 1/2. For example, turn on the setting switch (S2) now
In this state, the N-Tr 17 of the coefficient correction circuit 8 is turned on, and the resistance value of the output resistor 14 is reduced to 2/3. Therefore, as shown in FIG. 4, the frequency-capacitance characteristic, that is, the frequency change (fc) when the oscillation capacitor 13 is connected or disconnected is increased, and the change is (df2). If the setting switch (S1) is turned on to perform a larger coefficient correction, the resistance value of the output resistor 14 becomes 1/2, and the frequency change (fc) further increases to (df3).

As described above, by correcting the effective amount of the oscillation capacitor 13 in the oscillation circuit 1 by switching the resistance of the coefficient correction circuit 8, high-precision frequency adjustment can be performed.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, in a crystal oscillation circuit that performs time-division oscillation of a capacitor, the frequency adjustment by time-division is performed based on the design target value and the variation of the resistance and the capacitor due to the actual production. By providing the frequency adjustment coefficient correction means for correcting these errors even if errors occur, it is possible to provide a crystal oscillator frequency adjustment device capable of performing high-accuracy frequency adjustment using the same frequency setting value.

[Brief description of the drawings]

FIG. 2 is a block diagram of an electronic timepiece provided with a frequency adjusting device according to the present invention. FIG. 1 is a circuit block diagram embodying FIG. 2, and FIG. 3 is a main voltage of FIG. Waveform diagram,
FIG. 4 is a frequency-capacity characteristic diagram of a crystal oscillator, and FIG. 5 is a block diagram of an electronic timepiece according to a conventional embodiment. DESCRIPTION OF SYMBOLS 1 ... Oscillation circuit, 11, 13 ... Oscillation capacitor, 14 ... Output resistance, 15 ... Switching transistor, 4 ... Frequency adjustment means, 5 ... Frequency adjustment circuit, 6 ... Adjustment setting circuit, 7 ... Frequency adjustment coefficient correction means, 8... Coefficient correction circuit, 9... Coefficient correction setting circuit.

Claims (2)

(57) [Claims] An oscillation circuit, a signal generation circuit for outputting clocking information and the like with an oscillation signal from the oscillation circuit as an input, and a clock circuit for outputting time information, wherein a time-division switching of a capacitor of the oscillation circuit is performed. Alternatively, in an electronic timepiece provided with a frequency adjustment device that adjusts the frequency by selecting a capacitance value, by switching the output resistance value of the oscillation circuit, df / dc, which is the capacitance-frequency characteristic of the oscillation circuit, A frequency adjusting device for a crystal oscillator, comprising a frequency adjusting coefficient correcting means for correcting a relationship. 2. The frequency adjustment coefficient correction means includes: a coefficient correction circuit for switching an output resistance value of the oscillation circuit;
And a coefficient correction setting circuit for outputting a control signal for causing the coefficient correction circuit to select an output resistance value.