JP2005286667A - Oscillator and its oscillation frequency regulating method, electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillation circuit ensuring a stabilized oscillation frequency regardless of variation in power supply voltage, ambient temperature or manufacturing process. <P>SOLUTION: The oscillator comprises a means for counting the number of clocks at current oscillation frequency during the "H" level period or "L" level period of an "H" level signal or an "L" level signal having a predetermined period when it is inputted externally, and a means for storing the number of clocks in association with a digital value for current control, and regulates bias voltages PBIAS and NBIAS to the transistors 31 and 33 of a ring oscillator 20 by controlling mirror currents A and B flowing through a current control circuit 20 depending on the digital value. A digital value corresponding to the count of the count means is fed back, as a frequency regulation control signal, to the current control circuit 20 using a Look Up Table as a storage means thus regulating the oscillation frequency. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an oscillation device including a ring oscillator having a CMOS structure, an oscillation frequency adjusting method thereof, and an electronic apparatus including a drive circuit such as a liquid crystal display control IC that generates a drive signal using the oscillation device.

  In this type of liquid crystal display control IC, a drive signal is generated using an oscillation circuit including a ring oscillator having a CMOS structure. This conventional oscillation circuit will be described with reference to FIG.

  FIG. 6 is a circuit diagram showing a configuration example of a conventional oscillation circuit having a one-stage inverter circuit.

  As shown in FIG. 6, the oscillation circuit 1 includes a one-stage ring oscillator 2, a current control circuit 3 that controls the drive current of the inverter circuit that constitutes the ring oscillator 2, and an output circuit provided at the output section of the ring oscillator 2. 4.

  The ring oscillator 2 is connected to an odd number (here, one) of CMOS inverter circuits 21, and the output portion of the CMOS inverter circuit 21 at the final stage is the input of the inverter circuit 21 at the first stage (one stage) at the final stage. Connected to the department. A PchMOS transistor 22 (transistor means) as a constant current source for supplying and controlling a drive current (source current) is connected to the high potential (VDD) side of the inverter circuit 21, and a constant potential source is connected to the low potential (ground potential GND) side. An NchMOS transistor 23 (transistor means) as a current source is connected.

  In the output circuit 4, three inverter circuits 41 to 43 are connected in series on the output side of the ring oscillator 2, and a PchMOS transistor 44 that controls supply of drive current is provided on the high potential voltage source (VDD) side of the inverter circuit 41. The NchMOS transistor 45 is connected to the low potential voltage source (ground potential GND) side, and a clock signal as a frequency signal is output from the inverter circuit 43 at the final stage.

  The current control circuit 3 includes Pch MOS transistors 31 to 36 and Nch MOS transistors 37 to 39.

  The Pch MOS transistor 36 and the Nch MOS transistor 38 are diode-connected (a gate terminal and a source terminal or a drain terminal are connected). The Pch MOS transistor 36 and the Pch MOS transistor 22 of the ring oscillator 2 are connected to each other at their gate terminals to constitute a current mirror circuit. The NchMOS transistor 38 is connected to the NchMOS transistor 23 of the ring oscillator 2 at the gate terminals thereof to form a current mirror circuit.

  The PchMOS transistor 36 is connected in parallel to the PchMOS transistor 35 whose gate terminal receives the control signal ENABLE. When the “H” level ENABLE signal is input to the PchMOS transistor 35 and is turned off, the PchMOS transistor 36 is turned off. The transistor 36 is turned on and the mirror current B flows. In the Pch MOS transistor 36, an Nch MOS transistor 38 and an Nch MOS transistor 39 whose gate terminals are connected to each other are connected in series on the low potential side, and the mirror current B is also controlled by the Nch MOS transistor 39.

  The NchMOS transistor 38 is connected in parallel with the NchMOS transistor 37 whose gate terminal receives the inverted signal ENABLE_ of the control signal ENABLE. The NchMOS transistor 37 is turned off by receiving the “L” level ENABLE_ signal. At that time, the Nch MOS transistor 38 is turned on and the mirror current A flows. The Nch MOS transistor 38 has a Pch MOS transistor 34 connected in series on the high potential side, and the mirror current A is also controlled by the Pch MOS transistor 34.

  The gate terminal of the PchMOS transistor 34 includes a gate terminal of the PchMOS transistor 33 whose low potential side is connected in series with the external resistance element R (resistance value R), a PchMOS transistor 31 to which the control signal ENABLE is input, and its low potential. The PchMOS transistor 32 is connected in series with the PchMOS transistor 32 which is connected in series to the side and receives the inverted signal ENABLE_ of the control signal ENABLE at the gate terminal. The PchMOS transistor 32 has a high potential side connected to the body region of the substrate, and a low potential side connected to a connection portion between the external resistance element R and the low potential side of the PchMOS transistor 33.

  When an “H” level ENABLE signal is input to the PchMOS transistor 31 and an “L” level ENABLE_ signal is input to the PchMOS transistor 32 and turned on, the PchMOS transistors 33 and 34 are turned on and mirrored. Current A flows.

  In the conventional oscillation circuit 1 configured as described above, the oscillation frequency of the clock signal CLKOUT oscillated from the ring oscillator 2 can be changed by controlling the bias voltages PBIAS and NBIAS supplied from the current control circuit 3. it can.

  Hereinafter, control of the oscillation frequency of the ring oscillator 2 by the current control circuit 3 will be described with reference to FIGS. 7A and 7B.

  7A is a circuit diagram showing a configuration example of a ring oscillator having a three-stage inverter circuit instead of the one-stage ring oscillator of FIG. 6, and FIG. 7B is a circuit diagram of the ring oscillator of FIG. It is a signal waveform diagram for demonstrating operation | movement.

  As shown in FIG. 7 (a), PchMOS transistors 22a to 22c are connected to the high potential (power supply voltage VDD) side of odd-numbered (in this case, three) CMOS inverter circuits 21a to 21c, respectively. NchMOS transistors 23a to 23c are connected to the ground potential (GND) side. A bias voltage PBIAS from the current control circuit 3 is applied to the gate terminals of the PchMOS transistors 22a to 22c, and a bias voltage NBIAS is applied to the gate terminals of the NchMOS transistors 23a to 23c. These bias voltages PBIAS And a drive current (source current) according to NBIAS is generated.

  Therefore, source currents (drive currents) flowing through PchMOS transistors 22a-22c and NchMOS transistors 23a-23c connected to inverter circuits 21a-21c can be determined by bias voltages PBIAS and NBIAS.

In this ring oscillator, as shown in FIG. 7B, the phase difference between the input signal IN and the output signal OUT to the inverter circuits 21a to 21c connected in odd stages (here, 3 stages) is τ and is connected in series. Assuming that the number of inverter circuit stages is n, the oscillation frequency f obtained from the ring oscillator 2 is
Oscillation frequency f = 1 / (2nτ) Equation (1)
Represented by

  According to the above equation (1), the oscillation frequency f obtained from the ring oscillator can be variably controlled by controlling the phase difference τ.

  On the other hand, as described in Patent Document 1, for example, the phase difference τ varies depending on the source current of the inverter circuit. Therefore, by controlling the bias voltage supplied from the current control circuit 3, the oscillation frequency f of the clock signal oscillated from the ring oscillator can be changed.

  As a method of changing the bias voltages PBIAS and NBIAS supplied from the current control circuit 3, for example, a method of changing the resistance value of the external resistance element R is conceivable.

  As shown in FIG. 6, in the oscillation circuit 1, the Pch MOS transistor 22 and the Nch MOS transistor 23 of the ring oscillator 2 constitute a current mirror circuit with the Pch MOS transistor 36 and the Nch MOS transistor 38 of the current control circuit 3, respectively. The mirror current B flowing through the PchMOS transistor 36 is controlled by the NchMOS transistor 39, and the mirror current A flowing through the NchMOS transistor 38 is controlled by the PchMOS transistor 34.

  The gate terminals of the Pch MOS transistor 34 and the Pch MOS transistor 33 are connected to the connection part of the Pch MOS transistor 31 and the Pch MOS transistor 32. For this reason, the external resistance element R externally attached to the current control circuit 3 is replaced and its resistance value is changed, thereby changing the current flowing through the PchMOS transistor 33 and connecting the external resistance element R and the PchMOS transistor 33. , The potential of each connection portion between the Pch MOS transistor 31 and the Pch MOS transistor 32 also changes, and the mirror current A flowing through the Pch MOS transistor 34 changes.

  Thus, as the mirror current A changes, the mirror current B flowing through the PchMOS transistor 39 also changes. Thus, by changing the resistance value of the external resistance element R, the bias voltages PBIAS and NBIAS supplied from the current control circuit 3 are changed, and the oscillation frequency of the output clock signal CLKOUT from the ring oscillator 2 is arbitrarily changed. Can be made.

  Here, since accuracy is required for the control of the bias voltages PBIAS and NBIAS as the frequency control signal, an external resistor element (external) that can obtain higher accuracy than a resistor (internal resistance) manufactured using a semiconductor is used. A resistive element R) is used.

Further, as a conventional technique for changing the bias voltages PBIAS and NBIAS supplied to the ring oscillator 2 by replacing them with external resistance elements R having different resistance values, for example, Patent Document 2 discloses a PchMOS transistor 36 and a ring oscillator of the current control circuit 3. Also disclosed is a configuration in which resistors are provided between the two Pch MOS transistors 22 and between the Nch MOS transistor 38 of the current control circuit 3 and the Nch MOS transistor 23 of the ring oscillator 2.
JP-A-8-186474 JP-A-11-27106

  However, the conventional oscillation circuit has a problem that the oscillation frequency of the output clock signal changes due to variations in the power supply voltage VDD, the ambient temperature, the manufacturing process, and the like. Even when the oscillation frequency of the output clock signal is adjusted and controlled by the resistance value of the external resistance element R, if the resistance value varies due to variations in the manufacturing process of the external resistance element R, the output clock is correspondingly increased. The oscillation frequency of the signal also varies.

  For example, in a liquid crystal display whose display quality changes depending on the frame response, when the liquid crystal display is driven and controlled by a liquid crystal control IC (display drive circuit) that generates a drive signal using a conventional oscillation circuit as a clock signal, the oscillation of the output clock signal When the frequency variation becomes the drive frequency variation as it is and the frequency is shifted to the lower side, the drive frequency becomes low frequency, which causes a beat display phenomenon or a flicker display phenomenon.

  The present invention solves the above-described conventional problems, and can obtain a stable oscillation frequency of an output clock signal even if there are variations in power supply voltage, ambient temperature, manufacturing process, and resistance value of an external resistance element. It is an object of the present invention to provide an oscillation device capable of performing the above, an oscillation frequency adjusting method thereof, and an electronic apparatus using the oscillation device.

  The oscillation device of the present invention includes a ring oscillator means that can output a clock signal having a predetermined oscillation frequency by an inverter circuit configuration, a frequency adjustment control means that outputs a frequency adjustment signal according to the output oscillation frequency of the clock signal, Based on the output frequency adjustment signal, a control signal for controlling the drive current of the inverter circuit is variably controlled and supplied to the ring oscillator means, whereby the output oscillation frequency of the clock signal is set to a desired output oscillation frequency. Current control means enabling adjustment control, whereby the above object is achieved.

  Preferably, the frequency adjustment control means in the oscillation device of the present invention comprises: count means for counting the number of clocks in a predetermined period of the output oscillation frequency; and a digital value for variably controlling the count number and the control signal. Is stored in association with each other, and the digital value corresponding to the count number is output as the frequency adjustment signal from the storage unit.

  Further preferably, the counting means in the oscillation device of the present invention receives a reference signal that is at the “H” level or “L” level for a certain period, and the “H” level period or “L” level period of the reference signal. The number of clocks of the output oscillation frequency is counted as the count number.

  Further preferably, the storage means in the oscillation device of the present invention has a look-up table in which the count number and the digital value are associated with each other.

  Further preferably, the storage means in the oscillation device of the present invention further includes rewriting means for enabling rewriting of the stored value of the lookup table.

  Further preferably, in the ring oscillator means in the oscillation device of the present invention, an odd number of CMOS type inverter circuits are connected in series, and an output part of the last stage inverter circuit is connected to an input part of the first stage inverter circuit, Each constant current source for supplying each drive current is connected to the high potential side and the low potential side of each inverter circuit.

  Further preferably, each of the constant current sources in the oscillation device of the present invention comprises a transistor means, and the current control means can control the drive current of the inverter circuit by outputting the control signal to a control terminal of the transistor means. To do.

  Further preferably, the current control means in the oscillation device of the present invention comprises a high-potential side mirror transistor means in which the high-potential side transistor means of the constant current source and the respective control terminals are connected to form a current mirror circuit; The low-potential side transistor means of the constant current source and the low-potential side mirror transistor means constituting the current mirror circuit by connecting the control terminals to each other, and the current according to the digital value of the frequency adjustment signal A mirror current adjustment unit that enables adjustment control of the mirror current flowing in at least one of the mirror circuits is provided.

  Further preferably, in the oscillation device of the present invention, the first control transistor means is connected in series to the low potential side of the high potential side mirror transistor means, and the second control transistor is connected to the high potential side of the low potential side mirror transistor means. Transistor means are connected in series, and the low potential side mirror transistor means and each control terminal of the first control transistor means are connected to each other, and the mirror current adjustment unit is configured to respond to a digital value of the frequency adjustment signal. The control voltage of the second control transistor means can be adjusted and controlled.

  Further preferably, the mirror current adjustment unit in the oscillation device of the present invention is configured such that the low potential side drive terminal is connected to the control terminal of the second control transistor means, and the frequency adjustment signal Switch means for switching the control terminal of the adjustment transistor means to either the high potential side drive terminal or the low potential side drive terminal according to the digital value.

  Further preferably, a plurality of sets of adjusting transistor means and switch means in the oscillation device of the present invention are arranged in parallel by the number of bits of the digital value.

  Further preferably, the current control means in the oscillation device of the present invention includes a resistance element that enables the control signal to be variably controlled according to a resistance value.

  Further preferably, the current control means in the oscillation device according to the present invention is characterized in that the second control transistor means and other adjustment transistor means in which the control terminals are connected to each other, A resistance element connected in series to the potential side drive terminal and connected so that the potential of the connection point is linked to the potential of the control terminal, and the control signal is variably controlled according to the resistance value of the resistance element It is possible.

  Further, preferably, the resistance element in the oscillation device of the present invention is incorporated in the current control means, or is replaced with another resistance element having a different resistance value.

  An oscillation frequency adjustment method for an oscillation circuit according to the present invention is an oscillation frequency adjustment method for an oscillation device that adjusts and controls an output oscillation frequency of an oscillation device including a ring oscillator. The oscillation frequency adjustment method is an “H” level or an “L” level for a certain period. Is input to the counting means, and within the “H” level period or “L” level period of the reference signal, a count step for counting the number of clocks of the output oscillation frequency, and a digital signal corresponding to the counted number A frequency adjusting step for adjusting and controlling a control signal from the current control means for controlling the drive current of the ring oscillator to the ring oscillator based on the value, thereby achieving the above object.

  The electronic apparatus of the present invention is provided with a drive circuit that generates a drive signal using the oscillation device according to any one of claims 1 to 14, and thereby achieves the above object.

  The operation of the present invention will be described below with the above configuration.

  In the present invention, when a reference signal (“H” level or “L” level) for a certain period is input from the outside, the oscillation frequency of the current output clock signal (the initial value before adjustment by the digital value of the frequency adjustment signal) In the state), the count means for counting the number of clocks in the "H" level period or the "L" level period, and the count number and the digital value for current control by the current control means are stored in association with each other And switching the connection of the transistors in the current control means according to the digital value. Thereby, the current mirror ratio and the mirror current ratio are variably controlled, the control voltage (frequency control signal) to the constant current source of the ring oscillator means is adjusted and controlled, the drive current of the inverter circuit is controlled, and the output clock signal It becomes possible to variably control the oscillation frequency to a desired oscillation frequency.

  For example, using a look-up table as a storage means, a digital value corresponding to the count value (count number) of the count means is obtained, and this is fed back to set the oscillation frequency of the output clock signal to a desired oscillation frequency. Adjustment control can be performed quickly.

  As described above, according to the present invention, the control signal for controlling the drive current of the inverter circuit is supplied to the ring oscillator means based on the frequency adjustment signal corresponding to the output oscillation frequency of the clock signal and output. Since the oscillation frequency of the clock signal can be adjusted and controlled to the desired oscillation frequency, even if there are variations in the power supply voltage VDD, the ambient temperature, the manufacturing process, and the resistance value of the external resistance elements, the oscillation frequency of the output clock signal varies Can be suppressed. As a result, by mounting the oscillation device of the present invention on a liquid crystal control IC that controls a liquid crystal display whose display quality changes in response to a frame response, the liquid crystal panel can be driven at a driving frequency with little variation, and a flicker display phenomenon Good display quality can be obtained without causing the phenomenon of beat display.

  In addition, since the resistance element can be adjusted even if there is variation, it is not necessary to replace the resistor element as in the past, and an external resistor element can be incorporated, thereby reducing the cost of electronic equipment by reducing external parts. be able to.

  Hereinafter, embodiments of an oscillation device, an oscillation frequency adjusting method thereof, and an electronic apparatus using the oscillation device according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration example of the oscillation device of the present embodiment, and FIG. 2 is a circuit diagram showing a configuration example of the oscillation circuit 1A of FIG.

  As shown in FIGS. 1 and 2, the oscillation device 10 outputs a frequency adjustment signal (digital value D [4: 0]) that can be adjusted and controlled to a predetermined oscillation frequency according to the output clock signal CLKOUT. As a frequency adjustment control unit 5 as a frequency adjustment control means, and an oscillation means that can variably control a frequency control signal (bias voltage) from the current control circuit 3A to the ring oscillator 2 based on the output frequency adjustment signal. Oscillation circuit 1A.

  The frequency adjustment control unit 5 receives a reference signal REF which becomes “H” level or “L” level for a certain period from the outside, and oscillates within the “H” level period or “L” level period of the reference signal REF. The counter circuit 51 as a counting means for counting the number of clocks (clock value) of the oscillation frequency in the output clock signal CLKOUT currently oscillated from the circuit 1A, the count number (count value) counted by the counter circuit 51, and the frequency control signal A lookup table 52 (Look Up Table; count value / digital value comparison table) serving as storage means in which digital values for variably controlling (bias voltage) are stored in association with each other. The digital value stored in the look-up table 52 is Is output to the oscillation circuit 1A as the number adjustment signal.

  The oscillation circuit 1A supplies a ring oscillator 2 as ring oscillator means that can output a clock signal having a predetermined oscillation frequency by the inverter circuit 21, and supplies a frequency control signal for controlling the drive current of the inverter circuit 21 to the ring oscillator 2. And a current control circuit 3A as current control means for adjusting and controlling the output oscillation frequency of the clock signal.

  The difference between the oscillation circuit 1A and the conventional oscillation circuit 1 shown in FIG. 6 is that, in addition to the current control circuit 3 shown in FIG. 6, a frequency control signal corresponding to a digital value (frequency adjustment signal) from the frequency adjustment control unit 5 is used. This is that a mirror current adjustment unit 40 for adjusting and controlling (bias voltage) is provided in the current control circuit 3A.

  Although not shown in FIG. 2, the mirror current adjustment unit 40 includes a switch unit 40a and a PchMOS transistor 40b as adjustment transistor means, which are arranged in parallel to correspond to a 5-bit digital value. It is installed. In this switch unit 40a, the control terminal of the PchMOS transistor 40b is connected to the low potential side (connection portion of the PchMOS transistor 31 and the PchMOS transistor 32) or the high potential side (power supply voltage VDD) of the PchMOS transistor 40b for each bit of the digital value. The drive terminal on the low potential side of the Pch MOS transistor 40b is connected to the control terminal of the Pch MOS transistor 34 as the second control transistor means of the current mirror circuit.

  That is, according to the frequency adjustment signal (digital value D [4: 0]) from the frequency adjustment control unit 5, the control terminal of the Pch MOS transistor 40b is either the high potential side drive terminal or the low potential side drive terminal. Is controlled to be switched. When the control terminal of the Pch MOS transistor 40b and the low potential side drive terminal are connected by the switch unit 40a, the Pch MOS transistor 40b is turned on, and the Pch MOS transistor 34 is turned off by supplying a high potential to the control terminal. The mirror current A does not flow. On the other hand, when the control terminal of the PchMOS transistor 40b and the high potential side drive terminal are connected by the switch unit 40a, the PchMOS transistor 40b is turned off, and the PchMOS transistor 34 is turned on without supplying a high potential to the control terminal. The mirror current A flows.

  In the following, the method for adjusting the oscillation frequency of the oscillation device 10 according to the present embodiment will be described in detail.

  FIG. 3 is a signal waveform diagram for explaining the oscillation frequency adjusting method of the oscillation device 10 in the present embodiment. FIG. 3 shows a control signal ENABLE for starting and controlling the oscillation operation of the oscillation circuit 1A, a reference signal REF input from the outside to the counter circuit 51 at any time when the power supply voltage is stable after power-on, and an oscillation circuit In order to variably control the output clock signal CLKOUT oscillated from 1A and the bias voltage from the current control circuit 3A to the ring oscillator 2, a frequency adjustment signal (digital value) supplied from the frequency adjustment control unit 5 to the oscillation circuit 1A D [4: 0]). Although the reference signal REF that is at the “H” level for a certain period is shown here, the reference signal REF that is at the “L” level for a certain period may be used. Further, although the 5-bit digital signal D [4: 0] is used as the frequency adjustment signal, a necessary number of bits may be set.

  On the other hand, in the oscillation device 10 of the present embodiment, the resistance value of the external resistance element R connected (externally connected) to the oscillation circuit 1A is set to a resistance value at which a target frequency is output. This resistance value determines the mirror current in the current control circuit 3A, and if the resistance value varies, the oscillation frequency also varies accordingly.

  Since the resistance value of the external resistance element R is required to be accurate, the external resistance element R is connected (externally connected) to the current control circuit 3A of the oscillation circuit 1A as an external resistance element having higher precision than a resistance element manufactured using a semiconductor. The At present, as the external resistance element R, those having an accuracy of 1% or less (variation in resistance value) and those having a resistance value system up to two digits after the decimal point are commercially available. Resistance elements using semiconductors Therefore, it is preferable to use the external resistance element R because it can be manufactured with much higher accuracy than the manufacturing variation.

  In this manner, the output clock signal CLKOUT is oscillated and output from the oscillation circuit 1A by setting the control signal ENABLE shown in FIG. 3 to the “H” level in a state where the external resistance element R is connected to the oscillation circuit 1A. The counter circuit 51 determines the number of rising edges (oscillation frequency; count number) of the output clock signal CLKOUT that is oscillated and output from the oscillation circuit 1A at that time within a period in which the reference signal REF from the outside is “H” level. Be counted.

  For example, when the target oscillation frequency is 5 MHz and the “H” level period of the reference signal REF is 50 μs, the output clock signal CLKOUT oscillated and output from the oscillation circuit 1A within the “H” level period of the reference signal REF There will be 250 rising edges. In the initial oscillation state, if the oscillation frequency is faster than 5 MHz, the count number of the “H” level period of the reference signal REF is more than 250, and if it is a slow frequency, the “H” level period of the reference signal REF. Is less than 250.

  The count value (count number) is transferred from the counter circuit 51 to a lookup table 52 (Look Up Table). Here, as the reference signal REF, for example, a signal that is at the “H” level for a certain period, such as 50 μs, is supplied. On the contrary, a signal that is at the “L” level for a certain period is supplied. May be.

  In the look-up table 52 (Look Up Table), the oscillation characteristics of the oscillation circuit 1A are obtained from the current control circuit 3A to the ring oscillator 2 on the basis of measurement data and simulation results considering the power supply voltage VDD, ambient temperature, and manufacturing process variations. A digital value for controlling the frequency control voltage (bias voltage) supplied to is set in association with the count value.

  The stored value of the lookup table 52 (Look Up Table) can be appropriately rewritten so as to have a desired output oscillation frequency by a rewriting means (not shown). As such a lookup table 52 (Look Up Table), either a nonvolatile memory such as an EEPROM or a volatile memory such as a RAM may be used. If a set value (stored value) is written in advance using a non-volatile memory, there is an advantage that it is possible to save the trouble of re-setting when the power is turned on again.

  4 shows the digital value D of the frequency adjustment signal supplied from the frequency adjustment control unit 5 of FIG. 1 to the mirror current adjustment unit 40 of the oscillation circuit 1A and the oscillation frequency (MHz) of the output clock signal CLKOUT from the oscillation circuit 1A. It is a graph which shows the example of a relationship. The horizontal axis in FIG. 4 indicates the digital value D in decimal, and the vertical axis indicates the oscillation frequency (MHz) of the output clock signal CLKOUT at that time.

  In the example of FIG. 4, it is designed so that an oscillation frequency of 5 MHz is oscillated when the digital value D [4: 0] = [1, 0, 0, 0, 0], and as the digital value D increases. It is designed such that the oscillation frequency increases to 5.80 MHz and the oscillation frequency decreases to 4.00 MHz as the digital value D decreases. Thus, in the current control circuit 3A, the oscillation frequency can be variably controlled almost linearly by the frequency adjustment signal (digital value D) supplied to the mirror current adjustment unit 40.

  FIG. 5 is a diagram illustrating an example of setting the number of clocks and the digital value D lookup table 52 (Look Up Table) when the digital value D and the oscillation frequency are set as shown in FIG.

  As shown in FIG. 5, the lookup table 52 (Look Up Table) is set so that the frequency is adjusted by the digital value D [4: 0] of the frequency adjustment signal shown in FIG. In the example of FIG. 5, the digital value D [4: 0] = [1, 0, 0, 0, 0] when the count number of the output clock signal CLKOUT by the counter circuit 51 (the rising number of CLKOUT) is 248 to 252. As the count number (count value) by the counter circuit 51 increases, the digital value decreases to D [4: 0] = [0, 0, 0, 0, 0], and the count number (count value) is reduced. As the value decreases, the digital value D is set to increase to D [4: 0] = [1,1,1,1,1].

  For example, when the initial oscillation frequency is 5 MHz, the counter circuit 51 counts the number of clocks as 250 in the “H” level period of the reference signal REF, for example, a period of 50 μs, and therefore the lookup table 52 (Look Up Table). ), The digital value D [4: 0] = [1, 0, 0, 0, 0] is selected and supplied to the mirror current adjustment unit 40 of the current control circuit 3A as the frequency adjustment signal D [4: 0]. Is done.

  Here, for example, when the count value by the counter circuit 51 within the “H” level period of the reference signal REF is “255”, an output clock signal of 50 (μs) / 255 (clock) = 5.1 (MHz). CLKOUT is oscillated and output.

  Originally, when D [4: 0] = [1, 0, 0, 0, 0] is set as the digital value D of the frequency adjustment signal, the oscillation circuit unit 3A should oscillate at an oscillation frequency of 5 MHz. However, when the count value is “255”, the oscillation frequency varies up to the count value when the digital value D [4: 0] = [1, 0, 0, 1, 0] shown in FIG. 4 is set. Will be.

  Thus, in order to adjust the oscillation frequency that varies, the digital value D [4: 0] corresponding to the count value “250” is changed from [1, 0, 0, 0, 0] to [1, 0, The digital value D [4: 0] of the look-up table 52 (Look Up Table) is set to [0, 1, 1, 1, 0 by the rewriting means so as to be lowered by the shift amount to 0, 1, 0]. ] May be set.

  In this way, by creating the look-up table 52 (Look Up Table), it is possible to adjust the oscillation frequency according to the count value by the counter circuit 51 as the counting means, and to suppress variations in the oscillation frequency from the beginning. It becomes.

  As described above, according to the present embodiment, when the “H” level signal or the “L” level reference signal REF for a certain period is input to the counter circuit 51 from the outside, the “H” level period or “L” level is input. During the period, the number of clocks of the output clock signal CLKOUT having the current oscillation frequency is counted. In the look-up table 52 (Look Up Table), the count value by the counter circuit 51 and the digital value D for mirror current control are stored in association with each other, and a mirror that flows in the current control circuit 3A according to the digital value D is stored. The currents A and B are controlled, and the bias voltages PBIAS and NBIAS to the transistors 22 and 23 of the ring oscillator 2 are adjusted and controlled. In this way, the look-up table 52 (Look Up Table) is used as the storage means, and the digital value D corresponding to the count value by the counter circuit 51 is fed back to the mirror current adjustment unit 40 of the current control circuit 3A as a frequency adjustment control signal. Then, the control signals (bias voltages PBIAS and NBIAS) from the current control circuit 3A to the ring oscillator 2 are adjusted and controlled. As a result, a clock signal having a stable output oscillation frequency can be obtained even if the power supply voltage VDD, the ambient temperature, the manufacturing process, and the resistance value of the resistance element vary.

  As described above, the oscillation device 1A according to the present embodiment, which can obtain a stable oscillation frequency with little variation, is mounted on, for example, a liquid crystal control IC that drives a liquid crystal display, thereby suppressing variation in drive frequency and beat display. A better display quality can be obtained without causing a phenomenon or a flicker display phenomenon.

  In the above embodiment, the resistance element R may be provided as an external resistance element outside the oscillation circuit 1A so that it can be replaced with another resistance element having a different resistance value in order to adjust the output oscillation frequency. However, the present invention is not limited to this, and the function of adjusting the output oscillation frequency of the present invention may be incorporated as an internal resistance element R in the current control circuit 3B of the oscillation circuit 1B as shown in FIG. That is, as in the function of adjusting the output oscillation frequency of the present invention, the resistance element R can be adjusted and controlled to a desired output oscillation frequency even if the resistance value of the resistance element R varies. It is not necessary to replace with another resistance element R having a different resistance value for adjustment of the resistance, and the resistance element R can be incorporated in the current control circuit 3B, and external parts can be reduced, thereby reducing the cost of the electronic device. Can be achieved.

  In the above embodiment, it has been described that in the mirror current adjustment unit 40, the five switch units 40a and the PchMOS transistor 40b are connected in parallel to the voltage source VDD. However, the 5-bit digital value D [0,1 , 1, 1, 0], for example, the first switch unit 40a is turned off, the second to fourth switch units 40a are turned on, and the fifth switch unit 40a is turned off. As described above, since there are 5 bits, there are 32 combinations of the voltage drop of the PchMOS transistor 40b depending on the on / off 32 combinations of the first to fifth switch sections 40a, and any of these 32 voltages is selected. Then, it is input to the control terminal of the Pch MOS transistor 34 to control the mirror current. Thus, based on the output 5-bit frequency adjustment signal, the mirror current is controlled to variably control the control signal for controlling the drive current of the inverter circuit 21, and this is supplied to the ring oscillator 2. The output oscillation frequency of the clock signal can be adjusted and output to a desired output oscillation frequency. Here, the digital value D is not limited to 5-bit information, and may be 3 bits, 4 bits, 6 bits, or a plurality of bits other than these. Also in this case, a plurality of sets of the switch unit 40a and the PchMOS transistor 40b corresponding to a plurality of bits are necessary.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to an oscillation device including a ring oscillator having a CMOS structure, an oscillation frequency adjusting method thereof, and an electronic device including a drive circuit such as a liquid crystal display control IC that generates a drive signal using the oscillation device. Even if there are variations in power supply voltage VDD, ambient temperature, manufacturing process, etc., it is possible to suppress variations in oscillation frequency, so that the oscillation signal is used as a clock signal as in a liquid crystal control IC, etc. Can be widely used in devices such as liquid crystal displays controlled by the drive signal, electronic devices equipped with such circuits and devices, and to obtain highly reliable operating characteristics. it can.

It is a block diagram which shows the structural example of the oscillation apparatus of this embodiment. FIG. 2 is a circuit diagram illustrating a configuration example of an oscillation circuit in FIG. 1. It is a signal waveform diagram for demonstrating the oscillation frequency adjustment method of the oscillation apparatus of FIG. 2 is a graph showing an example of a relationship between a digital value of a frequency adjustment signal output from the frequency adjustment control unit of FIG. 1 to an oscillation circuit and an oscillation frequency (MHz) of an output clock signal from the oscillation circuit. It is a figure which shows the example of a setting of the look-up table (Look Up Table) of FIG. It is a circuit diagram which shows the structural example of the conventional oscillation circuit which has a 1 step | paragraph inverter circuit. (A) is a circuit diagram showing a configuration example of a ring oscillator having a three-stage inverter circuit instead of the one-stage ring oscillator of FIG. 6, and (b) is a diagram for explaining the operation of the ring oscillator of (a). FIG. It is a circuit diagram which shows the structural example of the oscillation circuit of other embodiment.

Explanation of symbols

1A, 1B Oscillator circuit 2 Ring oscillator 21, 21a-21c, 41-43 Inverter circuit 22, 22a-22b, 31-36, 40b, 44 Pch MOS transistor 23, 23a-23b, 37-39, 45 Nch MOS transistor 3A, 3B Current control circuit 40 Mirror current adjustment part 40a Switch part 4 Output part 5 Frequency adjustment control part 51 Counter circuit 52 Look-up table (Look Up Table)
10 Oscillator R External resistance element

Claims (16)

Ring oscillator means for enabling output of a clock signal having a predetermined oscillation frequency by an inverter circuit configuration;
Frequency adjustment control means for outputting a frequency adjustment signal according to the output oscillation frequency of the clock signal;
Based on the output frequency adjustment signal, a control signal for controlling the drive current of the inverter circuit is variably controlled and supplied to the ring oscillator means, whereby the output oscillation frequency of the clock signal is set to a desired output oscillation frequency. An oscillation device having current control means for enabling adjustment control. The frequency adjustment control means includes
Counting means for counting the number of clocks in a predetermined period of the output oscillation frequency;
Storage means for storing the count number and a digital value for variably controlling the control signal, and storing the digital value corresponding to the count number from the storage means for the frequency adjustment. The oscillation device according to claim 1 which outputs as a signal.   The counting means receives a reference signal that is at an “H” level or “L” level for a certain period, and sets the number of clocks of the output oscillation frequency within the “H” level period or “L” level period of the reference signal. The oscillation device according to claim 2, which counts as the count number.   The oscillation device according to claim 2, wherein the storage unit includes a lookup table in which the count number and the digital value are associated with each other.   The oscillation device according to claim 4, wherein the storage unit further includes a rewrite unit that enables rewriting of a stored value of the lookup table.   In the ring oscillator means, an odd number of CMOS type inverter circuits are connected in series, and the output part of the last stage inverter circuit is connected to the input part of the first stage inverter circuit. The oscillation device according to claim 1, wherein each constant current source for supplying each drive current is connected to each side. Each of the constant current sources comprises transistor means,
7. The oscillation device according to claim 6, wherein the current control means is capable of controlling the drive current of the inverter circuit by outputting the control signal to a control terminal of the transistor means. The current control means includes
The high potential side transistor means of the constant current source and the mutual control terminals are connected to each other, the high potential side mirror transistor means constituting the current mirror circuit, and the low potential side transistor means of the constant current source and the mutual control terminals of each other Are connected to each other to form a current mirror circuit.
8. The oscillation circuit according to claim 7, further comprising a mirror current adjustment unit that enables adjustment control of a mirror current flowing in at least one of the current mirror circuits according to a digital value of the frequency adjustment signal. First control transistor means is connected in series to the low potential side of the high potential side mirror transistor means,
Second control transistor means is connected in series to the high potential side of the low potential side mirror transistor means, and the control terminals of the low potential side mirror transistor means and the first control transistor means are connected to each other,
9. The oscillation device according to claim 8, wherein the mirror current adjustment unit is capable of adjusting and controlling a control voltage of the second control transistor means in accordance with a digital value of the frequency adjustment signal. The mirror current adjusting unit is
Adjustment transistor means having a low potential side drive terminal connected to the control terminal of the second control transistor means;
The switch means for switching the control terminal of the adjustment transistor means to either the high potential side drive terminal or the low potential side drive terminal according to the digital value of the frequency adjustment signal. The oscillation device described.   11. The oscillation device according to claim 10, wherein a plurality of sets of adjustment transistor means and switch means are arranged in parallel by the number of bits of the digital value.   The oscillation device according to claim 1, wherein the current control unit includes a resistance element that can variably control the control signal according to a resistance value. The current control means includes
The second control transistor means and other adjustment transistor means connected to each other's control terminals;
A resistor element connected in series to the low potential side drive terminal of the other adjustment transistor means, and connected so that the potential at the connection point is linked to the potential of the control terminal;
The oscillation device according to claim 9, wherein the control signal can be variably controlled according to a resistance value of the resistance element.   The oscillation device according to claim 12 or 13, wherein the resistance element is built in the current control means, or is replaced with another resistance element having a different resistance value. An oscillation frequency adjustment method for an oscillation device for adjusting and controlling an output oscillation frequency of an oscillation device including a ring oscillator,
A reference signal which becomes “H” level or “L” level for a certain period is input to the counting means, and the number of clocks of the output oscillation frequency is counted within the “H” level period or “L” level period of the reference signal. Counting step,
An oscillation frequency adjustment method for an oscillation device, comprising: a frequency adjustment step for adjusting and controlling a control signal from the current control means for controlling the drive current of the ring oscillator to the ring oscillator based on a digital value corresponding to the counted number .   An electronic apparatus provided with a drive circuit that generates a drive signal using the oscillation device according to claim 1.

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