JPH07221560A - Operational amplifier, semiconductor integrated circuti incorporated with the same and usage thereof - Google Patents

Abstract

PURPOSE:To reduce a mean dissipated current without decreasing an operating speed in the case of charging a capacitive load by setting a DC bias voltage at a high level and reducing the current through an output circuit after charging the load with the voltage set at a low level and increase the current. CONSTITUTION:A bias voltage generating circuit 40 outputs a DC bias voltage VB at a high or a low level in response to a binary switching control signal. Then the switching control signal is at a high level while an output voltage VO is rising and a current I2 flowing a PMOS transistor(TR) 21 whose source connects to a high level power supply VDD and whose gate receives a voltage VB is increased more than that when the switching control signal is at a low level thereby quickening a change in the voltage VO with respect to a change in an input voltage VI. After a capacitive load CL is charged, the switching control signal goes to a low level and a voltage VDD-VB is decreased, the current I2 is reduced more than that when the switching control signal is at a high level. Thus, the operation of a voltage follower circuit OP with respect to the load CL is quickened and an average dissipated current is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier used in a data driver for an LCD panel and the like, a semiconductor integrated circuit incorporating the same, and a method of using the same.

[0002]

2. Description of the Related Art An operational amplifier composed of CMOS has a C
Since it can be mixedly mounted on a MOS digital IC chip, it has been widely used in place of an operational amplifier composed of a bipolar transistor. CM
Although the OS circuit generally consumes less current, an analog data driver for a TFT-type LCD panel in which a large number of operational amplifiers are built in one IC consumes relatively large current and requires low power consumption.

FIG. 12 shows a voltage follower circuit OP in which an inverting input terminal VI (-) and an output terminal VO of an operational amplifier composed of CMOS are connected. In this circuit OP, the output circuit 20 is connected to the subsequent stage of the differential amplifier circuit 10.
The differential amplifier circuit 10 includes pMOS transistors 11 to 13
And nMOS transistors 14 and 15. nMO
The S-transistor 14 and the nMOS transistor 15 form a mirror circuit.
And the drain current of the nMOS transistor 15 have the same value I1. The output circuit 20 is p
It is composed of a MOS transistor 21 and an nMOS transistor 22. The nMOS transistor 30 is connected between the gate of the nMOS transistor 22 and the ground wiring VSS. The DC bias voltage VB from the bias voltage generation circuit 40 is applied to both gates of the pMOS transistors 11 and 21. A conventional configuration of the bias voltage generating circuit is shown in FIG.

The bias voltage generating circuit 40A is a pMOS.
It is composed of a transistor 41, a resistor 42, pMOS transistors 43 and 44, and an inverter 45. When the output enable signal OE is high level, pMO
S-transistor 43 is off, pMOS transistor 44
Is turned on, the gate of the pMOS transistor 41 is electrically connected to the drain of the pMOS transistor 41 via the pMOS transistor 44, and the pMOS transistor 41 is turned on.
Functions as a diode. Even if the power supply wiring potential VDD fluctuates and the current IB flowing through the resistor 42 fluctuates to some extent,
Due to the voltage-current characteristics of this diode, the voltage VDD-
VB becomes almost constant. Therefore, the power supply wiring potential VDD
The gate-source voltage of the pMOS transistors 11 and 21 of FIG.
The transistors 11 and 21 function as a constant current source.

The output voltage VO taken from the drain of the pMOS transistor 21 is
Feedback control is performed so that it becomes equal to the input voltage VI applied to the gate of No. 3. Voltage follower circuit O
When a capacitive load CL shown by a dotted line, for example, a liquid crystal pixel is connected to the output terminal of P, the change of the output voltage VO with respect to the input voltage VI becomes as shown in FIG. FIG. 14 (A)
, The waveform of the output voltage VO = VO1 is the capacitive load C
When L is large or the drain current I2 of the pMOS transistor 21 is small, the waveform of the output voltage VO = VO2 is when the capacitive load CL is small or the current I2 is large. The change in the output voltage VO when the input voltage VI falls is not significantly affected by the size of the capacitive load CL because the ON resistance of the nMOS transistor 22 is relatively small.

In FIG. 13, when the output enable signal OE is set to the low level, the pMOS transistor 4
3 is on, pMOS transistor 44 is off and V
B = VDD, and the pMOS transistor 21 is turned off. Further, the nMOS transistor 30 is turned on and the nMOS transistor 22 is turned off by the signal XOE obtained by inverting the output enable signal OE by the inverter 45. As a result, the output of the voltage follower circuit OP is in a high impedance state.

[0007]

When the capacitive load CL is a liquid crystal pixel, it is necessary to increase the current I2 in order to increase the display speed. However, the current I2 is applied to the nMOS transistor 22 even after the charging of the capacitive load CL is completed.
Since the current flows through to the ground wiring VSS side, current consumption increases.

In the normal mode, the output enable signal OE is set to a low level and the current I2 is set to 0 each time charging of the capacitive load CL is completed to reduce current consumption. Drain-gate parasitic capacitance and nMOS
By the oscillation preventing capacitor (not shown) connected between the drain and gate of the transistor 22, the capacitive load CL
Such a method is not preferable because the voltage between the terminals changes and the display quality deteriorates.

In view of the above problems, an object of the present invention is to provide an operational amplifier in which the average current consumption is reduced and the operation speed is increased, a semiconductor integrated circuit incorporating the same, and a method of using the same.

[0010]

In the first aspect of the present invention, for example, as shown in FIG. 12, a differential amplifier circuit 10 for amplifying and outputting a voltage between a pair of input terminals, and a high potential side power supply wiring. DC bias voltage VB lower by a certain value than the potential of VDD
, A pMOS transistor 21 whose source is connected to the high potential side power supply line VDD and whose gate is applied with the DC bias voltage VB, and a source which is connected to the low potential side power supply line VSS and whose drain is pM.
An output circuit 2 including an nMOS transistor 22 connected to the drain of the OS transistor 21 and having a gate to which a voltage according to one output voltage of the differential amplifier circuit 10 is applied.
In the operational amplifier having 0 and the bias voltage generating circuit 40, as shown in FIGS.
The high-level or low-level DC bias voltage VB is output according to the binary switching control signal DRV.

According to the first aspect of the present invention, the DC bias voltage V is applied when the capacitive load is charged by the switching control signal DRV.
B is set to a low level to increase the current to the capacitive load, and after this charging is completed, the DC bias voltage VB is set to a high level to reduce the output circuit through current to reduce the average current consumption without decreasing the operating speed. Can be reduced.

In the first aspect of the first aspect of the present invention, for example, as shown in FIG. 1, in the bias voltage generating circuit 40B, the gate and drain of the MOS transistor are connected (directly or indirectly connected, for example, turned on). Connected to the cathode of the diode 41 and connected to the cathode of the diode 41 at one end thereof (directly or indirectly, directly or indirectly, for example, through the turned-on pMOS transistor) to extract the DC bias voltage VB. The end is connected to the low potential side power supply wiring VSS and the switching control signal D
And a variable resistor 42, 46 whose resistance value is switched by turning on / off the switch element 46 by RV. The bias voltage generation circuit 40C shown in FIG. 3 is also included in this first mode. The description in the parentheses is the same below.

In the first mode, when the resistance of the variable resistance is switched to the smaller one by the switching control signal DRV, the current flowing through the diode 41 increases, which causes the voltage VDD-VB to rise, as shown in FIG. P of the output circuit 20
The current flowing through the MOS transistor increases. In the second aspect of the first invention, for example, as shown in FIG. 4, in the bias voltage generation circuit 40D, the switching element 47 is turned on / off by the switching control signal DRV, and the gate and drain of the MOS transistor are connected. The gate width or gate length of the configured diode is substantially switched, the anode is connected to the high-potential-side power supply wiring VDD, and the variable diodes 41A, 41B, 47 from which the DC bias voltage VB is taken out from the cathode and one end are A resistor 42 connected to the cathode of the variable diode and the other end of which is connected to the low potential side power supply wiring VSS. The bias voltage generation circuit 40E shown in FIG. 6 is also included in this second mode.

In the second mode, when the gate width of the variable diode is substantially narrowed or the gate length is substantially shortened by the switching control signal DRV, the current flowing through the resistor decreases and the voltage VDD-VB rises. Output circuit 2 shown in FIG.
The current flowing through the pMOS transistor of 0 increases. Further, since the change in the drain voltage with respect to the change in the drain current of the diode-connected MOS transistor is relatively small, the switching control signal D in the second mode is more than that in the first mode.
The DC bias voltage VB can be largely changed by the RV, and as a result, it is possible to reduce the average current consumption more than that in the first mode without lowering the operating speed of the operational amplifier in which the bias voltage generating circuit 40D is used. Become.

In the third aspect of the first aspect of the present invention, for example, as shown in FIG. 7, in the bias voltage generating circuit 40F, the switching element 47 is turned on / off by the switching control signal DRV,
The gate width or gate length of the diode configured by connecting the gate and drain of the MOS transistor is substantially switched, the anode is connected to the high potential side power supply wiring VDD, and the DC bias voltage VB is taken out from the cathode. The variable diodes 41A, 41B, and 47, one end of which is connected to the cathode of the variable diode and the other end of which is connected to the low-potential-side power supply wiring VSS, the switch control signal DRV turns on / off the switch element 46 to switch the resistance value. Variable resistors 42 and 46, and switching of variable diodes 41A, 41B and 47 and variable resistors 42 and 4
The combination with the switching of 6 is a combination in which the DC bias voltage VB changes most greatly by the switching control signal DRV. The bias voltage generation circuit 40G shown in FIG. 8 is also included in this third mode.

In the third mode, the combination makes it possible to change the DC bias voltage VB by the switching control signal DRV to a greater extent than in the second mode, whereby the operational amplifier using the bias voltage generation circuit 40F is used. It is possible to reduce the average current consumption more than that in the second mode without lowering the operating speed. Book second
In the semiconductor integrated circuit of the present invention, as shown in, for example, FIG. 10 and FIG.
One bias voltage generation circuit 40X is commonly used for a plurality of sets of 0 and the output circuit 20, and the output end of each operational amplifier is connected to the inverting input end to form voltage followers OP1 to OPn. , At least one set of the plurality of operational amplifiers is incorporated.

In the second invention, since the number of the voltage follower circuits OP1 to OPn is large, the effect that the average current consumption can be reduced without lowering the operation speed becomes remarkable. In the method of using the semiconductor integrated circuit according to the third aspect of the present invention, for example, in FIG. 10, capacitive load is connected to the voltage follower output terminals O1 to On of the semiconductor integrated circuit IC1, and the voltage follower input terminals ei1 to ei are connected.
When the voltage of n is raised from a low level to a high level to charge the capacitive load, the DC bias voltage VB is set to a low level by the switching control signal DRV to speed up the charging of the capacitive load, and the switching control is performed after the charging is completed. The level of the signal DRV is inverted and the DC bias voltage VB is set to a high level to reduce the current flowing through the output circuit 20 shown in FIG.

As a result, the effect of the second invention is realized.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 shows a bias voltage generating circuit 40B of the first embodiment used in the operational amplifier of FIG.

The pMOS transistor 41 is a pMOS transistor 41 whose gate and drain are always turned on during normal use.
The diode is connected through the MOS transistor 44, the source that is the anode is connected to the power supply line VDD, and the DC bias voltage VB is taken out from the drain that is the cathode through the pMOS transistor 44.
This drain is connected to the ground wiring VSS via the resistor 42. The resistor 42 has a resistor 42A in the middle thereof.
And a resistor 42B, and an intermediate portion thereof is connected to the ground wiring VSS via the nMOS transistor 46. The gate of the nMOS transistor 46 has pMO
A switching control signal DRV for switching the resistance between the drain of the S transistor 41 and the ground wiring VSS is supplied. The resistor 42 and the nMOS transistor 46 constitute a variable resistor. Curve P, straight lines A and B in FIG.
Indicate the voltage-current characteristics of the pMOS transistor 41, the resistor 42A, and the resistor 42, respectively.

PMOS transistor 44 and power supply wiring V
The pMOS transistor 43 connected between the DD and the source of the pMOS transistor 44, and the input terminal is the pMOS transistor 43.
It is connected to the gate of transistor 43 and the output end is pMOS
Inverter 45 connected to the gate of transistor 44
As in the case of the circuit of FIG. 13 described above, is to put the output of the circuit of FIG. 12 in a high impedance state when the output enable signal OE supplied to the input terminal of the inverter 45 is set to a low level. Is. The output enable signal OE is always set to a high level during normal use, and is set to a low level only when the output of the operational amplifier is in a high impedance state. These points also apply to the following examples.

Next, the operation of the bias voltage generating circuit 40B configured as described above will be described. When the switching control signal DRV is set to the high level while the output enable signal OE is at the high level, the nMOS transistor 46 is turned on,
The value of the variable resistance decreases and the current flowing through the pMOS transistor 41 increases compared to when the switching control signal DRV is low level. As a result, the drain voltage VDD-VB of the pMOS transistor 41 changes from V1 to V2 in FIG. 2, for example. The voltage VB-VSS is V4 when the nMOS transistor 46 is off, and the nMOS transistor 4
When 6 is turned on, it becomes V3. Between the voltages V1 to V4,
The relationship of V1 + V4 = V2 + V3 = VDD is established.

When the bias voltage generating circuit 40B is used as the bias voltage generating circuit 40 in FIG. 12 and a capacitive load CL is connected to the output end of the voltage follower OP as shown by the dotted line, switching control for changes in the input voltage VI is performed. Signal D
FIG. 9 shows how to apply RV and changes in DC bias voltage VB and output voltage VO. Switching control signal DRV
Is kept at a high level while the output voltage VO rises, whereby the current I2 flowing through the pMOS transistor 21 in FIG. 12 increases more than when the switching control signal DRV is at a low level, and the input voltage VI The change of the output voltage VO with respect to the change becomes faster. Further, after the charging of the capacitive load CL is completed, the switching control signal DRV is set to the low level, the voltage VDD-VB drops from VBH to VBL,
As a result, the current I2 decreases more than when the switching control signal DRV is at the high level. Therefore, according to the first embodiment, the voltage follower circuit OP for the capacitive load CL is provided.
Operation becomes faster and the voltage follower circuit OP
The average current consumption of is reduced.

The output end of the voltage follower circuit OP is LC
When connected to the data electrode of the D panel and used as a data driver, the charging / discharging period for the liquid crystal pixels is predetermined, and accordingly the switching control signal DR is set accordingly.
V can be defined as shown in FIG. The falling speed of the output voltage VO does not depend much on the level of the switching control signal DRV, but the switching control signal DRV is set to a high level at the falling of the output voltage VO, and the capacitive load C
The discharge of L may be accelerated. When it is not necessary to control the output of the operational amplifier by high impedance, the pMOS transistors 43 and 44 and the inverter 4
5 may be omitted. These points are the same for the other examples below.

[Second Embodiment] FIG. 3 shows an operational amplifier bias voltage generating circuit 40C of a third embodiment. In FIG. 1, the resistors 42A and 42B are connected in series, whereas in FIG. 3, the resistors 42A and 42B are connected in parallel. An nMOS transistor 46 is connected between the resistor 42B and the ground wiring VSS, a variable resistor is configured by the resistors 42A, 42B and the nMOS transistor 46, and the resistance value is switched by turning on / off the nMOS transistor 46. When the switching control signal DRV is set to a high level, the nMOS transistor 46 turns on,
The value of the variable resistance decreases and the current flowing through the pMOS transistor 41 increases compared to when the switching control signal DRV is low level.

The bias voltage generating circuit 40C of FIG. 3 is shown in FIG.
The operation of the voltage follower circuit OP when used as the second bias voltage generation circuit 40 is shown in FIG. 9 as in the first embodiment. [Third Embodiment] FIG. 4 shows a bias voltage generating circuit 40D for an operational amplifier according to the third embodiment.

In this circuit, the value of the resistor 42 is fixed, and the characteristics of the diode composed of a plurality of MOS transistors are variable. That is, the pMOS transistor 4
The sources of 1A and the pMOS transistor 41B are both connected to the power supply wiring VDD, and the gates of the pMOS transistor 41A and the pMOS transistor 41B are both connected to the drain of the pMOS transistor 41A via the pMOS transistor 44 that is normally turned on during normal use. p
The DC bias voltage VB is taken out from the drain of the MOS transistor 41A through the pMOS transistor 44. The drain of the pMOS transistor 41B is pMO
PMOS transistor 41 via S transistor 47
It is connected to the drain of A, and this drain is connected to the ground wiring VSS via the resistor 42.

PMOS transistors 41A, 41B, 4
When the switching control signal DRV is at a low level, the variable diode made of 7 turns on the pMOS transistor 47 and connects the pMOS transistor 41A to the pMOS transistor 41B in parallel. For example, the characteristics of the pMOS transistor 41A and the pMOS transistor 41B are Are equal to each other, the gate width of the pMOS transistor becomes equal to twice that when the switching control signal DRV is at the high level. The voltage of this variable diode −
The current characteristics are represented by curves P and Q in FIG. 5 when the pMOS transistor 47 is off and on, respectively. The straight line A is the voltage-current characteristic of the resistor 42.

When the pMOS transistor 47 is on, the current flowing through the resistor 42 is larger than when it is off, and the DC bias voltage VB with respect to the ground wiring VSS becomes higher. The voltages VB-VSS and VDD-VB when the pMOS transistor 47 is off are shown in FIG.
In the case of V1 and V4, the pMOS transistor 47
When turned on, these are V2 and V3 in FIG. 5, respectively.

As is clear from a comparison between FIG. 2 and FIG. 5, the circuit of FIG. 4 can change the DC bias voltage VB more largely by the switching control signal DRV than the circuit of FIG. This is a diode-connected MOS
This is because the change in the drain voltage with respect to the change in the drain current of the transistor is relatively small. A voltage follower circuit O when the bias voltage generation circuit 40D of FIG. 4 is used as the bias voltage generation circuit 40 of FIG.
The operation of P is shown in FIG. 9 as in the first embodiment.

[Fourth Embodiment] FIG. 6 shows an operational amplifier bias voltage generating circuit 40E of a fourth embodiment. In FIG. 4, the pMOS transistor 41B is connected in parallel to the pMOS transistor 41A to form a variable diode, whereas in FIG. 6, the pMOS transistor 41B is connected in series to the pMOS transistor 41A to form a variable diode. . The characteristic of the variable diode is pM connected in parallel to the pMOS transistor 41B.
It is switched by turning on / off the OS transistor 47.

When the pMOS transistor 47 is on, the current flowing through the resistor 42 is larger than when it is off, and the DC bias voltage VB with respect to the ground wiring VSS becomes higher. The operation of the voltage follower circuit OP when the bias voltage generating circuit 40D of FIG. 6 is used as the bias voltage generating circuit 40 of FIG. 12 is shown in FIG. 9 as in the first embodiment.

[Fifth Embodiment] FIG. 7 shows a bias voltage generating circuit 40F for an operational amplifier according to the fifth embodiment. This circuit is a combination of the variable resistance of FIG. 1 and the variable diode of FIG. 4, and the combination of the value of the variable resistance and the characteristics of the variable diode determines the difference between the high level and the low level of the DC bias voltage VB. In order to further increase the average current consumption without decreasing the operating speed of the operational amplifier in which the bias voltage generating circuit 40F is used,
The combination is such that the change of the DC bias voltage VB becomes larger by the switching control signal DRV.

That is, the gate of the nMOS transistor 46 is connected to the gate of the pMOS transistor 47, the switching control signal DRV is supplied to this, and the switching control signal D
When RV is at a low level, the nMOS transistor 46 is turned off and the pMOS transistor 47 is turned on, while the resistor 42A and the resistor 42B are connected in series, which makes the switching control signal DRV more variable than when it is at a high level. The current flowing through the resistance tends to decrease, while on the other hand, pMO
When the pMOS transistor 41B is connected in parallel to the S transistor 41A, the current flowing through the pMOS transistor 41A tends to be lower than when the switching control signal DRV is at a high level. Therefore, the curve P in FIG.
As is clear from the shape of
Drain voltage VDD-VB of the MOS transistor 41A
Changes more greatly.

The bias voltage generating circuit 40F of FIG. 7 is shown in FIG.
The operation of the voltage follower circuit OP when used as the second bias voltage generation circuit 40 is shown in FIG. 9 as in the first embodiment. [Sixth Embodiment] FIG. 8 shows a bias voltage generating circuit 40G for an operational amplifier according to the sixth embodiment.

The variable diode of this circuit has the same structure as the variable diode of FIG. 7, but the structure of the variable resistor is different from that of FIG. The value of the variable resistance is the value of the resistance 42 plus the on-resistance of the nMOS transistor 46 determined by the gate voltage. The gate of the nMOS transistor 46 is connected to the gate of the nMOS transistor 56, the gate of the nMOS transistor 56 is connected to its drain, and the source of the nMOS transistor 56 is connected to the ground wiring VSS via the resistor 52. nMOS transistors 46 and 56 and resistors 42 and 5
The mirror circuit 60 is composed of 2 and. When the nMOS transistor 46 and the nMOS transistor 56 have the same characteristics and the resistors 42 and 52 have the same value,
The current flowing through the resistor 42 becomes equal to the current flowing through the resistor 52.

The current flowing through the resistor 52 is the switching control signal D
It can be switched by RV. That is, nM
The drain of the OS transistor 56 is connected to the power supply wiring VDD via the resistor 52B and the resistor 52A, and the resistor 52A
The point between the resistor 52B and the resistor 52B is connected to the power supply wiring VDD through the pMOS transistor 57, and the switching control signal DRV
Is inverted by the inverter 61 and supplied to the gate of the pMOS transistor 57.

When the switching control signal DRV is at a low level, p
Since the MOS transistor 57 is turned off, the current flowing through the resistor 52 becomes smaller than that when the switching control signal DRV is at the high level, and thus the current flowing through the resistor 42 becomes smaller, while the pMOS transistor 47 is turned on. pMOS transistor 41A has pMOS transistor 4
1B is connected in parallel, and the switching control signal DRV
The current flowing through the pMOS transistor 41A tends to be smaller than that at a high level. Therefore, the change in the DC bias voltage VB with respect to the switching control signal DRV is the same as in the fifth embodiment.

The bias voltage generating circuit 40G of FIG. 8 is shown in FIG.
The operation of the voltage follower circuit OP when used as the second bias voltage generation circuit 40 is shown in FIG. 9 as in the first embodiment. [First Application Example of Operational Amplifier] FIG. 10 shows a CMOS semiconductor integrated circuit IC to which the bias voltage generation circuit 40X is applied.
1 is shown. The bias voltage generation circuit 40X includes the first to the first
It is one of the sixth embodiments, and the voltage follower circuit O
It is commonly used for P1 to OPn. The voltage follower circuits OP1 to OPn are configured by removing the bias voltage generation circuit 40 from the voltage follower circuit OP of FIG. The output terminals O1 to On of the CMOS semiconductor integrated circuit IC1 are respectively voltage follower circuits OP.
Output terminals 1 to OPn, which are connected to, for example, data electrodes of a TFT type LCD panel. Voltage follower circuit O
Voltages ei1 to ein corresponding to display data are supplied to the non-inverting input terminals of P1 to OPn. Input voltage ei1
The relationship between any one of ein and the switching control signal DRV is
The relationship is the same as the relationship between the input voltage VI and the switching control signal DRV in FIG.

Since the CMOS semiconductor integrated circuit IC1 has a large number of voltage follower circuits OP1 to OPn,
The effect of reducing the average current consumption without reducing the operating speed becomes significant. [Second Application Example of Operational Amplifier] FIG. 11 shows a CMOS semiconductor integrated circuit IC2 to which the bias voltage generating circuits 40X and 40Y are applied. The bias voltage generation circuit 40Y has the same configuration as the bias voltage generation circuit 40X. This CM
In the OS semiconductor integrated circuit IC2, the bias voltage generating circuit 40X that supplies the DC bias voltage VB1 to the odd-numbered voltage follower circuits OP1, OP3, ..., OPn-1 is commonly used, and the even-numbered voltage follower circuits are used. DC bias voltage V for the circuits OP2, ..., OPn
The bias voltage generation circuit 40Y that supplies B2 is commonly used.

In the operation of the LCD panel driving circuit, the charge / discharge phase may be shifted by 180 degrees between adjacent data electrodes in order to prevent display flicker. In this case, and when the data electrode of the LCD panel is taken out on one side, the CMOS semiconductor integrated circuit IC2 is used and the phases of the switching control signals DRV1 and DRV2 supplied to the bias voltage generating circuits 40X and 40Y are shifted by 180 degrees from each other. As a result, the current consumption of the CMOS semiconductor integrated circuit can be reduced.

The present invention also includes a CMOS semiconductor integrated circuit having three or more built-in configurations in which one bias voltage generating circuit is commonly used for a plurality of voltage follower circuits.

[0043]

As described above, in the operational amplifier according to the first aspect of the present invention, the DC bias voltage is set to the low level when the capacitive load is charged by the switching control signal to increase the current to the capacitive load. After the charging is completed, the DC bias voltage is set to a high level to reduce the output circuit through current, and thus it is possible to reduce the average current consumption without lowering the operation speed.

According to the second aspect of the first aspect of the present invention, since the change in the drain voltage with respect to the change in the drain current of the diode-connected MOS transistor is relatively small, the DC bias voltage is controlled by the switching control signal more than in the first aspect. There is an effect that the average current consumption can be reduced more than that in the first mode without reducing the operation speed of the operational amplifier.

According to the third aspect of the first aspect of the present invention, the variable diode and the variable resistor are connected in series, and the combination of the switching of the variable diode and the switching of the variable resistor is controlled by the switching control signal. Is a combination that changes the most, so that the DC bias voltage can be changed more greatly by the switching control signal than in the second mode, thereby lowering the operating speed of the operational amplifier in which the bias voltage generating circuit is used. Therefore, it is possible to reduce the average current consumption more than the second mode.

According to the semiconductor integrated circuit of the second aspect of the present invention, since the number of voltage follower circuits is large, the effect that the average current consumption can be reduced without lowering the operating speed becomes remarkable. According to the method of using the semiconductor integrated circuit of the third invention, the effects of the second invention are realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a bias voltage generating circuit for an operational amplifier according to a first embodiment of the present invention.

FIG. 2 is a voltage-current characteristic diagram showing the operation of the circuit of FIG.

FIG. 3 is a bias voltage generating circuit diagram for an operational amplifier according to a second embodiment of the present invention.

FIG. 4 is a bias voltage generating circuit diagram for an operational amplifier according to a third embodiment of the present invention.

5 is a voltage-current characteristic diagram showing the operation of the circuit of FIG.

FIG. 6 is a bias voltage generation circuit diagram for an operational amplifier according to a fourth embodiment of the present invention.

FIG. 7 is a bias voltage generation circuit diagram for an operational amplifier according to a fifth embodiment of the present invention.

FIG. 8 is a circuit diagram of a bias voltage generating circuit for operational amplifier according to a sixth embodiment of the present invention.

9 is a voltage waveform diagram showing the operation of the circuit of FIG. 12 to which the bias voltage generating circuits of the first to sixth embodiments of the present invention are applied.

FIG. 10 is a first semiconductor integrated circuit diagram to which the bias voltage generation circuit of this embodiment is applied.

FIG. 11 is a second semiconductor integrated circuit diagram to which the bias voltage generation circuit of this embodiment is applied.

FIG. 12 is a diagram showing a voltage follower circuit composed of CMOS.

13 is a diagram of a conventional bias voltage generation circuit used in FIG.

FIG. 14 is an input / output voltage waveform diagram of a conventional voltage follower circuit with respect to a capacitive load.

[Description of Reference Signs] 10 differential amplifier circuits 11 to 13, 21, 41, 41A, 41B, 43, 4
4, 47, 57 pMOS transistor 14, 15, 22, 30, 46, 56 nMOS transistor 16, 60 Mirror circuit 20 Output circuit 40, 40A to 40G, 40X, 40Y Bias voltage generating circuit OP, OP1 to OPn Voltage follower circuit IC1, IC2 CMOS semiconductor integrated circuit

Claims (6)

[Claims] 1. A differential amplifier circuit (10) for amplifying and outputting a voltage between a pair of input terminals, and a DC bias voltage (VB) which is lower than the potential of a high potential side power supply wiring (VDD) by a constant value. A bias voltage generation circuit (40) and a pMOS transistor (2) whose source is connected to the high potential side power supply line and whose gate is applied with the DC bias voltage.
1), an nMOS transistor (22) having a source connected to the low-potential-side power supply line, a drain connected to the drain of the pMOS transistor, and a gate to which a voltage corresponding to one output voltage of the differential amplifier circuit is applied. In an operational amplifier having an output circuit (20) provided with, and a bias voltage generation circuit having a binary switching control signal (DR
An operational amplifier which outputs a high level or a low level of the DC bias voltage according to V). 2. The bias voltage generating circuit (40B)
Is connected to the gate and drain of the MOS transistor,
A diode (41) from which the DC bias voltage (VB) is taken out from the cathode, one end of which is connected to the cathode of the diode and the other end of which is connected to the low-potential-side power supply wiring (VSS) by the switching control signal (DRV). Variable resistors (42, 46) whose resistance value is switched by turning on / off the switch element (46)
The operational amplifier according to claim 1, further comprising: 3. The bias voltage generation circuit (40D)
Is switched by the switching control signal (DRV).
7) is turned on / off to substantially switch the gate width or the gate length of the diode configured by connecting the gate and drain of the MOS transistor, and the anode is connected to the high potential side power supply wiring (VDD). A variable diode (41A, 41B, 47) from which the DC bias voltage (VB) is taken out from the cathode; and one end connected to the cathode of the variable diode and the other end connected to the low potential side power supply wiring (VSS). Resistance (4
The operational amplifier according to claim 1, further comprising: 4. The bias voltage generation circuit (40F)
Is switched by the switching control signal (DRV).
7) is turned on / off to substantially switch the gate width or the gate length of the diode configured by connecting the gate and drain of the MOS transistor, and the anode is connected to the high potential side power supply wiring (VDD). A variable diode (41A, 41B, 47) from which the DC bias voltage (VB) is taken out from the cathode; and one end connected to the cathode of the variable diode and the other end connected to the low potential side power supply wiring (VSS). A variable resistor (42, 46) whose resistance value is switched by turning on / off the switching element by the switching control signal, and the combination of switching of the variable diode and switching of the variable resistor is the switching control. The operational amplifier according to claim 1, wherein the combination is such that the DC bias voltage changes most greatly depending on a signal. 5. A plurality of any one of claims 1 to 4
The operational amplifier described in No. 1 is configured such that one bias voltage generation circuit (40X) is commonly used for a plurality of sets of the differential amplifier circuit (10) and the output circuit (20), and each operation is performed. The output end of the amplifier is connected to the inverting input end to form a voltage follower (OP1 to OPn),
A semiconductor integrated circuit (IC1), wherein at least one set of the plurality of operational amplifiers is built in. 6. The semiconductor integrated circuit (IC according to claim 5,
Connect a capacitive load to the voltage follower output ends (O1 to On) of 1) and connect the voltage follower input ends (ei1 to ei).
When the voltage of n) is raised from a low level to a high level to charge the capacitive load, the DC bias voltage (VB) is set to a low level by the switching control signal (DRV) to charge the capacitive load. A method of using a semiconductor integrated circuit, comprising increasing the speed and inverting the level of the switching control signal after completion of charging to set the DC bias voltage to a high level to reduce the current flowing through the output circuit (20).