KR200212557Y1 - Standard time collection device for personal computer - Google Patents

Abstract

The present invention relates to a PC standard time correcting device, and more particularly, to a PC standard time correcting device that enables accurate time setting of a PC. To this end, the present invention provides a first step of setting a standard time and obtaining a time error after a predetermined time, a second step of obtaining a time and time error by repeating the operation of the first step a predetermined number of times, and the time obtained in the above. And a fourth step of adjusting the division ratio according to the error, and a fourth step of automatically setting the standard time by correcting the time error with the adjusted division ratio.

Description

PC Standard Time Compensator {STANDARD TIME COLLECTION DEVICE FOR PERSONAL COMPUTER}

The present invention is to ensure accurate time setting at a low price, and more particularly to a PC standard time correction device that can overcome the limitations caused by component errors by correcting as much as the error of the crystal (Crystal).

1 is a configuration diagram of a Real Time Clock (RTC) adjusting device of a conventional PC (PC), as shown in this, when a frequency of 32.768KHz generated in the crystal (X-TAL) input oscillates a predetermined clock An oscillator 10 to divide the clock generated in the oscillator 10, a divider 20 for outputting the clock, and a register for generating and outputting seconds, minutes, hours, days, months, years, etc. in response to the divided clocks; Inputting the counter 30 and time and date information to be adjusted by the user, or outputting the time and date information generated in the register and the counter 30 to the PC (PC) side Bus interface 40, and Control unit 50 for receiving the data input through the bus interface 40 to generate a control signal for the necessary operation, and the address of the register for setting the time, date, etc. by the control signal generated from the control unit 50 Is composed of an address register 60 for adjusting the?.

Referring to the prior art configured in this way in detail as follows.

When the crystal (X-TAL) generates a frequency of 32.768KHz for the clock to the oscillator 10, the oscillator 10 generates a predetermined clock according to the frequency All.

The clock generated by the oscillator 10 is divided by the divider 20 and transmitted to the register and the counter 30.

Thereafter, the register and counter 30 generate a time such as seconds, minutes, and hours or a date such as day, month, and year. Transfer to bus interface 40, the The bus interface 40 displays the current time, date, and the like in a place where time information is required such as a display time window of the PC through the data line SDA.

The data line (SCL) provides information for the user to set the time or date. Input to bus interface 40.

Then The bus interface 40 transmits time or date information to the controller 50, and the controller 50 transmits an address selection signal for time or date to the address register 60.

The address register 60 controls the counters of the register and the counter 30 to adjust the time.

Adjust the time or date It is displayed on the display time window of the PC through the bus interface 40 and the data line SDA to confirm whether the time desired by the user is correct.

Adjust the time or date in the same way as above.

However, in the prior art as described above, it is the accuracy of the crystal that determines the exact time in the RTC (Real Time Clock). In other words, if the crystal oscillation frequency is higher than 32.768KHz, the clock will be faster and if it is low, it will be slow. However, when an error occurs in the crystal, there is a problem that cannot be correct. If the crystal has an error of + 5PPM, the watch

Has an error of.

Accordingly, an object of the present invention for solving the conventional problems as described above is to provide a PC standard time correction device to provide the accuracy at a relatively low cost in the device that requires an accurate clock or frequency.

Another object of the present invention is to provide a PC standard time correction device for correcting a component error of a crystal to overcome the limitation of the error.

1 is a configuration diagram for a Real Time Clock (RTC) control device of a conventional PC (PC).

2 is a block diagram of a PC standard time correction device of the present invention.

3 is an operation flowchart for a PC standard time correction method of the present invention.

***** Explanation of symbols for the main parts of the drawing *****

100: oscillator 200: divider

300: registers and counters 400: Bus interface

500: time correction unit 600: address register

700: Frequency adjuster X-TAL: Crystal

The present invention for achieving the above object is divided into a divider for outputting the clock of the oscillator according to the frequency oscillated in the crystal, the register and counter for setting the time, date, etc. using the clock, and the register and the counter To input standard time or transmit current time information to user A standard time adjusting device comprising a bus interface, comprising: a frequency adjusting unit for adjusting a load capacitor value of the Krystal to a large or small value according to a control signal; A time correction unit for obtaining a time error received through a bus interface, and outputting a control signal for adjusting a capacitor value of the frequency adjusting unit and a division control signal for adjusting a frequency division ratio of the frequency divider according to the time error; It features.

Hereinafter, with reference to the accompanying drawings in detail as follows.

3 is an operation flowchart of the PC standard time correction method of the present invention, as shown in the first step in which the user sets the standard time after the initial clock setting, and the current time after a predetermined time after setting the standard time And a second step of detecting a time error, a third step of adjusting a division ratio according to the detected current time and time error, and a fourth time of accurately adjusting the standard time by counting the standard time using the adjusted division ratio. Consists of steps.

PC standard time correction device of the present invention for performing the method consisting of each step is, as shown in Figure 2, the oscillator for generating a predetermined clock by the frequency generated in the crystal (X-TAL) ( 100), the divider 200 for dividing and outputting the clock generated by the oscillator 100, and the hour, minute, second, day, month, year, etc. using the clock output from the divider 200. A register and counter 300 for generating time information of the frequency, a frequency adjusting unit 700 for changing the frequency by adjusting the size of the load capacitors C1 and C2 of the crystal X-TAL, and the register and counter. Read the current time at 300 to display to the user or transfer the time input by the user to the register and the counter 300 Bus interface 400, and To obtain an error between the current time and the standard time read through the bus interface 400, a control signal for frequency adjustment and a control signal for adjusting the frequency division ratio of the frequency divider 200 to the frequency adjuster 700 for error correction. And a time correcting unit 500 for outputting the respective values, and an address register 600 for selecting and outputting an address to be adjusted by the time correcting unit 500.

When described in detail with respect to the operation and effect of the present invention configured as described above.

The user inputs the standard time through the data line (SCL) to set the standard time, and inputs the standard time. The bus interface 400 receives and transfers the data to the time correction unit 500, the registers, and the counters 300, respectively.

At this time, when the crystal (X-TAL) generates a frequency of 32.768KHz and supplies it to the oscillator 100, the oscillator 100 generates a predetermined clock and provides it to the divider 200.

Then, the time correction unit 500 outputs a control signal to the divider 200 to divide at a basic division ratio to set a standard time, and selects an address of a register corresponding to a time and outputs it to the address register 600. do.

Then, the register and counter 300 counts the divided clocks transmitted from the divider 200. Hours, minutes, and seconds are generated according to the standard time transmitted through the bus interface 400, and the generated hours, minutes, and seconds are written to a register corresponding to an address transferred from the address register 600.

Thus, the register and the counter 300 store the time information written in the corresponding register. The data is transferred to the data line of the SDA through the bus interface 400, and also to the time correction unit 500.

Thereafter, the data is transferred to the display time window of the PC of the data line of the SDA to display the standard time for the user to view.

The time correction unit 500 compares the standard time input by the user with the set current time to obtain a time error.

At this time, if the time displayed in the display time window of the PC is earlier or later than the standard time, the user wants to adjust the time through the data line SCL. Transfer to bus interface 400.

Then The bus interface 400 transmits the time to be adjusted to the register and the counter 300 and the time corrector 500, respectively.

Accordingly, the time correction unit 500 compares the standard time input by the user, the time to be adjusted, and the current time read from the register and the counter 300, respectively, and finds the time and time error to be adjusted. Then, the control signal is output to the frequency adjusting unit 700 and the divider 200 to correct the time error.

That is, the time correction unit 500 outputs a control signal in a high state to the frequency adjuster 700 because the time must be delayed if the current time is earlier than the standard time.

Accordingly, the transistor Q1 of the frequency adjusting unit 700 is turned on by the control signal in the high state, and the load capacitors C1 and C2 applied to the crystal X-TAL are made large by the capacitor C3. The frequency generated at (X-TAL) becomes high.

When the frequency is high, the clock output from the oscillator 100 is slowed down, and the frequency division ratio corresponding to the slowed down clock is output from the time corrector 500 to the divider 200.

Therefore, the divider 200 outputs a clock divided by a predetermined division ratio to the register and the counter 300.

If the current time is slower than the standard time, the time should be faster, and thus the control signal in the low state is output to the frequency adjusting unit 700.

Accordingly, since the transistor Q1 of the frequency adjusting unit 700 is turned off by the low state control signal, the load capacitor C2 applied to the crystal X-TAL is not operated. Thus, the crystal X-TAL Since the capacitor is applied only to the load capacitor (C1) operates, the frequency is lowered.

When the lowered frequency is input to the oscillator 100, the oscillator 100 generates a faster clock as the divider 200. At this time, when the frequency division unit 500 adjusts the frequency division ratio of the frequency divider 200 to the clock speed, the frequency divider 200 divides the clock and supplies the divided frequency to the register and the counter 300.

The register and counter 300 then counts clocks to produce a time at which the error is corrected.

As described in detail above, the present invention has an effect of correcting a component error so that an accurate time can be set.

Claims (2)

A divider that divides and outputs the clock of the oscillator according to the frequency oscillated in the crystal, registers and counters for setting time, date, etc. using the clock, and inputs standard time or registers current time information with the registers and counters. To send to the user A standard time adjusting device comprising a bus interface, comprising: a frequency adjusting unit for adjusting a load capacitor value of the Krystal to a large or small value according to a control signal; A time correction unit for obtaining a time error received through a bus interface, and outputting a control signal for adjusting a capacitor value of the frequency adjusting unit and a division control signal for adjusting a frequency division ratio of the frequency divider according to the time error; PC standard time correction device. The apparatus of claim 1, wherein the frequency adjuster comprises a capacitor connected in parallel with a load capacitor of a crystal, and a transistor connected in series with the capacitor to determine whether to operate the capacitor.