JP2017151034A - Oscillation device, temperature sensor, integrated circuit, and time piece - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation device, a temperature sensor, an integrated circuit, and a time piece with which it is possible to suppress an increase in circuit scale and reduce the absolute value of an outputted oscillation frequency.SOLUTION: Provided is an oscillation circuit 20 comprising a CR oscillation circuit 30, a frequency division circuit 40 for dividing the frequency of an oscillation signal outputted from the CR oscillation circuit 30. The CR oscillation circuit 30 has a temperature characteristic that makes it possible to detect a temperature on the basis of the frequency of the oscillation signal outputted from the CR oscillation circuit 30. The frequency division circuit 40 is configured with one stage or more of frequency dividers connected in series for dividing the frequency of an inputted signal, the number of stages of frequency dividers is set so that the frequency of a signal outputted from the frequency division circuit 40 is included in a preset frequency range.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an oscillation device including a CR oscillation circuit, a temperature sensor, an integrated circuit, and a timepiece.

  Conventionally, a CR oscillation circuit has a problem that the resistance value and the capacitance value change due to variations in resistance and capacitor constituting the circuit and the frequency fluctuates. For this reason, the thing which suppressed the fluctuation | variation of the oscillating frequency by the manufacture variation of a resistor or a capacitor | condenser is known by switching a resistor and a capacitor | condenser with a switch so that a desired frequency characteristic may be obtained (for example, patent document 1, 2).

Incidentally, elements such as resistors and capacitors constituting the CR oscillation circuit have temperature characteristics, and the oscillation frequency of the oscillation circuit also has temperature characteristics. Therefore, the oscillation frequency of the CR oscillation circuit oscillates at a frequency corresponding to the temperature, and the temperature can be measured by detecting this oscillation frequency. Therefore, the CR oscillation circuit can be used as a temperature sensor. Thus, in order to realize a highly accurate temperature sensor using the CR oscillation circuit, a characteristic in which the oscillation frequency changes linearly with respect to temperature is required.
In addition, when the obtained oscillation frequency is a high value, there is a possibility that it cannot be processed inside the IC due to restrictions of the circuit. For this reason, it is preferable that the absolute value of the oscillation frequency output from the CR oscillation circuit is small.

JP 63-116505 A JP 2005-167927 A

However, in order to reduce the absolute value of the oscillation frequency in the CR oscillation circuits described in Patent Documents 1 and 2, a capacitor having a large capacitance value and a resistor having a large resistance value are required. There is a problem that increases.
In the CR oscillation circuit, in order to adjust the oscillation frequency, the parasitic capacitance of a switch for switching a capacitor and a resistor, and the on-resistance of a transistor used for the switch or the like affect the oscillation frequency.
For this reason, it is difficult to create a high-accuracy temperature sensor by creating a CR oscillation circuit that has a characteristic that the oscillation frequency varies linearly with temperature and has a small absolute value of the oscillation frequency. It was.

  An object of the present invention is to provide an oscillation device, a temperature sensor, an integrated circuit, and a timepiece that can suppress an increase in circuit scale and can reduce the absolute value of an output oscillation frequency.

  The oscillation device of the present invention includes a CR oscillation circuit and a frequency dividing circuit that divides the oscillation signal output from the CR oscillation circuit, and the CR oscillation circuit outputs an oscillation signal output from the CR oscillation circuit. The frequency divider circuit has a temperature characteristic capable of detecting a temperature, and the frequency divider circuit is configured by connecting one or more stages of frequency dividers that divide an input signal in series, and the frequency divider The number of stages is characterized in that the frequency of the signal output from the frequency divider circuit is set to the number of stages at which the frequency falls within a preset frequency range.

According to the present invention, the CR oscillation circuit has a temperature characteristic capable of detecting the temperature based on the frequency of the oscillation signal. That is, the CR oscillation circuit is configured to have a temperature characteristic in which the frequency of the oscillation signal changes almost linearly with respect to the temperature, so that the temperature can be detected based on the frequency of the oscillation signal.
In addition, a frequency dividing circuit that divides the oscillation signal output from the CR oscillation circuit is provided, and the frequency of the signal output from the frequency dividing circuit is set in advance for the number of stages of the frequency dividing circuit. Since the number of stages corresponding to the frequency included in the frequency range is set, the absolute value of the oscillation frequency can be reduced and can be set to a frequency that can be calculated inside the IC.
In addition, since the absolute value of the oscillation frequency can be reduced by the frequency dividing circuit, it is not necessary to incorporate elements such as capacitors and resistors for reducing the absolute value of the oscillation frequency in the CR oscillation circuit. Expansion can be suppressed.

  An oscillation device according to the present invention includes a CR oscillation circuit, a frequency divider that divides an oscillation signal output from the CR oscillation circuit, a frequency divider control unit that controls the operation of the frequency divider, and a signal selection unit. The CR oscillation circuit has a temperature characteristic capable of detecting temperature based on the frequency of the oscillation signal output from the CR oscillation circuit, and the frequency divider circuit receives the input signal. One or more stages of frequency dividers are connected in series, and the frequency divider circuit control unit outputs the number of stages of the frequency dividers operating in the frequency divider circuit from the frequency divider circuit. The frequency of the signal is controlled to the number of stages that is a frequency included in a preset frequency range, and the signal selection unit includes an oscillation signal output from the CR oscillation circuit, and a signal output from the frequency divider circuit Is selected and output.

According to the present invention, the CR oscillation circuit has a temperature characteristic capable of detecting the temperature based on the frequency of the oscillation signal. That is, the CR oscillation circuit is configured to have a temperature characteristic in which the frequency of the oscillation signal changes almost linearly with respect to the temperature, so that the temperature can be detected based on the frequency of the oscillation signal.
Further, a frequency dividing circuit that divides the oscillation signal output from the CR oscillation circuit is provided, and a signal output from the frequency dividing circuit by the frequency dividing circuit control unit determines the number of stages of the frequency dividing circuit. Is set to the number of stages at which the frequency is included in the preset frequency range, the absolute value of the oscillation frequency can be reduced, and the frequency that can be calculated inside the IC can be set.
In addition, since the absolute value of the oscillation frequency can be reduced by the frequency dividing circuit, it is not necessary to incorporate elements such as capacitors and resistors for reducing the absolute value of the oscillation frequency in the CR oscillation circuit. Expansion can be suppressed.
Furthermore, since the number of stages of the frequency divider can be set by the frequency divider circuit control unit, the number of stages of the frequency divider can be easily set according to the temperature characteristics of the CR oscillation circuit. Furthermore, since the frequency divider control unit can stop unnecessary frequency dividers, the power consumption of the frequency divider can be suppressed.

A temperature sensor according to the present invention includes the oscillation device.
According to the present invention, since the temperature can be detected based on the frequency of the oscillation signal output from the CR oscillation circuit and frequency-divided by the frequency dividing circuit, the oscillation device can be used as a temperature sensor. In particular, in the frequency dividing circuit, the oscillation frequency can be lowered so as to be within a predetermined frequency range, so that arithmetic processing can be performed in the IC, and the IC can easily perform processing based on temperature.

An integrated circuit according to the present invention includes a vibrator oscillation circuit that oscillates a vibrator, a frequency adjustment circuit that performs frequency adjustment of the vibrator oscillation circuit, the oscillation device, and a frequency of an oscillation signal output from the oscillation device. And a control circuit that calculates a correction amount based on the frequency adjustment circuit and controls the frequency adjustment circuit according to the calculated correction amount.
According to the present invention, since the above-described oscillation device is provided, the same effect as that of the oscillation device can be obtained. In addition, a frequency adjustment circuit that adjusts the frequency of a vibrator oscillation circuit that oscillates a vibrator such as a crystal vibrator is provided, and the control circuit corresponds to the frequency of the oscillation signal output from the oscillation device, that is, the detected value of temperature. Since the correction amount is calculated based on the value and the frequency adjustment circuit is controlled in accordance with the correction amount, temperature compensation can be performed on the vibrator whose oscillation frequency changes depending on the temperature. Therefore, the frequency of the oscillation signal output from the vibrator oscillation circuit can be kept constant even when the temperature changes.

The timepiece of the present invention includes the integrated circuit, a reference signal generation circuit that generates a reference signal based on the oscillation signal output from the vibrator oscillation circuit, and a time that is driven based on the reference signal and displays the time And a display unit.
According to the present invention, since the integrated circuit is used, an oscillation signal having a constant frequency can be output from the vibrator oscillation circuit without being affected by temperature. Therefore, the reference signal generation circuit can generate a reference signal that is not affected by temperature changes, and can drive a time display unit based on this reference signal to provide a timepiece with high time display accuracy.

It is a block diagram which shows the structure of the electronic timepiece which concerns on one Embodiment of this invention. It is a block diagram which shows the structure of the oscillation apparatus in the said embodiment. It is a figure which shows the structure of the frequency divider circuit control part in the said embodiment. It is a figure which shows the structure of the signal selection part in the said embodiment. It is a timing chart explaining operation | movement of the oscillation apparatus in the said embodiment. It is a figure which shows the frequency characteristic of the oscillation signal output from the CR oscillation circuit in the said embodiment. It is a figure which shows the frequency characteristic of the signal output from each of the frequency divider of the frequency divider circuit in the said embodiment.

An embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a configuration of an electronic timepiece 1 according to an embodiment of the present invention.
[Electronic clock]
As shown in FIG. 1, the electronic timepiece 1 includes a power source 2, a timepiece IC 3 that is driven by the power source 2, a crystal unit 4, and a step motor 5.

  The power source 2 is composed of a primary battery or a secondary battery. When a secondary battery is used, a generator for charging the secondary battery may be provided in the electronic timepiece 1 or may be configured to be charged from the outside of the electronic timepiece 1. As the generator, a clock generator such as a solar cell or a generator that generates electricity with a rotating weight can be used.

The crystal resonator 4 corresponds to the resonator of the present invention, and is a passive element that causes oscillation with high frequency accuracy using the piezoelectric effect of crystal. The crystal unit 4 has a frequency-temperature characteristic in which the oscillation frequency changes with temperature.
The step motor 5 drives hands such as a minute hand, a second hand, and an hour hand through a train wheel (not shown). Therefore, the electronic timepiece 1 of the present embodiment is an analog timepiece.

  The watch IC 3 corresponds to an integrated circuit of the present invention, and a vibrator oscillation circuit 11 that oscillates the crystal vibrator 4, a reference signal generation circuit 12, a motor pulse forming circuit 13, a control circuit 15, and a frequency adjustment. The circuit 16 and the oscillation device 20 are provided.

The oscillator oscillation circuit 11 oscillates the crystal oscillator 4 to generate a source oscillation signal having a predetermined frequency (for example, 32.768 kHz), and outputs the source oscillation signal to the reference signal generation circuit 12.
The reference signal generation circuit 12 is configured by a reference signal generation frequency divider circuit including, for example, a 15-stage frequency divider (flip-flop), and sequentially divides the source oscillation signal to generate a 1 Hz reference signal.
The motor pulse forming circuit 13 forms and outputs a motor pulse for driving the step motor 5 using the signal output from the reference signal generating circuit 12.
This motor pulse is output to the step motor 5, the step motor 5 is driven, and the pointer is driven via the train wheel. Accordingly, in the electronic timepiece 1, the time display unit 6 that displays the time based on the reference signal is configured to include the motor pulse forming circuit 13, the step motor 5, a train wheel and a pointer not shown.

[Configuration of Oscillator]
As illustrated in FIGS. 1 and 2, the oscillation device 20 includes a CR oscillation circuit 30, a frequency divider circuit 40, a frequency divider circuit control unit 50, and a signal selection unit 60.

[Configuration of CR oscillation circuit]
The CR oscillation circuit 30 is a circuit composed of a capacitor (C) and a resistor (R), and outputs an oscillation signal having a preset frequency Fo. As shown in FIG. 2, the CR oscillation circuit 30 of the present embodiment includes three stages of inverters 31, 32, and 33, and Pch field effect transistors (MOSFETs) that constitute the inverters 31 to 33 of the respective stages. : Metal-oxide-semiconductor field-effect transistor) 311, 321, 331 are connected to the power supply voltage VDD, and Nch field-effect transistors 312, 322, 332 are connected to the ground voltage VSS. .
A resistor 341 and a capacitor 351 are connected in series to the drain of the inverter 31. A connection point 361 between the resistor 341 and the capacitor 351 is connected to the gate of the inverter 32.
A resistor 342 and a capacitor 352 are connected in series to the drain of the inverter 32, and a connection point 362 therebetween is connected to the gate of the inverter 33.
A resistor 343 and a capacitor 353 are connected in series to the drain of the inverter 33, and a connection point 363 therebetween is connected to the gate of the inverter 31 and further connected to the waveform shaping circuit 35.
One end of each of the capacitors 351 to 353 is connected to the ground voltage VSS. An output from the waveform shaping circuit 35 is an output of an oscillation signal oscillated by the CR oscillation circuit 30 and is input to the frequency dividing circuit 40 and the signal selection unit 60.

  The frequency Fo of the oscillation signal of the CR oscillation circuit 30 is determined by the charge / discharge speed of the charges charged in the capacitors 351 to 353. Therefore, the oscillation frequency is determined by the values of the drains of the inverters 31 to 33, the resistors 341 to 343 connected in series between the ground voltage VSS, and the capacitors 351 to 353.

  Since elements such as resistors 341 to 343 and capacitors 351 to 353 constituting the CR oscillation circuit 30 have temperature characteristics, the frequency Fo of the oscillation signal output from the CR oscillation circuit 30 varies depending on the temperature. By utilizing this temperature characteristic, the CR oscillation circuit 30 can be used as a temperature sensor. The temperature characteristics of the frequency of the oscillation signal output from the CR oscillation circuit 30 will be described later.

[Configuration of frequency divider]
The frequency divider circuit 40 is a circuit that divides and outputs the oscillation signal input from the CR oscillation circuit 30. As shown in FIG. 2, the frequency dividing circuit 40 is configured by connecting one or more stages in series. For example, in the present embodiment, four frequency dividers 41, 42, 43, and 44 connected in series are provided. Have. The plurality of frequency dividers 41 to 44 are constituted by flip-flops FF.
The oscillation signal A output from the CR oscillation circuit 30 is input to the clock terminal CL of the first-stage frequency divider 41, and the oscillation signal A is divided by 1/2 from the output terminal Q of the frequency divider 41. Signal B is output. The signal B output from the output terminal Q of the frequency divider 41 is input to the clock terminal CL and the signal selection unit 60 of the frequency divider 42. The signal C output from the output terminal Q of the frequency divider 42 is input to the clock terminal CL of the frequency divider 43 and the signal selection unit 60. The signal D output from the output terminal Q of the frequency divider 43 is input to the clock terminal CL of the frequency divider 44 and the signal selection unit 60. The signal E output from the output terminal Q of the frequency divider 44 is input to the signal selection unit 60.
Therefore, signals B to E obtained by dividing the oscillation signal A having the frequency Fo into 1/2, 1/4, 1/8, and 1/16 are output from the output terminals Q of the frequency dividers 41 to 44, respectively. The

Each frequency divider 41 to 44 is provided with a reset terminal R. Reset signals RA, RB, RC, and RD are input to the reset terminals R from the frequency divider control unit 50, respectively.
The frequency dividers 41 to 44 of the present embodiment are set so as to be stopped when the reset signals RA to RD are H level signals and to be operated when they are L level signals.

[Configuration of frequency divider control unit]
FIG. 3 is a diagram illustrating a configuration of the frequency divider circuit control unit 50.
The frequency divider circuit control unit 50 controls the operation of the frequency divider circuit 40. Control signals X, Y, and Z output from the control circuit 15 are input to the frequency divider control unit 50. The frequency divider circuit control unit 50 controls the frequency divider circuit 40 by outputting reset signals RA to RD to the frequency dividers 41 to 44 based on the control signals X, Y, and Z.
Such a frequency divider control unit 50 includes two NOT circuits 51 and 52, four NAND gates 531 to 534, and four NOR gates 541 to 544.

  The control signal X is input to the NOT circuit 51, and the control signal Y is input to the NOT circuit 52. Control signals X and Y are input to the NAND gate 531, the control signal X and the output of the NOT circuit 52 are input to the NAND gate 532, and the output of the NOT circuit 51 and the control signal Y are input to the NAND gate 533. The outputs of the NOT circuits 51 and 52 are input to the NAND gate 534.

The NOR gate 541 receives the control signal Z and the output of the NAND gate 531 and outputs a reset signal RA.
The NOR gate 542 receives the control signal Z and the output of the NAND gate 532, and outputs a reset signal RB.
The NOR gate 543 receives the control signal Z and the output of the NAND gate 533, and outputs a reset signal RC.
The NOR gate 544 receives the control signal Z and the output of the NAND gate 534, and outputs a reset signal RD.

[Configuration of signal selector]
FIG. 4 is a diagram illustrating a configuration of the signal selection unit 60.
The signal selection unit 60 includes an oscillation signal A having a frequency Fo output from the CR oscillation circuit 30, signals B to E output from each of the frequency dividers 41 to 44, and a reset output from the frequency division circuit control unit 50. Signals RA to RD and control signal Z output from control circuit 15 are input, and a signal selected from signals A to E is output.
The signal selection unit 60 includes five NAND gates 61 to 65 and a NAND gate 66.

The NAND gate 61 receives the oscillation signal A having the frequency Fo [Hz] output from the CR oscillation circuit 30 and the reset signal RA output from the frequency divider control unit 50.
The NAND gate 62 receives the signal B having the frequency Fo / 2 [Hz] output from the frequency divider 41 and the reset signal RB output from the frequency divider control unit 50.
The NAND gate 63 receives a signal C having a frequency Fo / 4 [Hz] output from the frequency divider 42 and a reset signal RC output from the frequency divider control unit 50.

The NAND gate 64 receives a signal D having a frequency Fo / 8 [Hz] output from the frequency divider 43 and a reset signal RD output from the frequency divider control unit 50.
The NAND gate 65 receives the signal E having the frequency Fo / 16 [Hz] output from the frequency divider 44 and the control signal Z output from the control circuit 15.
The NAND gate 66 receives the outputs of the NAND gates 61 to 65.

Hereinafter, the frequency division control process executed by the frequency divider circuit control unit 50 and the signal selection unit 60 will be described with reference to the timing chart of FIG.
In FIG. 5, A to E are signals output from the frequency dividers 41 to 44 of the CR oscillation circuit 30 and the frequency dividing circuit 40 as described above. RA to RD are reset signals output from the frequency divider control unit 50. X, Y, and Z are control signals output from the control circuit 15, and SENO is a signal output from the signal selection unit 60.
The frequency divider control unit 50 is controlled by the control signals X, Y, and Z output from the control circuit 15, and outputs reset signals RA to RD to the frequency dividers 41 to 44. Control the behavior. Further, the control signal Z and the reset signals RA to RD are also output to the signal selection unit 60, and the signal output from the oscillation device 20 is selected in conjunction with the control of the frequency dividing circuit 40.

[Selection control of oscillation signal A with frequency Fo]
The control circuit 15 sets the control signal X to the H level, the control signal Y to the H level, and the control signal Z to the L level when outputting the signal of the frequency Fo from the signal selection unit 60. As shown in FIG. 4, the NAND gate 531 of the frequency divider control unit 50 outputs an L level signal because an H level signal is input to each of two input terminals. On the other hand, each of the NAND gates 532 to 534 outputs an H level signal because an L level signal is input to at least one of the input terminals.
Since the NOR gate 541 receives the L level signal from the NAND gate 531 and the control signal Z is also at the L level, the NOR gate 541 outputs an H level signal as the reset signal RA.
On the other hand, since the other NOR gates 542 to 544 receive the H level signal from the NAND gates 532 to 534 and the control signal Z is at the L level, the other NOR gates 542 to 544 output the L level signal as the reset signals RB to RD.

  The first-stage frequency divider 41 of the frequency dividing circuit 40 stops because the H level reset signal RA is input to the reset terminal R, and the output signal B of the output terminal Q is maintained at the L level. The frequency dividers 42 to 44 stop operating because no clock signal is input to the clock terminal CL, and the output signals C to E are also maintained at the L level.

In the signal selection unit 60, as shown in FIG. 4, the NAND gate 61 to which the H level reset signal RA is input to one terminal inverts the oscillation signal A having the frequency Fo [Hz] input to the other terminal. The signal is output to the NAND gate 66.
On the other hand, NAND gates 62 to 65 to which L level reset signals RB to RD and control signal Z are input to one terminal output a signal maintained at H level to NAND gate 66.
Accordingly, the NAND gate 66 outputs a signal obtained by inverting the signal input from the NAND gate 61, that is, the oscillation signal A having the frequency Fo [Hz].

[Selection control of signal B of frequency Fo / 2]
When the control circuit 15 outputs a signal having the frequency Fo / 2 from the signal selection unit 60, the control signal X is set to H level, the control signal Y is set to L level, and the control signal Z is set to L level. In the frequency divider circuit control unit 50, the NAND gate 532 outputs an L level signal because an H level signal is input to each of two input terminals. On the other hand, the NAND gates 531, 533, and 534 each output an H level signal because an L level signal is input to at least one of the input terminals.
Therefore, the NOR gate 542 receives the L level signal from the NAND gate 532 and the control signal Z is also at the L level, and therefore outputs the H level signal as the reset signal RB.
On the other hand, the other NOR gates 541, 543, and 544 receive the H level signal from the NAND gates 531, 533, and 534, respectively, and the control signal Z is at the L level, so that the reset signals RA, RC, and RD are at the L level. Output a signal.

The first-stage frequency divider 41 of the frequency dividing circuit 40 operates because the L level reset signal RA is input to the reset terminal R, and the oscillation signal A of the frequency Fo [Hz] input to the clock terminal CL is supplied. A signal B having a frequency Fo / 2 [Hz] divided by 1/2 is output.
The signal B is input to the clock terminal CL of the frequency divider 42. The frequency divider 42 is stopped by receiving the H level reset signal RB, and is therefore maintained at the L level from the output terminal Q. Output signal C. Therefore, the frequency dividers 43 to 44 stop operating because no clock signal is input to the clock terminal CL, and the output signals D and E are also maintained at the L level.

In the signal selector 60, the NAND gate 62 to which the H level reset signal RB is input to one terminal is obtained by inverting the signal B having the frequency Fo / 2 [Hz] input to the other terminal into the NAND gate. 66.
On the other hand, NAND gates 61 and 63 to 65 to which L level reset signals RA, RC, RD and control signal Z are input to one terminal output signals maintained at H level to NAND gate 66.
Therefore, the NAND gate 66 outputs a signal obtained by inverting the signal input from the NAND gate 62, that is, a signal B having a frequency Fo / 2 [Hz].

[Selection control of signal C of frequency Fo / 4]
When the control circuit 15 outputs a signal having a frequency Fo / 4 from the signal selection unit 60, the control signal X is set to L level, the control signal Y is set to H level, and the control signal Z is set to L level. Then, in the frequency divider control unit 50, only the NAND gate 533 among the NAND gates 531 to 534 outputs an L level signal, and the other NAND gates 531, 532, and 534 output an H level signal. Therefore, the NOR gate 543 outputs an H level reset signal RC, and the other NOR gates 541, 542, and 544 output L level reset signals RA, RB, and RD.

Since the first-stage and second-stage frequency dividers 41 and 42 are operated by inputting the L level reset signals RA and RB, the signal B of the frequency Fo / 2 [Hz] and the frequency Fo / 4 [Hz, respectively. ] Signal C is output.
On the other hand, the third-stage frequency divider 43 is stopped when an H-level reset signal RC is input, and the frequency divider 44 to which no clock signal is input from the frequency divider 43 is also stopped. Therefore, the output signals D and E are maintained at the L level.

In the signal selector 60, the NAND gate 63 to which the H level reset signal RC is input to one terminal is a signal obtained by inverting the signal C having the frequency Fo / 4 [Hz] input to the other terminal. 66.
On the other hand, NAND gates 61 to 65 to which reset signals RA, RB, RD and control signal Z at L level are input to one terminal output signals maintained at H level to NAND gate 66.
Therefore, the NAND gate 66 outputs a signal obtained by inverting the signal input from the NAND gate 63, that is, a signal C having a frequency Fo / 4 [Hz].

[Selection control of signal D of frequency Fo / 8]
When the control circuit 15 outputs a signal having a frequency Fo / 8 from the signal selection unit 60, the control signal X is set to L level, the control signal Y is set to L level, and the control signal Z is set to L level. Then, in the frequency divider control unit 50, only the NAND gate 534 among the NAND gates 531 to 534 outputs an L level signal, and the other NAND gates 531 to 533 output an H level signal. For this reason, the NOR gate 544 outputs an H level reset signal RD, and the other NOR gates 541 to 543 output L level reset signals RA, RB, RC.

Since the first-stage to third-stage frequency dividers 41 to 43 are operated by receiving L level reset signals RA, RB, and RC, the signal B and the frequency Fo / 4 respectively. [Hz] signal C and frequency Fo / 8 [Hz] signal D are output.
On the other hand, the frequency divider 43 at the fourth stage is stopped by receiving the reset signal RD of H level, and the output signal E is maintained at L level.

In the signal selection unit 60, the NAND gate 64 to which the H level reset signal RD is input to one terminal is a signal obtained by inverting the signal D having the frequency Fo / 8 [Hz] input to the other terminal. 66.
On the other hand, NAND gates 61 to 63, 65 to which L level reset signals RA, RB, RC, and control signal Z are input to one terminal output signals maintained at H level to NAND gate 66.
Therefore, the NAND gate 66 outputs a signal obtained by inverting the signal input from the NAND gate 64, that is, a signal D having a frequency Fo / 8 [Hz].

[Selection control of signal E of frequency Fo / 16]
When the control circuit 15 outputs a signal having a frequency Fo / 16 from the signal selection unit 60, the control signal X is set to L level, the control signal Y is set to L level, and the control signal Z is set to H level. Then, in the frequency divider circuit control unit 50, the NOR gates 541 to 544 output the L level reset signals RA to RD because the H level control signal Z is input to one terminal.
For this reason, all the frequency dividers 41 to 44 are operated by receiving the L level reset signals RA to RD, so that the signal B having the frequency Fo / 2 [Hz] and the signal having the frequency Fo / 4 [Hz], respectively. C, a signal D having a frequency Fo / 8 [Hz] and a signal E having a frequency Fo / 16 [Hz] are output.

In the signal selection unit 60, the NAND gate 65 to which the H level control signal Z is input to one terminal is a signal obtained by inverting the signal E having the frequency Fo / 16 [Hz] input to the other terminal. 66.
On the other hand, NAND gates 61 to 64 to which L level reset signals RA to RD are input to one terminal output a signal maintained at H level to NAND gate 66.
Therefore, the NAND gate 66 outputs a signal obtained by inverting the signal input from the NAND gate 65, that is, a signal E having a frequency Fo / 16 [Hz].

As described above, the frequency dividing circuit control unit 50 and the signal selection unit 60 are controlled by the control signals X, Y, and Z output from the control circuit 15, and only a signal having a predetermined frequency (Fo to Fo / 16) is controlled. Can be selected and output from the oscillation device 20. Therefore, for example, when the oscillation device 20 is used as a temperature sensor, a signal having the most suitable frequency (for example, Fo / 2 [Hz]) can be selected and output.
Next, a signal having preferable characteristics when the oscillation device 20 is used as a temperature sensor will be described.

[Temperature characteristics of oscillation signal]
The frequency Fo of the oscillation signal A output from the CR oscillation circuit 30 affects the characteristics of the resistors 341 to 343 and the capacitors 351 to 353 as described above. For this reason, the temperature characteristics of the oscillation frequency change depending on the selection of the components of the resistors 341 to 343 and the capacitors 351 to 353. For example, the temperature characteristic of the oscillation signal F shown in FIG. 6 has low accuracy as a temperature sensor because the change in oscillation frequency with respect to temperature is not linear. That is, the oscillation frequency is substantially the same at temperatures of 30 degrees and 40 degrees, and cannot be determined.
On the other hand, in the temperature characteristic of the oscillation signal A shown in FIG. 6, the change of the oscillation frequency with respect to the temperature is linear, and the accuracy as a temperature sensor is high. However, since the absolute value of the oscillation frequency is high, there is a possibility that the calculation processing of the oscillation frequency cannot be performed inside the timepiece IC 3.
Here, even if it is attempted to adjust the oscillation frequency by switching the resistors 341 to 343 and the capacitors 351 to 353 with a switch in the CR oscillation circuit 30, as described above, a plurality of resistors and capacitors for switching are prepared in the circuit in advance. If this is done, the circuit scale becomes large. In addition, it is difficult to change the setting so that the characteristics of the switch for switching between the resistor and the capacitor affect the oscillation frequency and become a desired characteristic.
Therefore, in the present embodiment, the CR oscillation circuit 30 having a linear characteristic in which the change in the oscillation frequency with respect to temperature is made linear, and the absolute value of the oscillation frequency is the frequency divider 40, the frequency divider control unit 50, as described above. Adjustment is performed by the signal selection unit 60.

The oscillation device 20 divides the oscillation signal by the frequency dividing circuit 40 in order to reduce the absolute value of the oscillation frequency of the CR oscillation circuit 30 that outputs the oscillation signal A having the temperature characteristic shown in FIG.
FIG. 7 is a diagram illustrating the temperature characteristics of the signals B to E output from the frequency dividers 41 to 44, respectively. Here, in order to detect the temperature from the frequency of the output signal of the oscillation device 20, the greater the amount of frequency change with respect to the temperature change, the fewer false detections and the higher the measurement accuracy. On the other hand, as described above, it is preferable that the absolute value of the oscillation frequency is low in order to perform the calculation by the watch IC 3. Therefore, considering the calculation in the watch IC 3 and the accuracy as the temperature sensor, if the frequency of the output signal from the oscillation device 20 is selected to fall within a preset frequency range (for example, 3000 to 8000 Hz). Good.
Therefore, in this embodiment, it is preferable to select the signal B of Fo / 2 [Hz], and when the electronic timepiece 1 is manufactured, the control signal X, Y, Z output from the control circuit 15 and the signal B are output. It is set to do.

The temperature characteristics of the oscillation frequency of the CR oscillation circuit 30 are substantially the same in the CR oscillation circuit 30 of the same series using the same components for the resistors 341 to 343 and the capacitors 351 to 353, and therefore the CR series of the same series. In the oscillation device 20 using the oscillation circuit 30, the settings of the control signals X, Y, and Z in the control circuit 15 may be made common.
However, in the case of obtaining higher accuracy as in the yearly clock, the temperature characteristics of the individual oscillation devices 20 are inspected in consideration of variations of individual components of the resistors 341 to 343 and the capacitors 351 to 353, Depending on the result, control signals X, Y, and Z in the control circuit 15 may be set to determine a signal to be selected.

[Frequency adjustment of oscillator circuit]
A signal output from the oscillation device 20 used as a temperature sensor is input to the control circuit 15. The control circuit 15 detects the temperature of the oscillation device 20 based on the frequency of the input signal. Here, since both the oscillation device 20 and the crystal unit 4 are housed in the case of the electronic timepiece 1, they can be regarded as the same temperature. Therefore, if the temperature of the oscillation device 20 can be detected, the temperature of the crystal unit 4 can be estimated, and the temperature characteristics of the crystal unit 4 can be compensated by controlling the frequency adjustment circuit 16 according to the temperature. .
Note that the control circuit 15 calculates the temperature using a mathematical expression or a table indicating the relationship between the temperature and the oscillation frequency corresponding to the temperature characteristic of the signal B in FIG. A control signal for the frequency adjustment circuit 16 may be output using a table or the like indicating the relationship. The control circuit 15 may perform control using a table in which the relationship between the frequency of the signal output from the oscillation device 20 and the control signal for the frequency adjustment circuit 16 is set directly.

The frequency adjustment circuit 16 compensates for the temperature characteristics of the crystal resonator 4 by changing the load capacity of the resonator oscillation circuit 11. In the reference signal generation circuit 12 which is a frequency dividing circuit, the temperature characteristics of the crystal unit 4 are subjected to a logical slow / fast method in which the time reference signal is expanded and contracted by a necessary correction amount (slow / fast amount) every predetermined correction cycle (slow / fast cycle). May be compensated.
As a result, the reference signal generation circuit 12 can generate a reference signal with a small frequency fluctuation due to the influence of temperature. By displaying the time on the time display unit 6 based on this reference signal, the time display accuracy is high. It can be a timepiece 1. Therefore, the electronic timepiece 1 can be used as an annual difference clock.

[Effect of the embodiment]
The electronic timepiece 1 of the present embodiment described above has the following effects.
The CR oscillation circuit 30 of the present embodiment has a temperature characteristic that can detect the temperature based on the frequency of the oscillation signal A. That is, since the CR oscillation circuit 30 is configured to have a temperature characteristic in which the frequency of the oscillation signal A changes substantially linearly with respect to the temperature, the temperature is determined based on the frequency of the signal output from the oscillation device 20. Can be detected.
Further, a frequency dividing circuit 40 that divides the oscillation signal A output from the CR oscillation circuit 30 is provided, and the frequency dividing circuit control unit 50 determines the number of stages of the frequency dividing circuit 40 to determine the frequency of the output signal. Is set to the number of stages (for example, one stage when the signal B having the frequency Fo / 2 is selected) having a frequency included in a preset frequency range (for example, 3000 to 8000 Hz). The absolute value of the frequency of the output signal can be reduced and can be set to a frequency that can be calculated in the watch IC 3.
Thus, since the absolute value of the oscillation frequency can be reduced by the frequency dividing circuit 40, it is not necessary to incorporate elements such as a capacitor and a resistor for reducing the absolute value of the oscillation frequency in the CR oscillation circuit 30. An increase in the scale of the circuit 30 can be suppressed.

Further, since the number of stages of the frequency divider (for example, one stage when the signal B having the frequency Fo / 2 is selected) can be set by the frequency divider control unit 50, the frequency divider can be set according to the temperature characteristics of the CR oscillation circuit 30. The number of stages 41 to 44 can be easily set. Furthermore, since the frequency divider circuit control unit 50 can stop the unnecessary frequency dividers 41 to 44, the power consumption of the frequency divider circuit 40 can be suppressed.
Specifically, when only the first-stage frequency divider 41 is operated under the control of the frequency divider control unit 50, the other frequency dividers 42 to 44 do not operate. Compared to the case of operation, the power consumed by the frequency divider circuit 40 can be reduced by approximately 45.7%. Further, when only the first-stage and second-stage frequency dividers 41 and 42 operate, the power can be reduced by about 20%, and the first-stage to third-stage frequency dividers 41 to 43 operate. In this case, the power can be reduced by approximately 6.7%.

  Since the temperature can be detected based on the frequency of the signal output from the CR oscillation circuit 30 and divided by the frequency dividing circuit 40, the oscillation device 20 can be used as a temperature sensor. In particular, in the frequency dividing circuit 40, the oscillation frequency can be lowered so as to be within a predetermined frequency range (for example, 3000 to 8000 Hz), so that arithmetic processing can be performed in the timepiece IC3 (control circuit 15). The control circuit 15) can easily perform processing based on temperature.

  A frequency adjustment circuit 16 that adjusts the frequency of the oscillator oscillation circuit 11 that oscillates the crystal oscillator 4 is provided, and the control circuit 15 sets the frequency of the signal output from the oscillation device 20, that is, a value corresponding to the detected value of the temperature. Since the correction amount is calculated on the basis of this and the frequency adjustment circuit 16 is controlled in accordance with the correction amount, temperature compensation can be performed on the crystal unit 4 whose oscillation frequency changes depending on the temperature. Therefore, the frequency of the oscillation signal output from the oscillator oscillation circuit 11 can be kept constant even when the temperature changes.

  Since the electronic timepiece 1 of the present embodiment uses the timepiece IC 3 including the oscillation device 20, the vibrator oscillation circuit 11 can output an oscillation signal having a constant frequency without being affected by temperature. Therefore, the reference signal generation circuit 12 can generate a reference signal that is not affected by the temperature change, and driving the time display unit 6 (step motor 5) based on this reference signal can improve time display accuracy. it can. Therefore, the electronic timepiece 1 can be used as an annual difference clock.

[Modification of Embodiment]
The present invention is not limited to the above-described embodiment, and includes other configurations that can achieve the object of the present invention. The following modifications and the like are also included in the present invention.
In the above embodiment, the frequency dividing circuit 40 includes the four frequency dividers 41 to 44, but the number of frequency dividers is not limited to four.
Further, the configuration of the frequency divider control unit 50 and the signal selection unit 60 is not limited to the configuration of the above embodiment, and may be set as appropriate according to the number of frequency dividers and the like.

  In the above embodiment, the frequency divider circuit control unit 50 and the signal selection unit 60 are provided. However, the present invention is not limited to this. For example, the frequency divider circuit control unit 50 and the signal selection unit 60 may be omitted. In this case, the number of stages of the frequency dividing circuit 40 is the number of stages (for example, two stages) at which the frequency of the signal output from the frequency dividing circuit 40 becomes a frequency included in a preset frequency range (for example, 3000 to 8000 Hz). As long as it is set to. In this case, a signal having a frequency obtained by dividing the frequency of the oscillation signal output from the CR oscillation circuit 30 into 1/4 can always be output. According to this, since the oscillation device 20 does not need to include the frequency dividing circuit control unit 50 and the signal selection unit 60, the circuit configuring the oscillation device 20 can be simplified.

  In the above embodiment, the crystal resonator 4 is provided as the resonator of the present invention. However, the present invention is not limited to this. For example, a ceramic resonator may be provided instead of the crystal resonator 4. Even in this case, the same effects as in the above embodiment can be obtained.

  The integrated circuit of the present invention is not limited to an electronic timepiece, and can be applied to various devices that use a high-accuracy oscillation signal output from the oscillator oscillation circuit 11. For example, the present invention can be applied to various devices that perform operations based on a frequency-divided signal, such as a device with a built-in clock function or a device with a timer function. Specifically, the present invention can be applied to a biological information measuring device such as a portable blood pressure monitor or a pulse meter. Furthermore, the oscillation device and the temperature sensor constituted by the CR oscillation circuit and the frequency dividing circuit of the present invention can be used for a smartphone, a mobile phone, a PHS, a personal computer, an electronic notebook, a portable radio, a toy and the like.

  DESCRIPTION OF SYMBOLS 1 ... Electronic timepiece, 2 ... Power supply, 5 ... Step motor, 11 ... Oscillator oscillation circuit, 12 ... Reference signal generation circuit, 13 ... Motor pulse formation circuit, 15 ... Control circuit, 16 ... Frequency adjustment circuit, 20 ... Oscillator 3 ... IC (integrated circuit) for clock, 30 ... CR oscillation circuit, 31, 32, 33 ... inverter, 311, 312, 321, 322, 331, 332 ... field effect transistor, 341, 342, 343 ... resistance, 35 ... Waveform shaping circuit, 351, 352, 353 ... Capacitor, 361, 362, 363 ... Connection point, 4 ... Crystal resonator (vibrator), 40 ... Frequency divider, 41, 42, 43, 44 ... Frequency divider 50 ... Frequency divider control unit, 6 ... Time display unit, 60 ... Signal selection unit, A, B, C, D, E, F ... Signal, FF ... Flip-flop, Fo ... Frequency, Q ... Output terminal, R ... Set terminal, RA, RB, RC, RD ... reset signal, X, Y, Z ... control signal, VDD ... power supply voltage, VSS ... ground voltage.

Claims (5)

A CR oscillation circuit;
A frequency dividing circuit for frequency-dividing the oscillation signal output from the CR oscillation circuit,
The CR oscillation circuit has a temperature characteristic capable of detecting the temperature based on the frequency of the oscillation signal output from the CR oscillation circuit,
The frequency dividing circuit is configured by connecting one or more stages of frequency dividers for dividing an input signal in series,
The number of stages of the frequency divider is set to the number of stages where the frequency of the signal output from the frequency divider circuit is a frequency included in a preset frequency range. A CR oscillation circuit;
A frequency dividing circuit for frequency-dividing the oscillation signal output from the CR oscillation circuit;
A frequency divider control unit for controlling the operation of the frequency divider;
A signal selector,
The CR oscillation circuit has a temperature characteristic capable of detecting the temperature based on the frequency of the oscillation signal output from the CR oscillation circuit,
The frequency dividing circuit is configured by connecting one or more stages of frequency dividers for dividing an input signal in series,
The frequency divider control unit sets the number of stages of the frequency divider operating in the frequency divider circuit to a number of stages where the frequency of the signal output from the frequency divider circuit is a frequency included in a preset frequency range. Control
The signal selecting unit selects and outputs an oscillation signal output from the CR oscillation circuit and a signal output from the frequency divider circuit.   A temperature sensor comprising the oscillation device according to claim 1. A vibrator oscillation circuit that oscillates the vibrator;
A frequency adjustment circuit for adjusting the frequency of the oscillator oscillation circuit;
The oscillation device according to claim 1 or 2,
An integrated circuit comprising: a control circuit that calculates a correction amount based on a frequency of a signal output from the oscillation device and controls the frequency adjustment circuit according to the calculated correction amount. An integrated circuit according to claim 4;
A reference signal generation circuit that generates a reference signal based on an oscillation signal output from the vibrator oscillation circuit;
A time display unit that is driven based on the reference signal to display the time.

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