JP3018644B2 - Chip composite function device - Google Patents

Chip composite function device

Info

Publication number
JP3018644B2
JP3018644B2 JP3250975A JP25097591A JP3018644B2 JP 3018644 B2 JP3018644 B2 JP 3018644B2 JP 3250975 A JP3250975 A JP 3250975A JP 25097591 A JP25097591 A JP 25097591A JP 3018644 B2 JP3018644 B2 JP 3018644B2
Authority
JP
Japan
Prior art keywords
electrode
primary
thick film
electrodes
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3250975A
Other languages
Japanese (ja)
Other versions
JPH0590072A (en
Inventor
実 曽羽
健 井関
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP3250975A priority Critical patent/JP3018644B2/en
Publication of JPH0590072A publication Critical patent/JPH0590072A/en
Application granted granted Critical
Publication of JP3018644B2 publication Critical patent/JP3018644B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、コンデンサと抵抗とを
直列接続した構成のチップ複合機能素子に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip composite function device having a structure in which a capacitor and a resistor are connected in series.

【0002】[0002]

【従来の技術】近年、電子機器の軽薄短小化に伴い、回
路素子の小型化,薄型化,面実装化が要望され、チップ
抵抗器,チップコンデンサ等のチップ部品の需要が高ま
っており、また、コンデンサと抵抗を直列接続したチッ
プ複合機能素子の需要も高まりつつある。従来、このコ
ンデンサと抵抗を直列接続したチップ複合素子は実用化
されておらず、アルミナ等の絶縁基板に厚膜抵抗体と厚
膜誘電体を直列に形成したものが考えられている。
2. Description of the Related Art In recent years, as electronic devices have become lighter and thinner, there has been a demand for smaller, thinner, and more surface-mounted circuit elements, and the demand for chip components such as chip resistors and chip capacitors has been increasing. The demand for a chip composite function element in which a capacitor and a resistor are connected in series is also increasing. Heretofore, a chip composite device in which a capacitor and a resistor are connected in series has not been put to practical use, and a device in which a thick film resistor and a thick film dielectric are formed in series on an insulating substrate such as alumina has been considered.

【0003】以下に従来のアルミナ基板上に厚膜抵抗体
と厚膜誘電体を直列に形成したチップ複合素子について
説明する。
Hereinafter, a conventional chip composite device in which a thick film resistor and a thick film dielectric are formed in series on an alumina substrate will be described.

【0004】図2は従来のアルミナ基板上に厚膜抵抗体
と厚膜誘電体を直列に形成したチップ複合機能素子の断
面図を示すものである。図2において、1はアルミナ等
からなる方形の絶縁基板である。2,3は一次電極で、
絶縁基板1の両端部に形成されている。4は中間電極で
あり、一次電極2,3の間に設けられている。5は厚膜
抵抗体で、一次電極2と中間電極4との間に形成されて
いる。6は厚膜誘電体で中間電極4上に、お互い一部が
重なり合うように設けられている。7は上部電極で、厚
膜誘電体6上に形成され、一次電極3と接続している。
8は結晶化ガラスで、厚膜誘電体6を覆う。9は非晶質
ガラスで、厚膜抵抗体5と厚膜誘電体6を覆う。10は
端子電極で、一次電極2および3に接続している。11
は端子電極のめっき層で一次電極2,3および端子電極
10を覆う。一般に厚膜誘電体からなるコンデンサは、
信頼性確保のために、このような結晶化ガラスと非晶質
ガラスの2重コートを用いている。
FIG. 2 is a cross-sectional view of a conventional chip composite function element in which a thick film resistor and a thick film dielectric are formed in series on an alumina substrate. In FIG. 2, reference numeral 1 denotes a rectangular insulating substrate made of alumina or the like. 2 and 3 are primary electrodes,
It is formed on both ends of the insulating substrate 1. Reference numeral 4 denotes an intermediate electrode, which is provided between the primary electrodes 2 and 3. Reference numeral 5 denotes a thick-film resistor, which is formed between the primary electrode 2 and the intermediate electrode 4. Reference numeral 6 denotes a thick-film dielectric, which is provided on the intermediate electrode 4 so as to partially overlap each other. Reference numeral 7 denotes an upper electrode formed on the thick film dielectric 6 and connected to the primary electrode 3.
Reference numeral 8 denotes crystallized glass, which covers the thick film dielectric 6. Reference numeral 9 denotes an amorphous glass which covers the thick film resistor 5 and the thick film dielectric 6. Reference numeral 10 denotes a terminal electrode, which is connected to the primary electrodes 2 and 3. 11
Denotes a terminal electrode plating layer that covers the primary electrodes 2 and 3 and the terminal electrode 10. Generally, a capacitor made of a thick film dielectric is
To ensure reliability, a double coat of such crystallized glass and amorphous glass is used.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記の
ように構成されたチップ複合機能素子では、非晶質ガラ
ス9の流れ性が悪い場合、一次電極2,3との間に隙間
ができ、メッキ時に一次電極2,3部と非晶質ガラス9
との界面からメッキ液が浸入し空隙の多い結晶化ガラス
8を通って厚膜コンデンサまで達し絶縁性を劣化させた
り、端子電極10と非晶質ガラス9との間に細い溝がで
きメッキ時にメッキ液が入りメッキ後の洗浄工程で完全
に除去できず信頼性を低下させるという問題点を有して
いた。
However, in the chip composite function device constructed as described above, when the flowability of the amorphous glass 9 is poor, a gap is formed between the primary electrodes 2 and 3 and plating occurs. Sometimes two or three primary electrodes and amorphous glass 9
The plating solution infiltrates from the interface with the substrate and passes through the crystallized glass 8 having many voids to reach the thick film capacitor, thereby deteriorating the insulating properties, or forming a thin groove between the terminal electrode 10 and the amorphous glass 9 to form a thin groove. There is a problem that the plating solution cannot be completely removed in the washing step after plating and the reliability is reduced.

【0006】本発明は上記従来の問題点を解決するもの
で、メッキ工程での絶縁性の劣化を防いだ高信頼性のチ
ップ複合機能素子を提供することを目的とする。
An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a highly-reliable chip multifunction device which prevents deterioration of insulation during a plating process.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するため
に本発明のチップ複合機能素子は、方形の絶縁基板と、
この絶縁基板上に対向する両端部に形成された一対の一
次電極と、この両端の一次電極の間に形成された中間電
極と、この中間電極上に形成された厚膜誘電体と、この
厚膜誘電体上に前記一次電極のうち一方に接続するよう
に形成された上部電極と、前記中間電極と他方の一次電
極との間に形成された厚膜抵抗体と、前記誘電体を被覆
する結晶化ガラスと、この結晶化ガラスおよび前記抵抗
体を被覆する非晶質ガラスとを有し、露出した一次電極
及び前記非晶質ガラスと一次電極との界面を完全に覆う
ように前記絶縁基板の側面に端子電極を設けたものであ
る。
In order to achieve the above object, a chip composite function device according to the present invention comprises a rectangular insulating substrate,
A pair of primary electrodes formed at opposite ends on the insulating substrate, an intermediate electrode formed between the primary electrodes at both ends, a thick-film dielectric formed on the intermediate electrode, An upper electrode formed on the film dielectric so as to be connected to one of the primary electrodes, a thick film resistor formed between the intermediate electrode and the other primary electrode, and covering the dielectric. The insulating substrate having crystallized glass, amorphous glass covering the crystallized glass and the resistor, and completely covering the exposed primary electrode and the interface between the amorphous glass and the primary electrode. Are provided with terminal electrodes on the side surfaces thereof.

【0008】[0008]

【作用】本発明の構成によって、メッキ工程でのメッキ
液の浸入を防止し絶縁性の劣化を抑えた、信頼性の高い
チップ複合機能素子を得ることができる。
According to the structure of the present invention, a highly reliable chip composite function element in which the infiltration of the plating solution in the plating step is prevented and the deterioration of the insulating property is suppressed can be obtained.

【0009】[0009]

【実施例】以下、本発明の一実施例のチップ複合機能素
子について図面を参照しながら説明する。図1は本発明
の本実施例におけるチップ複合機能素子の断面図を示す
ものである。図1において、1はアルミナ等の絶縁基
板、12,13は絶縁基板11の対向する両端に形成さ
れた一次電極、14は絶縁基板11上の一次電極12,
13間に設けられた中間電極、15は一次電極12と中
間電極14間に接続された厚膜抵抗体、16は中間電極
14上に互いに一部重なるように形成された厚膜誘電
体、17は厚膜誘電体16上に一次電極13に接続する
ように設けられた上部電極、18は誘電体16を被覆す
る結晶化ガラス、19は結晶化ガラス18と厚膜抵抗体
15を被覆する非晶質ガラス、20は端子電極、21は
端子電極上に形成されるメッキ層である。端子電極20
は一次電極12,13の露出した部分を完全に覆い、か
つ非晶質ガラス19と一次電極12,13との界面まで
覆うように、絶縁基板1の側面に形成されている。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a multifunctional chip according to an embodiment of the present invention. FIG. 1 is a sectional view of a chip multifunction device according to the present embodiment of the present invention. In FIG. 1, 1 is an insulating substrate such as alumina, 12 and 13 are primary electrodes formed at opposite ends of the insulating substrate 11, and 14 is a primary electrode 12 on the insulating substrate 11.
An intermediate electrode provided between the first and second electrodes; a thick film resistor connected between the primary electrode and the intermediate electrode; a thick film dielectric formed on the intermediate electrode so as to partially overlap each other; Is an upper electrode provided on the thick-film dielectric 16 so as to be connected to the primary electrode 13, 18 is crystallized glass covering the dielectric 16, and 19 is a non-crystallized glass covering the crystallized glass 18 and the thick-film resistor 15. Amorphous glass, 20 is a terminal electrode, and 21 is a plating layer formed on the terminal electrode. Terminal electrode 20
Are formed on the side surfaces of the insulating substrate 1 so as to completely cover the exposed portions of the primary electrodes 12 and 13 and to cover the interface between the amorphous glass 19 and the primary electrodes 12 and 13.

【0010】以上のように構成されたチップ複合機能素
子では、非晶質ガラス20と一次電極12,13との界
面が端子電極20によって完全に覆われているためメッ
キ時にメッキ液の浸入を抑えることができ、厚膜誘電体
16の絶縁性の劣化を防止することができる。
[0010] In the chip composite function device constructed as described above, the interface between the amorphous glass 20 and the primary electrodes 12 and 13 is completely covered by the terminal electrode 20, so that the intrusion of the plating solution during plating is suppressed. This can prevent the insulation of the thick film dielectric 16 from deteriorating.

【0011】[0011]

【発明の効果】以上のように本発明によれば、一次電極
と非晶質ガラスとの界面および一次電極を端子電極で覆
うことにより、メッキ時にメッキ液の浸入を防止しコン
デンサの絶縁性を劣化をさせない、信頼性の高いチップ
複合機能素子を実現することができる。
As described above, according to the present invention, by covering the interface between the primary electrode and the amorphous glass and the primary electrode with the terminal electrode, the infiltration of the plating solution during plating is prevented and the insulation of the capacitor is improved. A highly reliable chip composite function element that does not deteriorate can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例におけるチップ複合機能素子
の断面図
FIG. 1 is a sectional view of a chip multifunction device according to an embodiment of the present invention.

【図2】従来のチップ複合機能素子の断面図FIG. 2 is a cross-sectional view of a conventional chip multifunction device.

【符号の説明】[Explanation of symbols]

1 絶縁基板 12 一次電極 13 一次電極 14 中間電極 15 厚膜抵抗体 16 厚膜誘電体 17 上部電極 18 結晶化ガラス 19 非晶質ガラス 20 端子電極 21 メッキ層 DESCRIPTION OF SYMBOLS 1 Insulating substrate 12 Primary electrode 13 Primary electrode 14 Intermediate electrode 15 Thick film resistor 16 Thick film dielectric 17 Upper electrode 18 Crystallized glass 19 Amorphous glass 20 Terminal electrode 21 Plating layer

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01G 4/14 - 4/42 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01G 4/14-4/42

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】方形の絶縁基板と、この絶縁基板上の対向
する両端部に形成された一対の一次電極と、この両端の
一次電極の間に形成された中間電極と、この中間電極上
に形成された厚膜誘電体と、この厚膜誘電体上に前記一
次電極のうち一方に接続されるように形成された上部電
極と、前記中間電極と他方の一次電極との間に形成され
た厚膜抵抗体と、前記誘電体を被覆する結晶化ガラス
と、この結晶化ガラスおよび前記抵抗体を被覆する非晶
質ガラスとを有し、かつ露出した一次電極及び前記非晶
質ガラスと一次電極との界面を完全に覆うように前記絶
縁基板の側面に端子電極を設けたチップ複合機能素子。
1. A square insulating substrate, a pair of primary electrodes formed at opposite ends on the insulating substrate, an intermediate electrode formed between the primary electrodes at both ends, and A formed thick film dielectric, an upper electrode formed on the thick film dielectric to be connected to one of the primary electrodes, and formed between the intermediate electrode and the other primary electrode. A thick-film resistor, a crystallized glass covering the dielectric, an amorphous glass covering the crystallized glass and the resistor, and an exposed primary electrode and the amorphous glass A chip multifunction device having terminal electrodes provided on side surfaces of the insulating substrate so as to completely cover an interface with the electrodes.
JP3250975A 1991-09-30 1991-09-30 Chip composite function device Expired - Fee Related JP3018644B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3250975A JP3018644B2 (en) 1991-09-30 1991-09-30 Chip composite function device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3250975A JP3018644B2 (en) 1991-09-30 1991-09-30 Chip composite function device

Publications (2)

Publication Number Publication Date
JPH0590072A JPH0590072A (en) 1993-04-09
JP3018644B2 true JP3018644B2 (en) 2000-03-13

Family

ID=17215812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3250975A Expired - Fee Related JP3018644B2 (en) 1991-09-30 1991-09-30 Chip composite function device

Country Status (1)

Country Link
JP (1) JP3018644B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0786504A (en) * 1993-09-10 1995-03-31 Koa Corp Cr network and fabrication thereof

Also Published As

Publication number Publication date
JPH0590072A (en) 1993-04-09

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