JP3136760B2 - Chip type three-terminal capacitor - Google Patents

Chip type three-terminal capacitor

Info

Publication number
JP3136760B2
JP3136760B2 JP04125922A JP12592292A JP3136760B2 JP 3136760 B2 JP3136760 B2 JP 3136760B2 JP 04125922 A JP04125922 A JP 04125922A JP 12592292 A JP12592292 A JP 12592292A JP 3136760 B2 JP3136760 B2 JP 3136760B2
Authority
JP
Japan
Prior art keywords
terminal
film dielectric
electrode
signal line
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP04125922A
Other languages
Japanese (ja)
Other versions
JPH05144663A (en
Inventor
隆志 池田
孝治 西田
健 井関
実 曽羽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP04125922A priority Critical patent/JP3136760B2/en
Publication of JPH05144663A publication Critical patent/JPH05144663A/en
Application granted granted Critical
Publication of JP3136760B2 publication Critical patent/JP3136760B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、チップ型3端子コンデ
ンサに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type three-terminal capacitor.

【0002】[0002]

【従来の技術】電子回路、特にデジィタル回路のノイズ
対策の一つとして、信号導体ラインとグランド導体との
間にバイパスコンデンサを接続して、高周波成分のノイ
ズをグランド導体に逃がして除去する方法が知られてい
る。バイパスコンデンサとしては、3端子コンデンサが
よく用いられているが、特に近年の回路素子の小型化、
面実装化に伴い、チップ型3端子コンデンサが注目され
ている。
2. Description of the Related Art As one of countermeasures against noise in electronic circuits, particularly digital circuits, there is a method of connecting a bypass capacitor between a signal conductor line and a ground conductor to release high frequency component noise to the ground conductor and remove it. Are known. As a bypass capacitor, a three-terminal capacitor is often used.
With the surface mounting, chip type three-terminal capacitors have been receiving attention.

【0003】以下に従来のチップ型3端子コンデンサに
ついて説明する。図6(a),(b)はそれぞれ従来の
チップ型3端子コンデンサの斜視図、等価回路図を示す
ものである。このチップ型3端子コンデンサは、積層チ
ップコンデンサ1の内部に信号導体ラインを設け、これ
をチップコンデンサの対向する両端縁に設けた信号ライ
ン電極2,3に接続し、この信号ライン電極2,3を形
成していない積層チップコンデンサ1の端面に、内部の
信号導体ラインとの間にコンデンサを形成するようにグ
ランド電極4を設けている。
Hereinafter, a conventional chip type three-terminal capacitor will be described. FIGS. 6A and 6B are a perspective view and an equivalent circuit diagram of a conventional chip type three-terminal capacitor, respectively. In this chip type three-terminal capacitor, a signal conductor line is provided inside a multilayer chip capacitor 1 and connected to signal line electrodes 2 and 3 provided at opposite ends of the chip capacitor. The ground electrode 4 is provided on the end surface of the multilayer chip capacitor 1 where no capacitor is formed so as to form a capacitor between itself and the internal signal conductor line.

【0004】[0004]

【発明が解決しようとする課題】図3のように構成され
たチップ型3端子コンデンサは、チタン酸バリウム等を
母体としているため脆く、基板縁に凹部もしくは凸部を
持つような複雑な形状をとることができない。そのた
め、方形基板縁の3方向に端面電極を形成する際には、
多連チップ抵抗器で用いられるスルーホール印刷、及び
ローラー印刷等の簡便な端面電極形成法はショート不良
を起こすため使えず、他の複雑な製造工程が必要とされ
る。また、母体の脆さに起因する、実装時の割れや電極
剥がれ等の問題点も有している。
The chip type three-terminal capacitor constructed as shown in FIG. 3 is made of barium titanate or the like as a base material, and therefore is brittle and has a complicated shape having a concave portion or a convex portion at the edge of the substrate. I can't take it. Therefore, when forming the end surface electrodes in three directions of the edge of the rectangular substrate,
Simple end-face electrode forming methods, such as through-hole printing and roller printing, used in multiple chip resistors cannot be used due to short-circuit failure, and require other complicated manufacturing steps. In addition, there are also problems such as cracks during mounting and peeling of electrodes due to the brittleness of the base.

【0005】本発明は上記の問題点を解決するもので、
アルミナ等の機械強度に優れる絶縁基板上に厚膜誘電体
によるコンデンサを形成し、この絶縁基板の端縁部に凹
部、もしくは凸部を設けることにより、多連チップ抵抗
器と同様のスルーホール印刷、及びローラー印刷等の簡
便な方法により端面電極を形成でき、かつ、母体強度、
並びに端面電極強度が大きいチップ型3端子コンデンサ
を提供することを目的とする。
The present invention solves the above problems,
By forming a capacitor made of a thick film dielectric on an insulating substrate with excellent mechanical strength such as alumina, and providing a concave or convex portion at the edge of this insulating substrate, through-hole printing similar to multiple chip resistors , And the end face electrode can be formed by a simple method such as roller printing, and the matrix strength,
It is another object of the present invention to provide a chip-type three-terminal capacitor having a large end face electrode strength.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に本発明のチップ型3端子コンデンサは、対向する両端
縁に複数の凹部または凸部を有する方形の絶縁基板と、
この絶縁基板の両端縁の凹部または凸部から絶縁基板の
上面にかけて形成された複数の端子電極と、この複数の
端子電極の少なくとも1つを除き他の端子電極に重なる
ように形成した厚膜誘電体と、前記端子電極のうち厚膜
誘電体が重なって形成されていない端子電極及び厚膜誘
電体に接続するように形成した上部電極と、前記厚膜誘
電体を被覆する保護層とを備え、前記端子電極のうち誘
電体が重なっている電極は信号ライン用の端子電極であ
り、前記厚膜誘電体が重なって形成されていない端子電
極はグランド用の端子電極であり、前記上部電極は前記
厚膜誘電体を介して前記信号ライン用の端子電極を覆っ
ているものである。
In order to achieve the above object, a chip-type three-terminal capacitor according to the present invention comprises: a rectangular insulating substrate having a plurality of concave portions or convex portions at opposite end edges;
A plurality of terminal electrodes formed from a concave portion or a convex portion at both end edges of the insulating substrate to an upper surface of the insulating substrate, and a thick film dielectric formed so as to overlap with other terminal electrodes except for at least one of the plurality of terminal electrodes. with the body and an upper electrode formed so as to be connected to the terminal electrode and thick film dielectric thick film dielectric does not overlap with one of the terminal electrodes, and a protective layer covering the thick film dielectric , Among the terminal electrodes
The electrode on which the conductors overlap is the terminal electrode for the signal line.
And the terminal electrode where the thick film dielectric is not formed to overlap.
The pole is a terminal electrode for ground, and the upper electrode is
A terminal electrode for the signal line is covered with a thick film dielectric.
Is what it is.

【0007】[0007]

【作用】この構成によって、上部に厚膜誘電体を形成し
た端子電極は、両基板端をIN、OUTとする信号ライ
ン電極として働き、他方、上部電極と接続する端子電極
はグランド電極として働き、チップ型3端子コンデンサ
を得ることができる。端子電極は絶縁基板両端縁の凹
部、または凸部に設ける構成であり、多連チップ抵抗器
と同様の簡便な端面電極形成法を取ることができる。ア
ルミナ等の機械強度の高い絶縁基板を母体として用いる
ことができるため、実装時の割れや電極剥がれのほとん
ど無い実装信頼性の高いチップ型3端子コンデンサを提
供できる。
According to this structure, the terminal electrode having the thick film dielectric formed thereon functions as a signal line electrode having both ends of the substrate IN and OUT, while the terminal electrode connected to the upper electrode functions as a ground electrode. A chip type three-terminal capacitor can be obtained. The terminal electrodes are provided in the concave portions or the convex portions at both ends of the insulating substrate, and a simple end face electrode forming method similar to the multiple chip resistor can be employed. Since an insulating substrate having high mechanical strength, such as alumina, can be used as a base, a chip type three-terminal capacitor having high mounting reliability with almost no cracking or electrode peeling during mounting can be provided.

【0008】[0008]

【実施例】(実施例1)以下、本発明の一実施例のチッ
プ型3端子コンデンサについて、図面を参照しながら説
明する。図1(a),(b),(c)は、それぞれ、本
発明の第1の実施例におけるチップ型3端子コンデンサ
の平面図、断面図、及び等価回路図を示すものである。
図1において、11はアルミナ等の絶縁基板で、対向す
る両端縁に複数の凹部を有している。この凹部から絶縁
基板の上面にかけて、信号ライン用端子電極12、グラ
ンド用端子電極13が形成されている。14は厚膜誘電
体、15はこの厚膜誘電体14及びグランド用端子電極
13に重なる上部電極、16は結晶化ガラス、17は非
晶質ガラスである。
(Embodiment 1) Hereinafter, a chip type three-terminal capacitor according to an embodiment of the present invention will be described with reference to the drawings. FIGS. 1A, 1B and 1C are a plan view, a sectional view and an equivalent circuit diagram of a chip type three-terminal capacitor according to a first embodiment of the present invention, respectively.
In FIG. 1, reference numeral 11 denotes an insulating substrate made of alumina or the like, which has a plurality of concave portions at opposite end edges. A signal line terminal electrode 12 and a ground terminal electrode 13 are formed from the concave portion to the upper surface of the insulating substrate. Reference numeral 14 denotes a thick film dielectric, 15 denotes an upper electrode overlapping the thick film dielectric 14 and the ground terminal electrode 13, 16 denotes crystallized glass, and 17 denotes amorphous glass.

【0009】以上のように構成されたチップ型3端子コ
ンデンサは、各端子電極が多連チップ抵抗器と同様に厚
膜導体ペーストのスルーホール印刷、焼成により形成で
きる。また、コンデンサはアルミナ等の母体基板上に厚
膜誘電体で形成しているため、チップの機械強度、並び
に端子電極の強度を大きくでき、実装時の割れ、電極剥
がれをほぼ解消することができる。また、多連チップ抵
抗器と同じはんだランドにより面実装ができるため、併
用する際の回路パターン設計がやり易いという利点もあ
る。
In the chip-type three-terminal capacitor configured as described above, each terminal electrode can be formed by printing and firing a through-hole of a thick film conductor paste in the same manner as a multiple chip resistor. In addition, since the capacitor is formed of a thick film dielectric on a base substrate such as alumina, the mechanical strength of the chip and the strength of the terminal electrode can be increased, and cracking and peeling of the electrode during mounting can be almost eliminated. . In addition, since surface mounting can be performed using the same solder lands as the multiple chip resistors, there is also an advantage that the circuit pattern can be easily designed when used in combination.

【0010】なお、厚膜誘電体の保護層を、結晶化ガラ
ス16と耐めっき性に優れる非晶質ガラス17の2重構
造にしているのは、非晶質ガラス17のみでは焼成時に
厚膜誘電体14中に非晶質ガラスが浸透してコンデンサ
特性に支障をきたし、結晶化ガラス16のみでは基板界
面との封止が不完全で、端子電極めっき時にコンデンサ
特性に支障をきたすためである。
The protective layer of the thick-film dielectric has a double structure of the crystallized glass 16 and the amorphous glass 17 having excellent plating resistance. This is because the amorphous glass penetrates into the dielectric material 14 and impairs the capacitor characteristics, and the crystallized glass 16 alone does not completely seal the interface with the substrate, and impairs the capacitor characteristics during terminal electrode plating. .

【0011】(実施例2)以下、本発明の第2の実施例
について図面を参照しながら説明する。図2は本発明の
第2の実施例を示すチップ型3端子コンデンサの平面図
である。図2において、各部は図1の構成と同様なもの
である。図1と異なるのは、信号ライン用電極端子12
を複数個設けた点である。
(Embodiment 2) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a plan view of a chip type three-terminal capacitor showing a second embodiment of the present invention. 2, each unit is the same as the configuration in FIG. The difference from FIG. 1 is that the signal line electrode terminals 12
Are provided.

【0012】以上のように、信号ライン用端子電極12
を複数個設けることにより、多連チップ抵抗器と同様の
電極形成工法で、チップ型の3端子コンデンサ集合体を
簡単に製造することができる。
As described above, the signal line terminal electrode 12
Are provided, a chip-type three-terminal capacitor assembly can be easily manufactured by the same electrode forming method as that of the multiple chip resistor.

【0013】なお、第1,第2の実施例において端子電
極12,13は基板端縁の凹部へのスルーホール印刷に
よる凹端子電極としたが、基板端縁に凸部を設け、ロー
ラー印刷による凸端子電極としても良い。また、第2の
実施例において、グランド用端子電極13を複数個設け
たものにも適用できる。また、信号ライン用電極端子1
2は両凹部から直線的に設けられているが、静電容量値
を合わせるためにグランド用端子電極13側に膨らんで
も、またはくぼんでも構わない。
In the first and second embodiments, the terminal electrodes 12 and 13 are concave terminal electrodes formed by printing through holes in concave portions at the edges of the substrate. A convex terminal electrode may be used. In the second embodiment, the present invention can be applied to a case in which a plurality of ground terminal electrodes 13 are provided. Also, the signal line electrode terminal 1
Although 2 is provided linearly from both concave portions, it may be expanded or recessed toward the ground terminal electrode 13 in order to match the capacitance value.

【0014】(実施例3)以下、本発明の第3の実施例
について図面を参照しながら説明する。図3は本発明の
第3の実施例を示すチップ型3端子コンデンサアレイの
平面図である。図3において、各部は図2の構造と同様
なものである。図2と異なるのは、グランド用端子電極
13が絶縁基板11の短辺方向の対向両端縁に設けられ
ている点である。
Embodiment 3 Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a plan view of a chip-type three-terminal capacitor array according to a third embodiment of the present invention. 3, each part is the same as the structure of FIG. The difference from FIG. 2 is that the ground terminal electrodes 13 are provided at opposite ends of the insulating substrate 11 in the short side direction.

【0015】以上のように、グランド用端子電極13が
絶縁基板11の短辺方向の対向両端縁に設けることによ
り、長辺方向に短縮することができチップをより小型化
することができる。また、チップの長辺方向だけでなく
短辺方向にもはんだ付けをするのでプリント基板へのは
んだ付け強度が上がるという利点もある。
As described above, by providing the ground terminal electrodes 13 on the opposite end edges in the short side direction of the insulating substrate 11, the length can be shortened in the long side direction, and the chip can be further downsized. Further, since soldering is performed not only in the long side direction but also in the short side direction of the chip, there is an advantage that the soldering strength to the printed circuit board is increased.

【0016】なお、第3の実施例においても端子電極1
2,13は基板端縁の凹部へのスルーホール印刷による
凹端子電極としたが、基板端縁に凸部を設け、ローラー
印刷による凸端子電極としても良く、また、静電容量値
を制御するためやパターンに余裕をもたせるために、凹
部から対向端縁にある対の凹部にかけて膨らんだりくぼ
んだりして非直線的に形成されているが、必要なければ
直線的に設けても構わない。
In the third embodiment, the terminal electrode 1
The reference numerals 2 and 13 are concave terminal electrodes formed by printing through holes in the concave portions of the substrate edge. However, convex portions may be provided on the substrate edge to form convex terminal electrodes by roller printing, and the capacitance value is controlled. In order to allow the pattern to have a margin, it is formed non-linearly by swelling or depressing from the concave portion to the pair of concave portions at the opposite edge, but may be linearly formed if not necessary.

【0017】(実施例4)以下、本発明の第4の実施例
について図面を参照しながら説明する。図4(a),
(b)は、本発明の第4の実施例を示すチップ型3端子
コンデンサの平面図である。図4において、各部は図3
の構成と同様なものである。図3と異なるのは、信号ラ
イン用端子電極12間に抵抗体18を複数個設けた点で
ある。
(Embodiment 4) Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 4 (a),
(B) is a plan view of a chip type three-terminal capacitor showing a fourth embodiment of the present invention. In FIG. 4, each part is shown in FIG.
Is similar to that of the above. The difference from FIG. 3 is that a plurality of resistors 18 are provided between the signal line terminal electrodes 12.

【0018】以上のように、信号ライン用端子電極12
間に抵抗体を設けることにより、抵抗とコンデンサの複
合部品の多連化が簡単に形成できる。
As described above, the signal line terminal electrode 12
By providing a resistor between them, multiple components of a resistor and a capacitor can be easily formed.

【0019】図5は本発明の第4の実施例の適用回路例
であり、一点鎖線で囲んだ部分が本発明のコンデンサで
ある。図5(a)は、バスラインに抵抗を直列に接続し
ノイズ軽減する直列終端である。図5(b)は、バスラ
インからグランドに対してひとつの抵抗とひとつのコン
デンサを直列接続するAC終端である。図5(c)は、
プルアップ、プルダウン用抵抗とコンデンサの組み合わ
せである。以上のように本実施例によれば以上の回路が
すべて対応可能である。
FIG. 5 shows an example of an application circuit of the fourth embodiment of the present invention. The portion surrounded by a dashed line is the capacitor of the present invention. FIG. 5A shows a series termination for reducing noise by connecting a resistor in series to the bus line. FIG. 5B shows an AC termination in which one resistor and one capacitor are connected in series from the bus line to the ground. FIG. 5 (c)
This is a combination of a pull-up / pull-down resistor and a capacitor. As described above, according to the present embodiment, all of the above circuits can be used.

【0020】[0020]

【発明の効果】以上のように本発明によれば、端面電極
を多連チップ抵抗器と同様の簡便な方法で形成でき、か
つアルミナ等の機械強度の高い母体を用いることができ
るため、実装時の割れや電極剥がれの無い実装信頼性の
高いチップ型3端子コンデンサを提供実現できるもので
ある。
As described above, according to the present invention, the end face electrodes can be formed by the same simple method as the multiple chip resistor, and a base having high mechanical strength such as alumina can be used. The present invention can provide and realize a chip-type three-terminal capacitor having high mounting reliability without cracking or electrode peeling.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)は本発明の第1の実施例におけるチップ
型3端子コンデンサの平面図 (b)は同実施例におけるチップ型3端子コンデンサの
断面図 (c)は同実施例におけるチップ型3端子コンデンサの
等価回路図
FIG. 1A is a plan view of a chip type three-terminal capacitor according to a first embodiment of the present invention; FIG. 1B is a cross-sectional view of the chip type three-terminal capacitor according to the embodiment; FIG. Circuit diagram of type 3 terminal capacitor

【図2】本発明の第2の実施例におけるチップ型3端子
コンデンサの平面図
FIG. 2 is a plan view of a chip type three-terminal capacitor according to a second embodiment of the present invention.

【図3】本発明の第3の実施例におけるチップ型3端子
コンデンサの平面図
FIG. 3 is a plan view of a chip-type three-terminal capacitor according to a third embodiment of the present invention.

【図4】(a)は本発明の第4の実施例におけるチップ
型3端子コンデンサの平面図 (b)は同実施例におけるチップ型3端子コンデンサの
等価回路図
FIG. 4A is a plan view of a chip type three-terminal capacitor according to a fourth embodiment of the present invention, and FIG. 4B is an equivalent circuit diagram of the chip type three-terminal capacitor according to the same embodiment.

【図5】(a)〜(c)は本発明の第4の実施例の適用
回路例を示す回路図
FIGS. 5A to 5C are circuit diagrams showing examples of applied circuits according to a fourth embodiment of the present invention;

【図6】(a)は従来のチップ型3端子コンデンサの斜
視図 (b)は従来のチップ型3端子コンデンサの等価回路図
6A is a perspective view of a conventional chip type three-terminal capacitor, and FIG. 6B is an equivalent circuit diagram of a conventional chip type three-terminal capacitor.

【符号の説明】[Explanation of symbols]

11 絶縁基板 12 信号ライン用端子電極 13 グランド用端子電極 14 厚膜誘電体 15 上部電極 16 結晶化ガラス 17 非晶質ガラス 18 厚膜抵抗体 DESCRIPTION OF SYMBOLS 11 Insulation substrate 12 Signal line terminal electrode 13 Ground terminal electrode 14 Thick film dielectric 15 Upper electrode 16 Crystallized glass 17 Amorphous glass 18 Thick film resistor

───────────────────────────────────────────────────── フロントページの続き (72)発明者 曽羽 実 大阪府門真市大字門真1006番地 松下電 器産業株式会社内 (56)参考文献 特開 昭50−80467(JP,A) 特開 昭57−206016(JP,A) 特開 平3−159105(JP,A) 実開 昭60−83234(JP,U) 実開 昭54−124161(JP,U) 実公 昭50−10511(JP,Y1) (58)調査した分野(Int.Cl.7,DB名) H01G 4/00 - 4/40 H01G 13/00 - 13/06 ──────────────────────────────────────────────────続 き Continued on the front page (72) Minoru Soba, Inventor 1006 Kazuma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-50-80467 (JP, A) JP-A Sho57 JP-A-3-159105 (JP, A) JP-A-60-83234 (JP, U) JP-A-54-124161 (JP, U) JP-A-50-10511 (JP, Y1) (58) Fields surveyed (Int.Cl. 7 , DB name) H01G 4/00-4/40 H01G 13/00-13/06

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 対向する両端縁に複数の凹部または凸部
を有する方形の絶縁基板と、この絶縁基板の両端縁の凹
部または凸部から絶縁基板の上面にかけて形成された複
数の端子電極と、この複数の端子電極の少なくとも1つ
を除き他の端子電極に重なるように形成した厚膜誘電体
と、前記端子電極のうち厚膜誘電体が重なって形成され
ていない端子電極及び厚膜誘電体に接続するように形成
した上部電極と、前記厚膜誘電体を被覆する保護層とを
備え、前記端子電極のうち誘電体が重なっている電極は
信号ライン用の端子電極であり、前記厚膜誘電体が重な
って形成されていない端子電極はグランド用の端子電極
であり、前記上部電極は前記厚膜誘電体を介して前記信
号ライン用の端子電極を覆っているチップ型3端子コン
デンサ。
1. A rectangular insulating substrate having a plurality of concave portions or convex portions at opposite ends, a plurality of terminal electrodes formed from the concave portions or convex portions at both ends of the insulating substrate to the upper surface of the insulating substrate, A thick-film dielectric formed so as to overlap other terminal electrodes except at least one of the plurality of terminal electrodes; a terminal electrode and a thick-film dielectric which are not formed by overlapping the thick-film dielectric among the terminal electrodes; An upper electrode formed so as to be connected to a protective layer covering the thick film dielectric.
The terminal electrode of which the dielectric is overlapped is
A terminal electrode for a signal line, wherein the thick film dielectric is overlapped.
Terminal electrodes that are not formed are ground terminal electrodes
And the upper electrode is connected to the signal through the thick film dielectric.
Chip type three-terminal capacitor covering the terminal electrode for the No. line .
【請求項2】 長辺方向の対向両端縁に複数対の凹部ま
たは凸部を有し短辺方向の対向両端縁に一対の凹部また
は凸部を有する方形の絶縁基板と、この長辺方向の凹部
または凸部から対向端縁にある対の凹部または凸部にか
けて形成された複数の信号ライン用端子電極と、この複
数の信号ライン用端子電極の両端部を除いて重なるよう
に形成された厚膜誘電体と、短辺方向の凹部または凸部
に形成された一対のグランド用端子電極と、このグラン
ド用端子電極から前記厚膜誘電体の上を経て対向端縁に
ある対のグランド用端子電極にかけて形成された上部電
極と、前記厚膜誘電体を被覆する保護膜とを備え、前記
上面電極は前記厚膜誘電体を介して前記複数の信号ライ
ン用電極を覆っているチップ型3端子コンデンサ。
2. A rectangular insulating substrate having a plurality of pairs of recesses or protrusions at opposite end edges in the long side direction and a pair of recesses or protrusions at opposite end edges in the short side direction; A plurality of signal line terminal electrodes formed from the concave or convex portion to a pair of concave or convex portions on the opposite edge, and a thickness formed so as to overlap except for both end portions of the plurality of signal line terminal electrodes. A film dielectric, a pair of ground terminal electrodes formed in a concave portion or a convex portion in the short side direction, and a pair of ground terminals on the opposite edge from the ground terminal electrode on the thick film dielectric. An upper electrode formed over the electrode, and a protective film that covers the thick film dielectric ,
The upper electrode is connected to the plurality of signal lines through the thick film dielectric.
Chip-type three-terminal capacitor covering the electrodes for
【請求項3】 長辺方向の対向両端縁に複数対の凹部ま
たは凸部を有し短辺方向の対向両端縁に一対の凹部また
は凸部を有する方形の絶縁基板と、この長辺方向の凹部
または凸部から対向端縁にある対の凹部または凸部にか
けて形成された複数の信号ライン用端子と、この信号ラ
イン用端子電極間の信号経路上に直列に接続された複数
の抵抗体と、この複数の信号ライン用端子電極の両端縁
と抵抗体部を除いて重なるように形成された厚膜誘電体
と、短辺方向の凹部または凸部に形成された一対のグラ
ンド用端子電極と、このグランド用端子電極から前記厚
膜誘電体を経て対向端縁にある対のグランド用端子電極
にかけて形成された上部電極と、前記厚膜誘電体を被覆
する保護層とを備え、前記上面電極は前記厚膜誘電 体を
介して前記複数の信号ライン用電極を覆っているチップ
型3端子コンデンサ。
3. A rectangular insulating substrate having a plurality of pairs of recesses or protrusions at opposite end edges in the long side direction and a pair of recesses or protrusions at opposite end edges in the short side direction; A plurality of signal line terminals formed from the concave or convex portions to a pair of concave or convex portions on the opposite edge, and a plurality of resistors connected in series on a signal path between the signal line terminal electrodes; A thick-film dielectric formed so as to overlap with both end edges of the plurality of signal line terminal electrodes except for the resistor portion, and a pair of ground terminal electrodes formed in a concave portion or a convex portion in a short side direction. , comprising an upper electrode formed over the grounding terminal electrode pairs on opposite edges from the grounding terminal electrode through the thick film dielectric, and a protective layer covering the thick film dielectric, said upper electrode the thick film dielectric of
A chip-type three-terminal capacitor that covers the plurality of signal line electrodes via a plurality of signal line electrodes .
【請求項4】 保護膜は結晶化ガラスと非結晶化ガラス
の二重構造である請求項1記載のチップ型3端子コンデ
ンサ。
4. The chip-type three-terminal capacitor according to claim 1, wherein the protective film has a double structure of crystallized glass and non-crystallized glass.
JP04125922A 1991-08-08 1992-05-19 Chip type three-terminal capacitor Expired - Fee Related JP3136760B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04125922A JP3136760B2 (en) 1991-08-08 1992-05-19 Chip type three-terminal capacitor

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP19937091 1991-08-08
JP3-199370 1991-08-08
JP04125922A JP3136760B2 (en) 1991-08-08 1992-05-19 Chip type three-terminal capacitor

Publications (2)

Publication Number Publication Date
JPH05144663A JPH05144663A (en) 1993-06-11
JP3136760B2 true JP3136760B2 (en) 2001-02-19

Family

ID=26462220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04125922A Expired - Fee Related JP3136760B2 (en) 1991-08-08 1992-05-19 Chip type three-terminal capacitor

Country Status (1)

Country Link
JP (1) JP3136760B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100711012B1 (en) * 1998-10-07 2007-04-25 소니 가부시끼 가이샤 Coding apparatus and method, decoding apparatus and method, data processing system, storage medium, and signal
WO2011121994A1 (en) 2010-03-30 2011-10-06 株式会社村田製作所 Power supply device

Also Published As

Publication number Publication date
JPH05144663A (en) 1993-06-11

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