JPS6386414A - Laminated ceramic capacitor - Google Patents

Laminated ceramic capacitor

Info

Publication number
JPS6386414A
JPS6386414A JP61229788A JP22978886A JPS6386414A JP S6386414 A JPS6386414 A JP S6386414A JP 61229788 A JP61229788 A JP 61229788A JP 22978886 A JP22978886 A JP 22978886A JP S6386414 A JPS6386414 A JP S6386414A
Authority
JP
Japan
Prior art keywords
ceramic
capacitor
conductive
external electrode
intermediate layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61229788A
Other languages
Japanese (ja)
Other versions
JPH0464450B2 (en
Inventor
外丸 隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP61229788A priority Critical patent/JPS6386414A/en
Publication of JPS6386414A publication Critical patent/JPS6386414A/en
Publication of JPH0464450B2 publication Critical patent/JPH0464450B2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、セラミックと外部電極とを同時に焼成した積
層形セラミックコンデンサに関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multilayer ceramic capacitor in which a ceramic and an external electrode are simultaneously fired.

(従来の技術) セラミックと外部電極とを同時に焼成して得られる従来
の積層形セラミックコンデンサは次のような製造手順に
従って作成される。
(Prior Art) A conventional multilayer ceramic capacitor obtained by simultaneously firing a ceramic and an external electrode is manufactured according to the following manufacturing procedure.

まず、複数枚の長尺な未焼成誘電体セラミックシートの
主面に旧、Cu等の導電粒子を含む導電ペーストを印劉
して複数個の内部電極用導電層を形成し、これ等のシー
トを1つ置きに長手方向にずらして重ねた後圧着し、ず
らしたシートの導電層が切断面に露出する位置と、ずら
さないシートの導Ti層が切断面に露出する位置とで切
断してコンデンサ素体としてのチップ片を作成する。次
いで、該チップ片の導電層が露出している端面とこれに
連なる周端縁部に、導電ペーストを塗布して外部電極用
導電層を形成した後、900〜1200℃の温度で還元
雰囲気中でセラミック素体の電極を同時に焼成する。こ
のようにして得られた積層形セラミックコンデンサの外
部電極は、該端面で内部電極と電気的に接続し、該端面
とこれに連なるコンデンサ素体の周端縁部に直に密着し
ている。
First, a conductive paste containing conductive particles such as Cu is printed on the main surface of a plurality of long unfired dielectric ceramic sheets to form a plurality of conductive layers for internal electrodes. The sheets were stacked one on top of the other, shifted in the longitudinal direction every other time, and then crimped, and then cut at a position where the conductive layer of the shifted sheet was exposed to the cut surface, and at a location where the conductive Ti layer of the unshifted sheet was exposed to the cut surface. Create a chip piece as a capacitor body. Next, a conductive paste is applied to the end face of the chip piece where the conductive layer is exposed and the peripheral edge connected thereto to form a conductive layer for an external electrode, and then heated in a reducing atmosphere at a temperature of 900 to 1200°C. The electrodes of the ceramic body are fired at the same time. The outer electrode of the multilayer ceramic capacitor thus obtained is electrically connected to the inner electrode at the end face, and is directly in close contact with the end face and the peripheral edge of the capacitor element connected thereto.

(発明が解決しようとする問題点) 上述のような製造手順により作成された第3図及び第4
図に図示の積層形セラミックコンデンサは、プリント基
板等に半田付は後の温度衝撃試験時等において、コンデ
ンサ素体の周端縁部に形成された外部電極aの周縁のセ
ラミックbにクラックCが入り絶縁抵抗値が103MΩ
以下になるものが生ずるという問題があった。尚、第4
図において、dは内部電極である。
(Problems to be solved by the invention) Figures 3 and 4 produced by the manufacturing procedure described above
When the multilayer ceramic capacitor shown in the figure is soldered to a printed circuit board, etc., cracks C appear in the ceramic b around the external electrode a formed at the peripheral edge of the capacitor body during a later temperature shock test. Insulation resistance value is 103MΩ
There was a problem that the following occurred. Furthermore, the fourth
In the figure, d is an internal electrode.

本発明は、従来のこのような問題を解消することのでき
る積層形セラミックコンデンサを提出することをその目
的とするものである。
An object of the present invention is to provide a multilayer ceramic capacitor that can solve these conventional problems.

(問題点を解決するための手段) 本発明は、上述の目的を達成するために、内部電極用導
電層が形成された未焼成セラミツクシートを複数枚積層
し圧着して成るコンデンサ素体の両端面及びそれに連な
る周端縁部に外部電極用導電層を形成した後焼成してな
る積層形セラミックコンデンサにおいて、該セラミック
素体の周端縁部と外部電極用導電層との間に上記セラミ
ックと同一組成のセラミックと導電性粒子とから成る中
間層が介在することを特徴とする。
(Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention provides a capacitor body formed by laminating and press-bonding a plurality of unfired ceramic sheets on which conductive layers for internal electrodes are formed. In a multilayer ceramic capacitor formed by forming a conductive layer for an external electrode on a surface and a peripheral edge portion connected thereto and then firing it, the above ceramic and the conductive layer for an external electrode are provided between the peripheral edge portion of the ceramic body and the conductive layer for an external electrode. It is characterized by the presence of an intermediate layer consisting of ceramic and conductive particles of the same composition.

(作 用) 未焼成のセ、ラミックの焼成に伴う収縮と、外部電極用
導電層の焼成に伴う収縮とが相違するため、焼成後にコ
ンデンサ素体の周端縁部に形成された外部電極の周縁に
おけるセラミックに歪が残る。しかしコンデンサ素体の
周端縁部と外部電極との間に、該セラミックと同一組成
のセラミックと導電製粒子とから成る中間層を介在させ
ると、該中間層の収縮mは、セラミックの収縮旦と外部
電極の収縮mとの中間であるので、セラミックに生ずる
歪は小さくなる。かくて本案コンデンサをプリント基板
等に半田付けした後の温度衝撃試験等において、外部電
極の周縁におけるセラミックにクラックが生じない。
(Function) Because the shrinkage caused by firing the unfired ceramic and ramic and the shrinkage caused by the firing of the conductive layer for the external electrode are different, the shrinkage caused by the firing of the external electrode conductive layer formed on the peripheral edge of the capacitor body after firing is different. Distortion remains in the ceramic at the periphery. However, if an intermediate layer consisting of a ceramic having the same composition as the ceramic and conductive particles is interposed between the peripheral edge of the capacitor body and the external electrode, the contraction m of the intermediate layer will be reduced by the shrinkage rate of the ceramic. Since it is between the shrinkage m of the external electrode and the shrinkage m of the external electrode, the strain occurring in the ceramic becomes small. Thus, no cracks occur in the ceramic at the periphery of the external electrode during a temperature shock test or the like after the capacitor of the present invention is soldered to a printed circuit board or the like.

(実施例) 本発明の実施例を添付図面に付説明する。(Example) Embodiments of the present invention will be described with reference to the accompanying drawings.

実施例1 BaTtO3を主成分といる厚さ381LI11の未焼
成誘電体セラミックシートを複数枚を用意した。
Example 1 A plurality of unfired dielectric ceramic sheets having a thickness of 381 LI11 and containing BaTtO3 as a main component were prepared.

また、純度99,9%の旧粉末100gと、エチルセル
ローズ15gと、ブチルカルピトール941Jとを混練
して作成した内部電極用導電ペーストと、純度99.9
%のNi粉末50gと該セラミックシートと同一組成の
未焼成セラミツク粉末50gとエチルセルローズ20g
とブチルカルピトール941Jとを混練して作成した中
間層用ペーストと、純度99.9%のNi粉末i oo
gとエチルセルローズ20(+とブチルカルピトール9
4CIとを混練して作成した外部電極用ペーストとを用
意した。
In addition, a conductive paste for internal electrodes was prepared by kneading 100 g of old powder with a purity of 99.9%, 15 g of ethyl cellulose, and butyl calpitol 941J, and a conductive paste with a purity of 99.9%.
% Ni powder, 50 g of unfired ceramic powder with the same composition as the ceramic sheet, and 20 g of ethyl cellulose.
An intermediate layer paste prepared by kneading and butyl calpitol 941J, and 99.9% pure Ni powder ioo
g and ethyl cellulose 20 (+ and butyl calpitol 9
An external electrode paste prepared by kneading 4CI and 4CI was prepared.

上述の未焼成セラミツクシートと内部電極用導電ペース
トとを用いて、従来の方法に従って、未焼成のコンデン
サ素体を作成し、該コンデンサ素体に内在する内部電極
の1端が露出する端面に連なる周端縁部に中間層用ペー
ストを帯状に塗布し、150℃で乾燥した後、該中間層
上とコンデンサ素体の端面とに連続して外部電極用ペー
ストを塗布し、乾燥した後、N2を2%含むN2ガス雰
囲気中で1180℃で2時間焼成して積層形セラミック
コンデンサを作成した。これ等のコンデンサの外部電極
上に市販の無電解ニッケルメッキ浴によってニッケルメ
ッキ膜を形成した。
Using the above-mentioned unfired ceramic sheet and conductive paste for internal electrodes, an unfired capacitor body is created according to a conventional method, and one end of the internal electrode contained in the capacitor body is connected to the exposed end face. After applying the intermediate layer paste in a band shape to the peripheral edge and drying it at 150°C, apply the external electrode paste continuously on the intermediate layer and the end face of the capacitor body, and after drying, apply N2 A multilayer ceramic capacitor was produced by firing at 1180° C. for 2 hours in an N2 gas atmosphere containing 2%. A nickel plating film was formed on the external electrodes of these capacitors using a commercially available electroless nickel plating bath.

第1図及び第2図は、本発明の1実施例の積層形セラミ
ックコンデンサを示す。
1 and 2 show a multilayer ceramic capacitor according to one embodiment of the present invention.

同図において、(1)は内部にセラミック層を介して積
層され交互に対向する端面に露出する内部電極(乃を有
するコンデンサ素体、〈3)は該端面に連なるコンデン
サ素体(1)の周端縁部に形成された帯状の中間層、(
4)は該中間層(3)及び端面上に連続して形成された
外部電極である。
In the same figure, (1) is a capacitor body having internal electrodes laminated through ceramic layers and exposed on alternately opposing end faces, and (3) is a capacitor body (1) that is connected to the end faces. A band-shaped intermediate layer formed on the peripheral edge, (
4) is an external electrode continuously formed on the intermediate layer (3) and the end face.

この積層形セラミックコンデンサは、ガラスエポキシ配
線基板上に半田付けし、市販のLCRメータ(YHP社
製)、絶縁抵抗計(東亜電波製)とを用いて、静電容量
(C)と誘電正接(tanδ)と絶縁抵抗(IR)とを
測定した。次いで一55℃に30分間保持し、2秒以内
に+125℃に移動して30分間保持す8むとを1.、
イクノ音る熱衝撃試験を100回行なった後、再び静電
容ffi (C)と誘電正接(tanδ)と絶縁抵抗(
IR)とを測定し、静電容伍の最大変化率とtanδの
最大値と絶縁抵抗103MΩ以下の個数と目視で発見さ
れるクラックを有するものの個数を下表に示した。
This multilayer ceramic capacitor was soldered onto a glass epoxy wiring board, and the capacitance (C) and dielectric loss tangent ( tan δ) and insulation resistance (IR) were measured. Then, hold at -55°C for 30 minutes, move to +125°C within 2 seconds and hold for 30 minutes.1. ,
After conducting the thermal shock test 100 times, the capacitance ffi (C), dielectric loss tangent (tan δ), and insulation resistance (
The table below shows the maximum rate of change in capacitance, the maximum value of tan δ, the number of insulation resistances of 103 MΩ or less, and the number of cracks found visually.

実施例2 中間層用ペーストとして、実施例1における旧粉末50
gに代えて35CIセラミツクと同一組成の未焼成セラ
ミツク粉末50gに代えて650を用いた実施例1と同
じ方法及び條件で作成した。
Example 2 Old powder 50 in Example 1 was used as a paste for the intermediate layer.
It was produced in the same manner and under the same conditions as in Example 1 except that 50 g of unfired ceramic powder having the same composition as 35 CI ceramic was used instead of 650 g.

この測定結果を下表に示す。The measurement results are shown in the table below.

実施例3 中間層用ペーストとして、実施例1における旧粉末50
gに代えて20(lセラミックと同一組成の未焼成セラ
ミツク粉末50gに代えて80gとしたこと以外は実施
例1と同じ方法及び條件で作成した。この測定結果を下
表に示す。
Example 3 Old powder 50 in Example 1 was used as a paste for the intermediate layer.
It was prepared in the same manner and under the same conditions as in Example 1, except that 80 g was used instead of 50 g of unfired ceramic powder having the same composition as the 20 (l) ceramic powder. The measurement results are shown in the table below.

実施例4 内部電極用ペースト、中間層用ペースト及び外部電極用
ペーストの導電粒子として、実施例1におけるN1粉末
に代えてCu粉末としたこと以外は、実施例1と同じ方
法及び同じ条件で作成した。この測定結果を下表に示す
Example 4 Created by the same method and under the same conditions as Example 1, except that Cu powder was used instead of N1 powder in Example 1 as the conductive particles of the internal electrode paste, intermediate layer paste, and external electrode paste. did. The measurement results are shown in the table below.

比較例 中間層を除いた以外は実施例1と同じ方法及び同じ條件
で作成した。
Comparative Example A comparative example was prepared in the same manner and under the same conditions as in Example 1, except that the intermediate layer was omitted.

表 n −1000@ 尚、前記各ペーストの導電粒子として、AQ。table n -1000@ In addition, AQ is used as the conductive particles of each of the pastes.

^Q−Pd等を同様に用いることができる。^Q-Pd etc. can be used similarly.

(発明の効果) 以上説明したように、本発明によれば、プリント基板に
半田付けした時あるいは温度衝撃試験等を行なった時r
もコンデンサ素体の周端縁部の外部電極周縁におけるセ
ラミックにクラックが発生することが少なく、また絶縁
抵抗の劣化も少ないという効果がある。
(Effects of the Invention) As explained above, according to the present invention, when soldering to a printed circuit board or performing a temperature shock test, etc.
This also has the effect that cracks are less likely to occur in the ceramic around the outer electrode at the peripheral edge of the capacitor body, and there is less deterioration of insulation resistance.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の1実施例の拡大斜視図、第2図はその
断面図、第3図は従来例の拡大斜視図、第4図はその断
面図である。 (1)・・・コンデンサ素体  (り・・・内部電極(
3)・・・中間層      (4)・・・外部電極外
ンる
FIG. 1 is an enlarged perspective view of one embodiment of the present invention, FIG. 2 is a sectional view thereof, FIG. 3 is an enlarged perspective view of a conventional example, and FIG. 4 is a sectional view thereof. (1)... Capacitor body (ri... internal electrodes)
3)...Intermediate layer (4)...Outer electrode

Claims (1)

【特許請求の範囲】[Claims]  内部電極用導電層が形成された未焼成セラミックシー
トを複数枚積層し圧着して成るコンデンサ素体の両端面
及びそれに連なる周端縁部に外部電極用導電層を形成し
た後焼成してなる積層形セラミックコンデンサにおいて
、該セラミック素体の周端縁部と外部電極用導電層との
間に上記セラミックと同一組成のセラミックと導電性粒
子とから成る中間層が介在することを特徴とする積層形
セラミックコンデンサ。
A laminated layer formed by laminating and press-bonding a plurality of unfired ceramic sheets on which conductive layers for internal electrodes are formed, forming a conductive layer for external electrodes on both end faces of the capacitor body and the peripheral edges connected thereto, and then firing the sheets. A laminated type ceramic capacitor, characterized in that an intermediate layer consisting of a ceramic having the same composition as the ceramic and conductive particles is interposed between the peripheral edge of the ceramic body and the conductive layer for external electrode. ceramic capacitor.
JP61229788A 1986-09-30 1986-09-30 Laminated ceramic capacitor Granted JPS6386414A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61229788A JPS6386414A (en) 1986-09-30 1986-09-30 Laminated ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61229788A JPS6386414A (en) 1986-09-30 1986-09-30 Laminated ceramic capacitor

Publications (2)

Publication Number Publication Date
JPS6386414A true JPS6386414A (en) 1988-04-16
JPH0464450B2 JPH0464450B2 (en) 1992-10-15

Family

ID=16897682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61229788A Granted JPS6386414A (en) 1986-09-30 1986-09-30 Laminated ceramic capacitor

Country Status (1)

Country Link
JP (1) JPS6386414A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952863A (en) * 1996-12-09 1999-09-14 Texas Instruments Incorporated Circuit and method for generating non-overlapping clock signals for an integrated circuit
WO2012043740A1 (en) * 2010-09-29 2012-04-05 京セラ株式会社 Capacitor
WO2024075402A1 (en) * 2022-10-03 2024-04-11 株式会社村田製作所 Multilayer ceramic electronic component

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5952863A (en) * 1996-12-09 1999-09-14 Texas Instruments Incorporated Circuit and method for generating non-overlapping clock signals for an integrated circuit
WO2012043740A1 (en) * 2010-09-29 2012-04-05 京セラ株式会社 Capacitor
CN102549687A (en) * 2010-09-29 2012-07-04 京瓷株式会社 Capacitor
JP5420060B2 (en) * 2010-09-29 2014-02-19 京セラ株式会社 Capacitor
US8743528B2 (en) 2010-09-29 2014-06-03 Kyocera Corporation Capacitor
WO2024075402A1 (en) * 2022-10-03 2024-04-11 株式会社村田製作所 Multilayer ceramic electronic component

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