JP2994312B2 - ECL logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an ECL (Emit
The present invention relates to a ter-coupled logic (Logic) circuit, and more particularly, to a high-speed ECL logic circuit.

[0002]

2. Description of the Related Art An EC composed of a conventional ECL logic circuit
As an example of the L frequency dividing circuit, FIG. 4 shows a resistive load type frequency dividing circuit having a master / slave configuration.

Referring to FIG. 4, a frequency dividing circuit 200 includes a master / slave flip-flop (hereinafter referred to as FF) 1
0 and the FF 20 to divide the input signal by １ ／. Since the FF 10 and the FF 20 are circuit blocks having the same circuit configuration, only the circuit configuration of the FF 10 will be described. Transistors Q5 and Q6 constitute an input differential amplifier. Input signal 1 and an inverted input signal which is an inverted signal of input signal 1 are input to their bases, and their common emitters are connected to a constant current source.

The transistors Q1 and Q4 form a transistor pair 3 of the master circuit, and their emitters are connected to the collector of the transistor Q5. Similarly, transistors Q2 and Q3 form a transistor pair of the slave circuit, and their emitters are connected to the collector of transistor Q6. The output loads of the transistors Q1 and Q2 are formed using a resistor R1, and the transistors Q3 and Q2
The output load of No. 4 is configured using the resistor R2.

The circuit operation of the frequency dividing circuit 200 will be briefly described. The input signal 1 and the inverted input signal 2 are inputted to the FF 10 and the FF 20 in opposite phase relations.
The circuit operation differs for each half cycle of the input signal. FF10 is
When the input signal goes high, the transistor Q
The transistor pair of the slave circuit composed of Q2 and Q3 is inverted. Similarly, the FF 20 is inverted when the input signal goes to the ECL low level. The reason that the FFs 10 and 20 can be inverted is that the FF of the other side is inverted half a cycle before.

A frequency dividing circuit 200 shown in FIG.
The high-speed performance of the L logic circuit depends on the switching response of the transistor itself constituting the ECL logic circuit, the output resistance and the total load capacitance connected to this output resistance (that is, the load capacitance connected to the output resistance and the parasitic capacitance associated with the wiring and the resistance) And the time constant.

Therefore, in order to increase the speed of the ECL logic circuit, it is necessary to improve the speed of the transistor by miniaturizing the process, optimize the current and gain for lowering the output load resistance, and reduce the parasitic capacitance. Layout design considerations were needed.

Next, factors that determine the switching speed of the ECL logic circuit will be described. The switching speed of the ECL logic circuit can be considered by dividing into the following three factors.

1) Switching response time of a transistor constituting the ECL logic circuit This can be represented by a forward transition time τf of the transistor.
Is getting significantly smaller.

2) Base response time (mirror response time) This can be expressed as G0 · rbb · Cjc. Here, G0 is a circuit gain, rbb is a base resistance,
Cjc is a base-collector junction capacitance. The base resistance rbb and the base-collector junction capacitance Cjc can be reduced with miniaturization of the process. However, the circuit gain G0 is a constant determined by the circuit configuration, and the circuit gain G0 is required to reduce the base response time. Is indispensable.

3) Collector response time (resistive load response time) This can be expressed as RL · Cjs + RL · CL. Here, RL is a load resistance, Cjs is a junction capacitance between the collector and the semiconductor substrate, and CL is a load capacitance. The junction capacitance Cjs between the collector and the semiconductor substrate and the load capacitance CL decrease with the miniaturization of the process. However, the load resistance RL is a constant determined from the circuit configuration like the circuit gain G0 described in 2). In order to reduce the load resistance, it is necessary to configure a circuit to reduce the load resistance RL.

Although the switching speed of the frequency dividing circuit 200 varies depending on the process as described above, τf = 10 pS, rbb = 1 kΩ, C
jc = 10fF, Cjs = 50fF, CL = 100f
F, the current value Ic of the constant current source is 0.5 mA, RL = 406
Calculated using each value of Ω: 1) Switching response time τf of transistor: 10p
S2) Base response time G0 · rbb · Cjc: 1.95 × 1 kΩ × 10fF = 20 pS Here, G0 = ΔVout (DC) / (4kT
/ Q) = 203 mV / (4 × 26 mV) = 1.95. Here, ΔVout (DC) is the DC output amplitude of FF10.

3) Collector response time RL · Cjs + RL
CL: 406Ω · (50 fF + 100 fF) = 61 pS

[0014]

In the above-mentioned conventional ECL logic circuit, although the switching response time and the base response time of the transistor can be reduced by miniaturization of the process, it is difficult to reduce the collector response time. That is, the load resistance R
It is necessary to increase the value of L to a certain degree or more. On the other hand, if the load resistance RL is increased, there is a problem that the collector response speed is reduced.

Therefore, an object of the present invention is to reduce the collector response time in addition to the base response time to speed up the ECL logic circuit and to reduce the ECL logic without lowering the circuit gain.
An object of the present invention is to provide an ECL logic circuit in which the output amplitude level of the logic circuit is increased to a level that does not cause a practical problem.

It is another object of the present invention to provide an ECL logic circuit with less distortion of an output signal.

[0017]

Therefore, in an ECL logic circuit according to the present invention, a load of an output stage for outputting to an external circuit is constituted by a resistor, and a load from an input stage to the output stage is connected to a collector via a resistor. And a transistor connected to a power supply.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of an ECL logic circuit according to the present invention. Components common to those of the conventional example shown in FIG. 4 are denoted by common reference characters / numbers.

Referring to FIG. 1, the FF 30 and the FF 40 have the same circuit configuration. The input differential amplifiers (transistors Q5 and Q6) constituting the FF 30, the transistor pair 3 of the master circuit (transistors Q1 and Q4), and the FF 30 The transistor pair (transistors Q2 and Q3) is FF
Same as 10.

Unlike the FF 10 shown in FIG. 4, the collectors of the transistors Q1 and Q2 are connected to the emitter of a transistor Q14 having a base and a collector connected. The collector of the transistor Q14 is connected to the base via a power supply and the collector via a resistor R1. The emitter of the transistor Q13 connected to the power supply is connected.

Similarly, the collectors of the transistors Q3 and Q4 are connected to the base of the transistor Q16.
The emitter of a transistor Q15 having a base connected to a power supply and a collector connected to a power supply via a resistor R2 is connected to the collector of the transistor Q16.

Now, when the input signal 1 goes high and the inverted input signal 2 goes low, the transistors Q5, Q1
2 is on, and transistors Q6 and Q11 are off. Accordingly, the transistors Q2, Q3, Q7 and Q10 are turned off, but the transistors Q1 and Q9 and the transistor Q9 are turned off.
4, Q8 can take two states, on and off. That is, if both the transistors Q1 and Q9 are on, the transistors Q4 and Q8 are both off and the transistors Q1 and Q9 are off.
If both 9 are off, both transistors Q4 and Q8 are on.

Similarly, when the input signal 1 goes low and the inverted input signal 2 goes high, the transistors Q6, Q
11 is on, and transistors Q5 and Q12 are off.
Accordingly, the transistors Q1, Q4, Q8, and Q9 are turned off, but the transistors Q2 and Q7 and the transistor Q
3, Q10 can be in two states: on and off. That is, if both transistors Q2 and Q7 are on, both transistors Q3 and Q10 are off and transistor Q3
If both Q2 and Q7 are off, transistors Q3 and Q10
Both turn on.

Next, a DC level circuit gain and an AC gain are calculated.

First, a high level Vout (H) at the contact A of the emitter of the transistor Q14 in FIG. 1 is determined. When the transistors Q1 and Q2 are both off and the transistors Q3 and Q10 are both on, the current flowing through the transistor Q14 is the sum of the base currents of the transistors Q3 and Q10. Then, the high level Vout
(H) is given by the following equation.

Vout (H) = Vcc−2 · VF (2Ic / hFE) (1) where Vcc is a power supply voltage, VF is a base-emitter voltage of the transistor, and hFE is a DC current gain of the transistor. It is.

Similarly, the low level Vout (L) at the contact A of the emitter of the transistor Q14 is calculated from the case where the transistor Q1 or the transistor Q2 is turned on, and is calculated by the following equation. Vout (L) = Vcc−2 · VF (Ic) (2) From the equations (1) and (2), the DC amplitude ΔVout at the contact A of the emitter of the transistor Q14 is calculated from the following equation. ΔVout = Vout (H) −Vout (L) = 2 · (KT / q) · ln (h FE / 2) (3) where K is the Boltzmann constant, T is the absolute temperature, and q is the electron temperature. The amount of charge. Therefore, the DC load resistance RL (DC) from the contact A to the power supply is given by the following equation. RL (DC) = ΔVout / Ic = 2 · (KT / q) / Ic · ln (hFE / 2) (4) On the other hand, an AC load resistance R from the contact A to the power supply
L (AC) is calculated from the following equation, reflecting the diode characteristics of the transistors Q13 and Q14.

Therefore, according to the equations (4) and (5), the AC load resistance RL (AC) is converted to the DC load resistance RL (D
RL (AC) / RL (DC) = 2 / ln (hFE / 2) (6) with respect to C).

Here, Ic = 0.5 mA, hFE = 10
Specifically, assuming that 0 and T = 300 [゜ K], RL (DC) = 2.26 mV · ln (100/2) /
0.5mA = 406Ω RL (AC) = 4.26mV / 0.5mV = 208Ω,
RL (AC) / RL (DC) = 0.51, and the AC load resistance RL (AC) becomes the DC load resistance RL (D
It turns out that it becomes much smaller than C).

This is conceptually described with reference to FIG. 2. The DC load resistance RL (DC) can be obtained from the slope α of a straight line connecting the point P1 on the diode characteristic curve and the origin. Load resistance RL (AC) is obtained from the slope β of the tangent at the point P2 on the diode characteristic curve. If the current at the point P2 is about 1/2 or more of the current flowing at the point P1, the slope β is Becomes smaller than the inclination α.

As described above, in the ECL logic circuit according to the present invention, the effective value of the AC load resistance which determines the collector response speed can be reduced, so that the collector response time is shortened and the high speed of the entire ECL logic circuit is achieved. Performance is greatly improved.

Further, since the DC load resistance RL (DC) that determines the circuit gain is large, the output amplitude level of the ECL logic circuit can be increased to a level that does not pose a practical problem.

When the switching speed of the ECL logic circuit according to the present invention is calculated using the same values as the parameters calculated in the conventional example, τf = 10 pS, rbb = 1 kΩ,
Cjc = 10fF, Cjs = 50fF, CL = 100f
F, the current value Ic of the constant current source is 0.5 mA, RL (DC)
1) The switching response time τf of the transistor 2) The base response time G0 · rbb · Cjc 3) The collector response time RL · Cjs + RL · CL is calculated as follows, respectively.

1) Switching response time τf of the transistor: 10 pS 2) Base response time G0 · rbb · Cjc: 1.95 × 1 kΩ × 10fF = 20 pS

Here, G0 = ΔVout (DC) / (4
kT / q) = 203 mV / (4 × 26 mV) = 1.95
Calculated as However, ΔVout (DC) = 2.26
It was calculated as mV · ln (100/2).

3) Collector response time RL · Cjs + RL
CL: 208Ω · (50 fF + 100 fF) = 31 pS

Therefore, (10 + 20 + 31) pS / (10 + 20 + 61) p compared to the total response speed of the conventional example.
S = 0.67, and the total response speed is greatly improved.

Further, the effect of the load resistance response becomes relatively large with the miniaturization and speeding up of process transistors in the future, so that the improvement effect becomes more remarkable.

Next, the output waveform at the internal contact and the output waveform to the external circuit of the ECL logic circuit of the present invention will be described with reference to FIG.

FIG. 3A shows the input signal 1 input to the base of the transistor Q5, and FIG. 3B shows the emitter voltage of the transistor Q18. First, in the period T0, the base current of the transistors Q1 and Q9 does not flow, and an overshoot occurs due to switching.

Next, in the period T1, the transistor Q
1, Q9 base currents flow and transistors Q17, Q1
8 is activated and clamped to a high level corresponding to the diode forward voltage for the base current.

Next, in the period T2, the transistor Q
7 is turned on, clamped to a low level corresponding to the diode forward voltage corresponding to the collector current, and then during period T3
Then, the transistor Q8 is turned on in place of the transistor Q7, and is clamped at a low level corresponding to the diode forward voltage corresponding to the collector current. And the period T0 to T4
The operation up to is repeated.

As described above, in the emitter of the transistor Q18, which is an internal contact, the circuit gain becomes nonlinear at the time of switching response, and the output is distorted.
There is a danger that the logical operation with another ECL logic circuit connected to the output terminal Out and the inverted output terminal Out bar shown in FIG.

However, the output of the ECL logic circuit of the present invention is obtained from the resistors R3 and R4 of FIG. 1, and the waveforms of the output terminal Out and the inverted output terminal Out bar are shown in FIG.
The waveform has no distortion as shown in FIG. The reason is that the high level of the output terminal Out is in a state where no current flows through the resistor R3 or the resistor R4, that is, equal to the power supply voltage Vcc. On the other hand, the low level of the output terminal Out is (Vc
c-R3.Ic), and no nonlinearity of the diode is visible.

Therefore, there is no distortion in the output waveform, and the logical consistency with the next-stage ECL logic circuit is good.

In the above description, the case where one diode constituted by the transistors Q14, Q16, Q18 and Q20 is inserted has been described. However, N diodes (N is a natural number) may be inserted. Alternatively, the diodes may be eliminated only by the transistors Q13, Q15, Q17, and Q19. The circuit gain can be increased by inserting N diodes as compared with the case where the diodes are deleted.

[0048]

As described above, in the ECL logic circuit of the present invention, the internal output load is constituted by the transistor and the resistor connected between the collector and the power supply of the transistor, and the AC effective impedance of the output load is reduced. A high-speed ECL logic circuit can be realized.

The output terminal to the external circuit is connected to a resistive load, the output waveform has no distortion, and the logical consistency with the next-stage ECL logic circuit is good.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining a DC load resistance RL (DC) and an AC load resistance RL (AC).

FIG. 3 is a characteristic diagram showing a switching response of the ECL logic circuit shown in FIG. 1;

FIG. 4 shows a conventional resistive load type ECL divider circuit.

[Explanation of symbols]

3,3 'Master circuit transistor pair 4,4' Slave circuit transistor pair 10,20,30,40 Master / slave flip-flop 100,200 Divider circuit Q1-Q19 Transistor R1-R4 Resistance

Claims (5)

(57) [Claims] 1. A load at an output stage for outputting to an external circuit is constituted by a resistor, and a load from an input stage to the output stage is constituted by a transistor having a collector connected to a power supply via a resistor. ECL logic circuit. 2. The load of the output stage is constituted by the resistor and N (N is a natural number) diodes connected in series to the resistor, and the load from the input stage to the output stage is defined by the transistor and the transistor. 2. The ECL logic circuit according to claim 1, wherein said ECL logic circuit comprises N diodes connected in series to an emitter of said transistor. 3. A first differential transistor constituting a first differential transistor.
And a second transistor; third and fourth transistors constituting a second differential transistor; a fifth transistor having a collector connected to the emitter of the first transistor and applying an input signal to a base; A sixth transistor having a collector connected to the emitter of the third transistor, having the emitter commonly connected to the emitter of the fifth transistor, and applying an inverted signal of the input signal to a base; and the first transistor A seventh transistor having a collector connected to an emitter, a base connected to a power supply, and a collector connected to a power supply via a first resistor; a collector of the second transistor connected to an emitter, and a base connected to a power supply. An eighth transistor having a collector connected to a power supply via a second resistor, and the first transistor The collector of the collector third transistor connected in common, said collector and the collector of the fourth transistor of the second transistor are connected in common, said base of said third transistor second
An ECL logic circuit, wherein the ECL logic circuit is connected to a collector of the first transistor, and a base of the fourth transistor is connected to a collector of the first transistor. 4. N (N is a natural number) diodes between the collector of the first transistor and the emitter of the seventh transistor and between the collector of the second transistor and the emitter of the eighth transistor. The ECL logic circuit according to claim 3, wherein the ECL logic circuit is inserted. 5. The ECL logic circuit according to claim 2, wherein said transistors are all NPN transistors, and said diodes are diodes connecting a base and a collector of said NPN transistor.