JPH0750528A - Operational amplifier - Google Patents
Operational amplifierInfo
- Publication number
- JPH0750528A JPH0750528A JP5194868A JP19486893A JPH0750528A JP H0750528 A JPH0750528 A JP H0750528A JP 5194868 A JP5194868 A JP 5194868A JP 19486893 A JP19486893 A JP 19486893A JP H0750528 A JPH0750528 A JP H0750528A
- Authority
- JP
- Japan
- Prior art keywords
- buffer circuit
- operational amplifier
- current
- current mirror
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、主に携帯用通信機等に
用いられる演算増幅器に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier mainly used in portable communication devices and the like.
【０００２】[0002]
【従来の技術】従来の演算増幅器１０は、図５に示すよ
うに、差動増幅段１とカレントミラー段２を備え、差動
増幅段１は、上下に対称配置された第一、第二差動増幅
回路１ａ、１ｂで、カレントミラー段２は、上下に対称
配置された第一、第二カレントミラー回路２ａ、２ｂで
それぞれ構成されており、カレントミラー回路２ａ、２
ｂの共通出力に、バッファ回路３を接続して構成されて
いる。2. Description of the Related Art A conventional operational amplifier 10 includes a differential amplification stage 1 and a current mirror stage 2 as shown in FIG. 5, and the differential amplification stage 1 is provided with first and second symmetrically arranged vertically. In the differential amplifier circuits 1a and 1b, the current mirror stage 2 is composed of first and second current mirror circuits 2a and 2b which are vertically symmetrically arranged.
The buffer circuit 3 is connected to the common output of b.
【０００３】すなわち、第一差動増幅回路１ａは、一対
のＮＰＮ型のトランジスターＱ１、Ｑ２で、第二差動増
幅回路１ｂは、一対のＰＮＰ型のトランジスターＱ４、
Ｑ５でそれぞれ構成されている。That is, the first differential amplifier circuit 1a is a pair of NPN type transistors Q1 and Q2, and the second differential amplifier circuit 1b is a pair of PNP type transistors Q4 and Q4.
Each is composed of Q5.
【０００４】一方、第一カレントミラー回路２ａは、Ｐ
ＮＰ型の３つのトランジスタＱ７、Ｑ８、Ｑ９からな
り、また、第二カレントミラー回路２ｂは、ＮＰＮ型の
３つのトランジスタＱ１０、Ｑ１１、Ｑ１２でそれぞれ
構成されている。On the other hand, the first current mirror circuit 2a has a P
It is composed of three NP type transistors Q7, Q8, Q9, and the second current mirror circuit 2b is composed of three NPN type transistors Q10, Q11, Q12, respectively.
【０００５】そして、上記の第一、第二差動増幅回路１
ａ、１ｂの一方のトランジスタＱ１、Ｑ４のベースは、
正相入力端子ＩＮ1 に、他方のトランジスタＱ２、Ｑ５
のベースは、逆相入力端子ＩＮ2 にそれぞれ共通に接続
されている。Then, the above-mentioned first and second differential amplifier circuits 1
The bases of the transistors Q1 and Q4 of one of a and 1b are
The positive phase input terminal IN 1, the other transistor Q2, Q5
The bases of are commonly connected to the negative-phase input terminal IN 2 .
【０００６】また、第一差動増幅回路１ａを構成するト
ランジスタＱ１のコレクタは、第一差動増幅回路１ａの
出力となり、第一カレントミラー回路２ａの入力部に接
続され、トランジスタＱ２のコレクタは正電源に接続さ
れ、トランジスタＱ１、Ｑ２のエミッタは第一定電流回
路４ａに共通して接続されている。また、第二差動増幅
回路１ｂを構成するトランジスタＱ４のコレクタは、第
二差動増幅回路１ｂの出力となり、第二カレントミラー
回路２ｂの入力部に接続され、トランジスタＱ５のコレ
クタは負電源に接続され、トランジスタＱ４、Ｑ５のエ
ミッタは第二定電流回路４ｂに共通して接続されてい
る。なお、第一、第二定電流回路４ａ、４ｂは、たとえ
ば接合型のＦＥＴからなるものである。Further, the collector of the transistor Q1 constituting the first differential amplifier circuit 1a becomes the output of the first differential amplifier circuit 1a, is connected to the input part of the first current mirror circuit 2a, and the collector of the transistor Q2 is It is connected to a positive power supply, and the emitters of the transistors Q1 and Q2 are commonly connected to the first constant current circuit 4a. The collector of the transistor Q4 that constitutes the second differential amplifier circuit 1b becomes the output of the second differential amplifier circuit 1b and is connected to the input part of the second current mirror circuit 2b, and the collector of the transistor Q5 serves as a negative power source. The emitters of the transistors Q4 and Q5 are commonly connected to the second constant current circuit 4b. The first and second constant current circuits 4a and 4b are, for example, junction type FETs.
【０００７】そして、第一、第二カレントミラー回路２
ａ、２ｂの出力部となるトランジスタＱ９、Ｑ１２のコ
レクタは、バッファ回路３入力部に共通に接続されると
ともに、正負電源にかけて位相補償用のコンデンサＣ
１、Ｃ２が接続されている。また、バッファ回路３は、
例えば、エミッタフォロワー等で構成され、その内部に
存在する入力インピーダンスが、第一、第二カレントミ
ラー回路２ａ、２ｂに対する負荷インピーダンスＺ0 と
して作用する。Then, the first and second current mirror circuits 2
The collectors of the transistors Q9 and Q12, which are the output parts of a and 2b, are commonly connected to the input part of the buffer circuit 3 and are connected to the positive and negative power supplies to form a capacitor C for phase compensation.
1, C2 are connected. In addition, the buffer circuit 3
For example, an input impedance formed by an emitter follower or the like and existing therein acts as a load impedance Z 0 for the first and second current mirror circuits 2a and 2b.
【０００８】演算増幅器１０は、第一、第二カレントミ
ラー回路２ａ、２ｂの動作電流が、第一、第二差動増幅
回路１ａ、１ｂのトランジスタＱ１、Ｑ２、Ｑ４、Ｑ５
のコレクタ電流で一義的に決定されるため、入力信号電
圧に応じた電流が負荷インピーダンスＺ0 に流れ、電源
電圧の変動や温度変化の影響を受けにくく、安定した出
力特性が得られるとともに、比較的低電流で動作すると
いう利点を有するものである。しかし、さらなる低消費
電流化という市場ニーズに対応するためには、より低い
電流で動作する必要があった。In the operational amplifier 10, the operating currents of the first and second current mirror circuits 2a and 2b are the same as the transistors Q1, Q2, Q4 and Q5 of the first and second differential amplifier circuits 1a and 1b.
Since it is uniquely determined by the collector current of, the current according to the input signal voltage flows into the load impedance Z 0 , is not easily affected by the fluctuation of the power supply voltage and the temperature change, and stable output characteristics can be obtained. It has the advantage of operating at a relatively low current. However, it has been necessary to operate at a lower current in order to meet the market need for further lower current consumption.
【０００９】そのため、低消費電流で動作する演算増幅
器２０として、図６に示すように、トランジスタＱ２
１、Ｑ２２、Ｑ２５、Ｑ２６からなるダイヤモンド型の
バッファ回路１３を用い、トランジスターＱ２１、Ｑ２
２の電流源に定電流回路５ａ、５ｂを用いたものを開発
中であった。Therefore, as an operational amplifier 20 that operates with low current consumption, as shown in FIG.
A diamond type buffer circuit 13 composed of 1, Q22, Q25 and Q26 is used, and transistors Q21 and Q2 are used.
A current source using the constant current circuits 5a and 5b as the second current source was under development.
【００１０】[0010]
【発明が解決しようとする課題】ところが、最近の携帯
用通信機等において、さらなる低消費電流化を行う必要
があり、微小電流で動作する演算増幅器が求められてい
る。しかしながら、上記従来例の演算増幅器２０におい
ては、微小電流で動作させると、入力波形に対する出力
波形の応答性が低くなるという欠点があった。特に、波
形の立ち下がり部では、立ち下がり時間が長くなり高速
追従性が悪く波形歪が生じ、また、立ち下がり後も微小
な振動が残り回路の安定性を低下させていた。However, in recent portable communication devices and the like, it is necessary to further reduce the current consumption, and there is a demand for an operational amplifier that operates with a minute current. However, the operational amplifier 20 of the above-mentioned conventional example has a drawback that the response of the output waveform with respect to the input waveform becomes low when operated with a minute current. In particular, at the trailing edge of the waveform, the trailing time is long, the high-speed followability is poor, and waveform distortion occurs, and even after the trailing edge, a small amount of vibration remains to reduce the stability of the circuit.
【００１１】本発明の目的は、低消費電流で回路の安定
性が高く高速な応答性を有する演算増幅器を提供するこ
とにある。An object of the present invention is to provide an operational amplifier which has low current consumption, high circuit stability, and high-speed response.
【００１２】[0012]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明においては、一対のカレントミラー段と、
該カレントミラー段の共通出力に接続されるダイヤモン
ド型のバッファ回路とを備えた演算増幅器において、前
記バッファ回路の入力段トランジスタのベースとエミッ
タ間に、コンデンサを接続したことを特徴とするもので
ある。To achieve the above object, in the present invention, a pair of current mirror stages,
In an operational amplifier including a diamond type buffer circuit connected to a common output of the current mirror stage, a capacitor is connected between a base and an emitter of an input stage transistor of the buffer circuit. .
【００１３】また、一対のカレントミラー段と、該カレ
ントミラー段の共通出力に接続されるダイヤモンド型の
バッファ回路とを備えた演算増幅器において、前記バッ
ファ回路の入力段トランジスタのベースとエミッタ間
に、コンデンサを接続するとともに、前記バッファ回路
の電流源を、前記カレントミラー段の動作電流で制御し
たことを特徴とするものである。Further, in an operational amplifier including a pair of current mirror stages and a diamond type buffer circuit connected to a common output of the current mirror stages, between the base and emitter of the input stage transistor of the buffer circuit, It is characterized in that a capacitor is connected and the current source of the buffer circuit is controlled by the operating current of the current mirror stage.
【００１４】また、正負の入力端子を有する一対の差動
増幅段と、該差動増幅段の出力に接続される一対のカレ
ントミラー段と、該カレントミラー段の共通出力に接続
されるダイヤモンド型のバッファ回路とを備えた演算増
幅器において、前記バッファ回路の入力段トランジスタ
のベースとエミッタ間に、コンデンサを接続したことを
特徴とするものである。Further, a pair of differential amplification stages having positive and negative input terminals, a pair of current mirror stages connected to the outputs of the differential amplification stages, and a diamond type connected to the common output of the current mirror stages. In the operational amplifier including the buffer circuit, the capacitor is connected between the base and the emitter of the input stage transistor of the buffer circuit.
【００１５】また、正負の入力端子を有する一対の差動
増幅段と、該差動増幅段の出力に接続される一対のカレ
ントミラー段と、該カレントミラー段の共通出力に接続
されるダイヤモンド型のバッファ回路とを備えた演算増
幅器において、前記バッファ回路の入力段トランジスタ
のベースとエミッタ間に、コンデンサを接続するととも
に、前記バッファ回路の電流源を、前記カレントミラー
段の動作電流で制御したことを特徴とするものである。Also, a pair of differential amplification stages having positive and negative input terminals, a pair of current mirror stages connected to the outputs of the differential amplification stages, and a diamond type connected to the common output of the current mirror stages. And a capacitor is connected between the base and the emitter of the input stage transistor of the buffer circuit, and the current source of the buffer circuit is controlled by the operating current of the current mirror stage. It is characterized by.
【００１６】[0016]
【作用】上記の構成によれば、バッファ回路の入力段ト
ランジスタのベースとエミッタ間にコンデンサを接続す
ることにより、入力波形の過渡域での高速な電圧変化に
応じた電流を、バッファ回路に流し込むことで、入力波
形に対する出力波形の応答性を向上することができる。
また、バッファ回路に電流を供給する電流源を、入力信
号電圧に応じた電流が流れているカレントミラー段の動
作電流で制御するようにしたため、入力信号の電圧変化
に応じて、バッファ回路への供給電流が変化し、入力波
形に対する出力波形の応答性がより向上する。According to the above construction, by connecting the capacitor between the base and the emitter of the input stage transistor of the buffer circuit, a current corresponding to a fast voltage change in the transient region of the input waveform is supplied to the buffer circuit. Thus, the response of the output waveform with respect to the input waveform can be improved.
Further, since the current source that supplies the current to the buffer circuit is controlled by the operating current of the current mirror stage in which the current corresponding to the input signal voltage is flowing, the buffer circuit is controlled according to the voltage change of the input signal. The supply current changes, and the responsiveness of the output waveform to the input waveform is further improved.
【００１７】[0017]
【実施例】以下、本発明による演算増幅器の実施例を図
面を用いて説明する。なお、従来例と同一もしくは相当
する部分には同一符号を付し、その説明を省略する。Embodiments of the operational amplifier according to the present invention will be described below with reference to the drawings. The same or corresponding parts as those of the conventional example are designated by the same reference numerals, and the description thereof will be omitted.
【００１８】本発明は、入力波形の過渡域での高速な電
圧変化に応じた電流を、バッファ回路に流すことを特徴
とするものである。すなわち、図１に示すように、差動
増幅段１、カレントミラー段２およびバッファ回路２３
からなり、バッファ回路２３の入力段トランジスタＱ２
１、Ｑ２２のベースとエミッタ間にコンデンサＣＡ１、
ＣＡ２を接続して、演算増幅器３０を構成している。The present invention is characterized in that a current corresponding to a fast voltage change in a transient region of an input waveform is passed through a buffer circuit. That is, as shown in FIG. 1, the differential amplifier stage 1, the current mirror stage 2, and the buffer circuit 23.
And the input stage transistor Q2 of the buffer circuit 23.
1, a capacitor CA1 between the base and emitter of Q22,
The operational amplifier 30 is configured by connecting CA2.
【００１９】演算増幅器３０は、コンデンサＣＡ１、Ｃ
Ａ２により、入力波形の立上がりおよび立ち下がりでの
高速な電圧変化に応じた電流が、バッファ回路２３の出
力段のトランジスタＱ２５、Ｑ２６に流れ、入力波形に
対する出力波形の応答性が向上する。The operational amplifier 30 includes capacitors CA1 and C1.
Due to A2, a current corresponding to a fast voltage change at the rising and falling edges of the input waveform flows through the transistors Q25 and Q26 at the output stage of the buffer circuit 23, and the response of the output waveform to the input waveform is improved.
【００２０】本発明の演算増幅器３０の効果を確認する
ため、図２に示す回路を用いて、従来例の演算増幅器２
０を用いた場合と、本発明の演算増幅器３０を用いた場
合の波形の応答特性をシミュレーションした。その結果
を図３に示す。なお、図２の回路条件としては、演算増
幅器２０および３０の出力に２ｋΩの抵抗Ｒ１と１０ｐ
ＦのコンデンサＣ３を並列に接続し、電源電圧Ｖｃｃを
±２．５ｖ、動作電流を０．６ｍＡとし、入力に１ＭＨ
ｚで３Ｖｐｐの矩形波を加えたものである。In order to confirm the effect of the operational amplifier 30 of the present invention, the circuit shown in FIG.
The response characteristics of the waveform when 0 was used and when the operational amplifier 30 of the present invention was used were simulated. The result is shown in FIG. The circuit conditions shown in FIG. 2 are as follows: the outputs of the operational amplifiers 20 and 30 are 2 kΩ resistors R1 and 10 p.
The capacitor C3 of F is connected in parallel, the power supply voltage Vcc is ± 2.5v, the operating current is 0.6mA, and the input is 1MH.
It is a waveform obtained by adding a rectangular wave of 3 Vpp to z.
【００２１】図３の特性は、図２の回路の出力波形をシ
ミュレーションしたもので、実線は本発明の演算増幅器
３０の特性で、コンデンサＣＡ１、ＣＡ２にそれぞれ５
ｐＦを用いたものである。また、破線は従来例の演算増
幅器２０の特性である。図３の特性から、本発明の演算
増幅器３０では、立ち下がり部での波形の収束する時間
が従来例の演算増幅器２０より短く、また、立ち下がり
後継続した振動も見られず、波形歪および安定性が改善
されていることが判る。The characteristic of FIG. 3 is a simulation of the output waveform of the circuit of FIG. 2, and the solid line is the characteristic of the operational amplifier 30 of the present invention.
It uses pF. The broken line is the characteristic of the operational amplifier 20 of the conventional example. From the characteristics of FIG. 3, in the operational amplifier 30 of the present invention, the time at which the waveform converges at the falling portion is shorter than that of the operational amplifier 20 of the conventional example, and no continuous vibration is observed after the falling, resulting in waveform distortion and It can be seen that the stability is improved.
【００２２】また、図４に示すように、バッファ回路３
３の入力段トランジスタＱ２１、Ｑ２２のベースとエミ
ッタ間にコンデンサＣＡ１、ＣＡ２を接続するととも
に、ＮＰＮ型トランジスタＱ２３を、そのコレクタをバ
ッファ回路３３のトランジスタＱ２１のエミッタとＱ２
６のベースの接続点に接続し、エミッタを負電源に接続
し、ベースを第二カレントミラー回路２ｂのトランジス
タＱ１０とＱ１１の共通ベースに接続する。さらに、Ｐ
ＮＰ型トランジスタＱ２４を、そのコレクタを、バッフ
ァ回路３３のトランジスタＱ２２のエミッタとＱ２５の
ベースの接続点に接続し、エミッタを正電源に接続し、
ベースを第一カレントミラー回路２ａのトランジスタＱ
７とＱ８の共通ベースに接続して、演算増幅器４０を構
成してもよい。Further, as shown in FIG. 4, the buffer circuit 3
The capacitors CA1 and CA2 are connected between the bases and emitters of the input stage transistors Q21 and Q22 of FIG. 3, and the NPN transistor Q23 has its collector connected to the emitter of the transistor Q21 of the buffer circuit 33 and Q2.
6 is connected to the connection point of the base, the emitter is connected to the negative power supply, and the base is connected to the common base of the transistors Q10 and Q11 of the second current mirror circuit 2b. Furthermore, P
The collector of the NP-type transistor Q24 is connected to the connection point between the emitter of the transistor Q22 and the base of Q25 of the buffer circuit 33, and the emitter is connected to the positive power source.
The base is the transistor Q of the first current mirror circuit 2a.
The operational amplifier 40 may be configured by connecting to the common base of 7 and Q8.
【００２３】演算増幅器４０は、トランジスタＱ２３、
Ｑ２４が、バッファ回路３３の電流源となり、各カレン
トミラー回路２ａ、２ｂによりその動作電流が制御さ
れ、入力信号の電圧変化に応じて、バッファ回路３３の
トランジスタＱ２１、Ｑ２２の動作電流およびトランジ
スタＱ２５、Ｑ２６のベース電流を供給するため、コン
デンサＣＡ１、ＣＡ２の効果と重なって、入力波形に対
する出力波形の応答性がより向上する。The operational amplifier 40 includes a transistor Q23,
Q24 serves as a current source of the buffer circuit 33, the operating current of which is controlled by the current mirror circuits 2a and 2b, and the operating currents of the transistors Q21 and Q22 of the buffer circuit 33 and the transistor Q25 are Since the base current of Q26 is supplied, the effect of the capacitors CA1 and CA2 overlaps, and the responsiveness of the output waveform with respect to the input waveform is further improved.
【００２４】[0024]
【発明の効果】以上説明したように、本発明にかかる演
算増幅器によれば、微小な動作電流でも出力波形の応答
性が向上するとともに、波形歪みが改善された演算増幅
器を得ることができ、携帯用通信機等の低消費電流化に
寄与することができる。As described above, according to the operational amplifier of the present invention, it is possible to obtain an operational amplifier in which the response of the output waveform is improved even with a minute operating current and the waveform distortion is improved. It is possible to contribute to reduction in current consumption of portable communication devices and the like.
【図１】本発明の実施例による演算増幅器の回路図であ
る。FIG. 1 is a circuit diagram of an operational amplifier according to an embodiment of the present invention.
【図２】波形の応答特性測定回路図である。FIG. 2 is a circuit diagram for measuring a response characteristic of a waveform.
【図３】本発明の実施例による演算増幅器の波形の応答
特性図である。FIG. 3 is a waveform response characteristic diagram of an operational amplifier according to an embodiment of the present invention.
【図４】第二の実施例による演算増幅器の回路図であ
る。FIG. 4 is a circuit diagram of an operational amplifier according to a second embodiment.
【図５】第一の従来例の演算増幅器の回路図である。FIG. 5 is a circuit diagram of a first conventional operational amplifier.
【図６】第二の従来例の演算増幅器の回路図である。FIG. 6 is a circuit diagram of a second conventional operational amplifier.
１ 差動増幅段 １ａ、１ｂ 第一、第二差動増幅回路 ２ カレントミラー段 ２ａ、２ｂ 第一、第二カレントミラー回路 ４ａ、４ｂ 定電流回路 ２３、３３ バッファ回路 ３０、４０ 演算増幅器 DESCRIPTION OF SYMBOLS 1 differential amplification stage 1a, 1b 1st, 2nd differential amplification circuit 2 current mirror stage 2a, 2b 1st, 2nd current mirror circuit 4a, 4b constant current circuit 23, 33 buffer circuit 30, 40 operational amplifier
Claims (4)
ラー段の共通出力に接続されるダイヤモンド型のバッフ
ァ回路とを備えた演算増幅器において、前記バッファ回
路の入力段トランジスタのベースとエミッタ間に、コン
デンサを接続したことを特徴とする演算増幅器。1. An operational amplifier comprising a pair of current mirror stages and a diamond type buffer circuit connected to a common output of the current mirror stages, wherein an input stage transistor of the buffer circuit has a base and an emitter between the base and the emitter. An operational amplifier characterized by connecting a capacitor.
ラー段の共通出力に接続されるダイヤモンド型のバッフ
ァ回路とを備えた演算増幅器において、前記バッファ回
路の入力段トランジスタのベースとエミッタ間に、コン
デンサを接続するとともに、前記バッファ回路の電流源
を、前記カレントミラー段の動作電流で制御したことを
特徴とする演算増幅器。2. An operational amplifier including a pair of current mirror stages and a diamond type buffer circuit connected to a common output of the current mirror stages, wherein an input stage transistor of the buffer circuit has a base and an emitter between the base and the emitter. An operational amplifier, wherein a capacitor is connected and a current source of the buffer circuit is controlled by an operating current of the current mirror stage.
と、該差動増幅段の出力に接続される一対のカレントミ
ラー段と、該カレントミラー段の共通出力に接続される
ダイヤモンド型のバッファ回路とを備えた演算増幅器に
おいて、前記バッファ回路の入力段トランジスタのベー
スとエミッタ間に、コンデンサを接続したことを特徴と
する演算増幅器。3. A pair of differential amplification stages having positive and negative input terminals, a pair of current mirror stages connected to the outputs of the differential amplification stages, and a diamond type connected to a common output of the current mirror stages. In the operational amplifier including the buffer circuit of claim 1, a capacitor is connected between the base and the emitter of the input stage transistor of the buffer circuit.
と、該差動増幅段の出力に接続される一対のカレントミ
ラー段と、該カレントミラー段の共通出力に接続される
ダイヤモンド型のバッファ回路とを備えた演算増幅器に
おいて、前記バッファ回路の入力段トランジスタのベー
スとエミッタ間に、コンデンサを接続するとともに、前
記バッファ回路の電流源を、前記カレントミラー段の動
作電流で制御したことを特徴とする演算増幅器。4. A pair of differential amplification stages having positive and negative input terminals, a pair of current mirror stages connected to the outputs of the differential amplification stages, and a diamond type connected to the common output of the current mirror stages. And a capacitor is connected between the base and the emitter of the input stage transistor of the buffer circuit, and the current source of the buffer circuit is controlled by the operating current of the current mirror stage. An operational amplifier characterized by:
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19486893A JP3214174B2 (en) | 1993-08-05 | 1993-08-05 | Operational amplifier |
| US08/280,716 US5515005A (en) | 1993-07-27 | 1994-07-26 | Operational amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19486893A JP3214174B2 (en) | 1993-08-05 | 1993-08-05 | Operational amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0750528A true JPH0750528A (en) | 1995-02-21 |
| JP3214174B2 JP3214174B2 (en) | 2001-10-02 |
Family
ID=16331644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19486893A Expired - Fee Related JP3214174B2 (en) | 1993-07-27 | 1993-08-05 | Operational amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3214174B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002021682A1 (en) * | 2000-09-08 | 2002-03-14 | Neo Tek Research Co., Ltd | High gain low power op amp for driving the flat panel display |
| JP2007181019A (en) * | 2005-12-28 | 2007-07-12 | Advantest Corp | Power amplification circuit and testing apparatus |
| JP2011009906A (en) * | 2009-06-24 | 2011-01-13 | New Japan Radio Co Ltd | Output circuit |
-
1993
- 1993-08-05 JP JP19486893A patent/JP3214174B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002021682A1 (en) * | 2000-09-08 | 2002-03-14 | Neo Tek Research Co., Ltd | High gain low power op amp for driving the flat panel display |
| JP2007181019A (en) * | 2005-12-28 | 2007-07-12 | Advantest Corp | Power amplification circuit and testing apparatus |
| JP4690887B2 (en) * | 2005-12-28 | 2011-06-01 | 株式会社アドバンテスト | Power amplification circuit and test apparatus |
| JP2011009906A (en) * | 2009-06-24 | 2011-01-13 | New Japan Radio Co Ltd | Output circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3214174B2 (en) | 2001-10-02 |
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