JP2990029B2 - Method of manufacturing complementary MISFET - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary MISFET in which a source and a drain are formed by solid-phase diffusion from an insulating film containing impurities, and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a MISFET is miniaturized, it is necessary to make a source / drain junction shallower.
In the case of a micro device having a size of about m, particularly a p-channel device, it is difficult to cope with it simply by lowering the energy of ion implantation. As a method for solving this problem, an insulating film containing impurities is used.
A method of forming a source / drain by solid-phase diffusion of an impurity has been proposed. IED ・
Technical Digest (IEDM Technic
al Digest), 1992, 897-900
In the page, an example of p-channel MISFET creation is shown in the same way as IDM Technical Digest, 1
993, pages 119-122, n-channel MI
An example of making an SFET has been reported.

FIG. 9 shows a method for manufacturing a p-channel device described in the above-mentioned document. First, after a gate insulating film 2 and a gate electrode 1 are formed on a substrate 3 by a known method, a silicon oxide film (BSG film) to which boron is added.
Is deposited over the entire surface by a chemical vapor deposition (CVD) method. In the example of the above-mentioned literature, boron-doped polysilicon is used as a gate electrode, and a nitrided oxide film formed by oxidizing and nitriding a substrate is used as a gate insulating film. Next, the BSG sidewall 8b is formed on the side surface of the gate electrode by anisotropically etching the deposited BSG film only in the vertical direction. Next, a deep source / drain 10 is formed by ion implantation. Finally, heat treatment is performed and BSG
Boron is diffused into the substrate from the side wall 8b to form a shallow source
The drain 11 is formed. At this time, the impurities of the deep source / drain 10 are electrically activated at the same time. When forming an n-channel device, a silicon oxide film (PSG film) doped with phosphorus is used instead of the BSG film.
Is used.

[0004]

SUMMARY OF THE INVENTION Silicon MISFET
In order to suppress power consumption, an n-channel element and a p-channel element are usually formed on the same substrate, and are used as a complementary structure. For this purpose, an n-type source / drain is provided in an n-channel portion on a wafer, and a p-type source / drain is provided in a
It is necessary to form a drain. In a normal ion implantation method, this can be easily realized by using photolithography. That is, when forming an n-channel element, an n-type impurity is ion-implanted with the p-channel portion covered with photoresist, and when forming a p-channel element, a p-type impurity is ion-implanted with the p-channel portion covered with photoresist. The n-type and p-type source / drain can be separately formed on the same substrate.

However, in the conventional solid-phase diffusion method described above, it is not easy to separately produce an n-type and a p-type depending on the location. To put it simply, after depositing an insulating film containing impurities (BSG film or PSG film) on the entire surface, it is sufficient to remove only unnecessary portions, but in order to remove the insulating film on the side surface of the gate, it is necessary to use an isotropic film. Etching is required, and at this time, the gate insulating film is simultaneously damaged. Also, B
Depositing an SG film or a PSG film only at a specific location on a substrate is impossible with a normal film forming method.

An object of the present invention is to provide a complementary MIS that solves the above-mentioned problems without impairing the reliability of the gate insulating film.
An object of the present invention is to provide an FET and a manufacturing method thereof.

[0007]

[0008]

Means for Solving the Problems The complementary MIS of the present invention
The method of manufacturing the FET includes a step of depositing a first insulating film on the semiconductor substrate after forming the gate electrode, and a step of forming the source and drain of the first conductive type FET on the substrate by photolithography and ion implantation. Forming the first insulating film by using photolithography and an anisotropic etch-back method except for a predetermined region on the substrate and a side surface of the gate electrode. depositing a second insulating film added with a second conductivity type impurity, from the second insulating film by heating the second conductivity type by diffusing the second conductivity type impurity into the substrate It is characterized by a step of forming the source and drain of the FET.

[0009]

As described above, it is difficult to realize a state where the insulating film of the diffusion source does not exist only in a specific portion of the substrate. Therefore, instead, a thin insulating film that functions to prevent impurity diffusion into the substrate is formed only on a part of the substrate, and then an insulating film of a diffusion source is deposited on the entire surface, thereby diffusing only a specific part of the substrate. To form a shallow junction. Specifically, after forming the gate electrode, a thin insulating film (suitable for silicon oxide or silicon nitride) is deposited by a CVD method, and only the p-channel portion is covered with a photoresist while covering the n-channel portion. Etch back the membrane.
At this time, since the etching is performed anisotropically only in the vertical direction, the gate insulating film is not damaged. Next, BSG
When a film is deposited on the entire surface of the substrate and subjected to a heat treatment, boron in the BSG film diffuses into the substrate in the p-channel portion to form p-type source / drain, but in the n-channel portion, boron becomes the first insulating film. It is blocked and does not reach the substrate. The source / drain of the n-channel part where the shallow junction can be easily formed is
It is formed by an ion implantation method.

In the above description, the solid-phase extension method is applied only to the p-channel device.
The source and drain can be formed by solid phase diffusion from the PSG film, and the p-type source and drain can be formed by ion implantation. However, it is more appropriate to apply solid-phase diffusion to the p-type source / drain where it is difficult to form a shallow junction.

In the p-channel portion, the BSG film directly contacts the substrate, whereas in the n-channel portion, an insulating film is sandwiched between the BSG film and the substrate. In an insulating film such as a silicon oxide film or a silicon nitride film, diffusion of impurities such as boron is usually slower than in a silicon substrate. Therefore, by heating, boron in the BSG film diffuses into the silicon substrate in the p-channel region to form a shallow p-type source / drain, but is blocked by a thin insulating film sandwiched in the n-channel portion, and boron is removed. Does not reach the substrate. This makes it possible to separately produce an n-type element and a p-type element depending on the location on the substrate.

In addition, as a result of the side surface of the gate insulating film not being in direct contact with the BSG film, there is also an additional effect of suppressing deterioration of the reliability of the gate insulating film due to penetration of boron from the BSG film into the gate insulating film. can get.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 to 7 are diagrams showing steps of a method for manufacturing a complementary MISFET according to a first embodiment of the present invention. For the reasons described above, a description will be given below assuming that solid-phase diffusion is applied to a p-channel device. After forming the gate insulating film 2 and the gate electrode 1 by a usual method, an insulating film 5 for preventing diffusion (silicon oxide film or silicon nitride film) is formed on the entire surface.
Is deposited to a thickness of about 10 nm. Next, the p-channel portion is covered with a photoresist 7a, and n-type impurity ions such as arsenic or phosphorus are implanted through the insulating film 5 in the n-channel region to thereby form an n-type impurity.
The shallow source / drain 6 of the ISFET is formed. At this time, the insulating film 5 also functions to prevent contamination from entering at the time of ion implantation and to prevent the n-type source / drain 6 from deepening due to ion channeling. Next, the photoresist 7a is peeled off, the n-channel portion is newly covered with the photoresist 7b, and the insulating film 5 in the p-channel region is anisotropically etched back in the vertical direction by a known dry etching method. As a result, the substrate surface in the p-channel region is exposed, and an insulating film 5b is formed on the side surface of the gate electrode. Next, the photoresist 7b is removed, and a BSG film 8 is deposited on the entire surface. Then, it is anisotropically etched back in the vertical direction to form BSG side walls 8a and 8b on the side surfaces of the gate electrode. Next, by performing normal photoresist formation and ion implantation twice, a deep n-type source / drain 9 and a deep p-type source / drain 10 are formed. The deep source / drain functions to lower the resistance of the source / drain, facilitate the formation of salicide, and prevent the junction from being broken at the time of opening the connection hole with the wiring. Finally, heating is performed to activate the impurities in the ion-implanted regions 6, 9, and 10, and to diffuse boron from the BSG side wall 8b into the substrate to form shallow p-type source / drain 11. At this time, in the n-channel region, the BSG film hardly reaches the substrate because boron in the BSG side wall 8a is blocked by the insulating film 5a, and the BSG film does not affect the nMOS. Further, the insulating films 5a and 5b prevent boron in the BSG film 8 from entering the gate insulating film 1 and prevent the reliability of the gate insulating film from lowering. Thereafter, through a normal interphase insulating film deposition, contact hole formation, wiring formation, etc., the complementary type MISF is formed.
ET is completed.

In the above embodiment, the shallow n-type source / drain 6 is ion-implanted after the insulating film 5 is deposited. However, this order is irrelevant to the essence of the present invention and may be reversed.
In addition, although it has been described that the insulating film 5 is anisotropically etched back in the vertical direction, if a material capable of obtaining a sufficient etch-back selectivity between the insulating film 5 and the gate insulating film 2 is used, the isotropic It is also possible to use etching. BS
The case where the diffusion of boron from the G film 8 and the heat treatment for activating the ion-implanted impurities are used has been described, but may be performed separately.

In the first embodiment, the case where the source / drain is considered to be the most common, in which the source / drain is composed of two regions of a shallow portion and a deep portion, has been described. Not essence. Then, more basic,
A second embodiment according to the present invention when the source / drain consists only of a shallow region will be described with reference to FIG. B
Up to the point where the SG film 8 is deposited on the entire surface of the substrate, it is the same as in the first embodiment. Thereafter, heat treatment is performed without etching back the BSG film 8 to diffuse boron in the BSG film 8 to form a shallow p-type source / drain 11 over the entire p-channel region. FIG. 8 shows the state at this time.
Thereafter, the MISFET is completed through ordinary deposition of an interlayer insulating film, formation of a contact hole, formation of a wiring, and the like. The BSG film 8 is used as it is as a part of the interlayer insulating film. The fact that the insulating film 5 prevents the gate insulating film from deteriorating is the same as in the first embodiment.

The complementary MISFE manufactured according to the present invention
T is, as shown in FIGS. 1 to 7 or 8, in the p-channel device, the BSG film 8 directly contacts the substrate surface,
The n-channel device is characterized in that the BSG film 8 is in contact with the insulating film 5 therebetween. Thus, the source / drain of the p-channel element can be formed shallow by solid phase diffusion. Further, the side surface of the gate electrode 1 is covered with the insulating film 5 and does not directly contact the BSG film 8. This prevents boron diffused from the BSG film 8 from entering the gate insulating film 2 and deteriorating its reliability.

[0018]

As described above, the present invention forms a shallow p-type junction using solid-phase diffusion from a BSG film by forming an insulating film for preventing impurity diffusion only in a part of the substrate.
It can be formed only on a specific portion on the substrate. As a result, the solid-phase diffusion method from the BSG film becomes complementary MIS
It can be applied to the manufacture of FET. Further, since the side surface of the gate electrode does not directly contact the BSG film, the reliability of the gate insulating film is prevented from deteriorating.

[Brief description of the drawings]

FIG. 1 shows a complementary MISFE according to a first embodiment of the present invention.
FIG. 4 is a diagram showing steps of a method for manufacturing T.

FIG. 2 shows a complementary MISFE according to a first embodiment of the present invention.
FIG. 4 is a diagram showing steps of a method for manufacturing T.

FIG. 3 is a diagram showing a complementary MISFE according to a first embodiment of the present invention;
FIG. 4 is a diagram showing steps of a method for manufacturing T.

FIG. 4 shows a complementary MISFE according to the first embodiment of the present invention.
FIG. 4 is a diagram showing steps of a method for manufacturing T.

FIG. 5 is a diagram showing a complementary MISFE according to a first embodiment of the present invention;
FIG. 4 is a diagram showing steps of a method for manufacturing T.

FIG. 6 shows a complementary MISFE according to the first embodiment of the present invention.
FIG. 4 is a diagram showing steps of a method for manufacturing T.

FIG. 7 shows a complementary MISFE according to the first embodiment of the present invention.
FIG. 4 is a diagram showing steps of a method for manufacturing T.

FIG. 8 is a schematic sectional view showing a second embodiment of the complementary MISFET according to the present invention.

FIG. 9 is a diagram showing a conventional method for manufacturing a p-channel element.

[Explanation of symbols]

 Reference Signs List 1 gate electrode 2 gate insulating film 3 semiconductor substrate 3a n-channel region of semiconductor substrate 3b p-channel region of semiconductor substrate 4 element isolation insulating film 5, 5a, 5b diffusion prevention insulating film 6 shallow n-type source / drain 7a, 7b photoresist Reference Signs List 8 BSG film 8a, 8b BSG sidewall 9 Deep n-type source / drain 9 Deep p-type source / drain 9 Shallow p-type source / drain

Claims (3)

(57) [Claims] 1. A post-gate electrode formation, first on a semiconductor substrate
Depositing an insulating film, forming a shallow source / drain of the first conductivity type FET only in a predetermined region on the substrate using photolithography and ion implantation, and anisotropically etching back with photolithography. Removing the first insulating film except for a predetermined region on the substrate and a side surface of the gate electrode by using a method; and depositing a second insulating film doped with a second conductivity type impurity over the entire surface of the substrate. a step of a feature in that a step of forming the source and drain of the second shallow from the insulating film of the second conductivity type by diffusing the second conductivity type impurity into the substrate FET by heating To manufacture a complementary MISFET. 2. Using photolithography and ion implantation.
Deep source / drain of first conduction type and second conduction type
The complementary M according to claim 1, further comprising a step of forming.
Manufacturing method of ISFET. 3. The method according to claim 1, wherein the first insulating film is made of silicon oxide or nitride.
Silicon oxide and the second insulating film are silicon oxide doped with boron.
Con, first conductivity type is n-type, the second conductivity type is p-type, or claim 1 semiconductor substrate characterized in that it is a silicon 2
A manufacturing method of the complementary MISFET according to the above.