JP2986501B2 - Digital convergence correction device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a convergence correction device for a television receiver or a display having a cathode ray tube, and more particularly to an increase in processing speed and a reduction in circuit cost. The present invention relates to a digital convergence correction device suitable for a case.

[Conventional technology]

FIG. 8 is a block diagram showing a configuration of a conventional digital convergence correction device.

In the figure, reference numerals 1 and 2 denote H in raster scan, respectively.
Input terminals for (horizontal) blanking pulse and V (vertical) blanking pulse. 3 is blanking pulse 1,
An address generator that generates an address signal synchronized with the raster scan based on 2.

Reference numeral 4 denotes an address switch for switching an address input terminal of a memory 5, and reference numeral 5 denotes a memory for storing convergence correction data, using a RAM (random access memory) that can be read and written. 6 is a data switch for switching the data input / output terminal of the memory 5, 7 is a D / A converter with a latch, 8 is an LPF (low pass filter),
A convergence correction waveform output terminal 9 is connected to a CY amplifier (convergence yoke amplifier; not shown).

Reference numeral 10 denotes a CPU for operating the memory 5 and controlling various arithmetic operations.
(Processing device), 11 is a keyboard for instructing convergence adjustment, 12 is an input port for transmitting instructions from the keyboard 11 to the CPU 10, 13 is an adjustment pattern generator for generating an adjustment pattern signal, and 14 is an adjustment pattern output terminal And is connected to a video processing circuit (not shown) of the television receiver.

First, the circuit operation when performing convergence correction will be described.

When performing convergence correction, the address switch 4 and the data switch 6 each select a.

Now, it is assumed that the address generator 3 generates an address signal synchronized with the raster scan and reads the convergence correction data stored in the memory 5 via the address switch 4.

For reference, in a system of 63.5 μs in one horizontal period and 128 bytes of convergence correction data read out in one horizontal period, the period in which the address generator 3 reads data stored in the memory 5 is 63.5 μs ÷ 128 ≒ 500 ns. .

The data read from the memory 5 is transmitted to the data switch 6
After that, the data is fetched by the latched D / A converter 7 in synchronization with the data read timing by the address generator 3, and is sequentially converted from a digital signal to an analog signal. The D / A converter 7 with the latch holds the previous data until the next data is fetched.
It has a so-called latch function.

Thereafter, the signal output from the latched D / A converter 7 is input to a low-pass filter 8, where it is interpolated, and then output from a convergence correction waveform output terminal 9 to output a CY amplifier (not shown). Drive and perform convergence correction.

Next, a circuit operation when convergence adjustment is performed will be described.

During the convergence adjustment, the convergence correction operation is always performed because the adjuster checks the convergence state.

Therefore, first, the timing signal output separately from the address signal from the address generator 3 causes the adjustment pattern generator 13 to output a video signal of an adjustment pattern such as a cross hatch used for confirming a convergence state (that is, a video signal of an adjustment pattern (ie, , Adjustment pattern signal) is generated. And
The adjustment pattern signal is sent to the adjustment pattern output terminal 14.
The output signal is input to a video processing circuit (not shown) to display an adjustment pattern on the screen of the television receiver.

Next, the adjuster checks the convergence state based on the displayed adjustment pattern while referring to the adjustment pattern. When a part to be adjusted is found, the convergence adjustment instruction is sent from the keyboard 11 for the part.

The CPU 10 receives this instruction via the input port 12, switches the address switch 4 and the data switch 6 from a to b at an arbitrary timing, operates the memory 5, and thereafter returns from b to a. . That is, for example, at an arbitrary timing, the data is switched from a to b, necessary data among the data stored in the memory 5 is read and fetched, and thereafter, the data is returned from b to a. After creating desired new convergence correction data on the basis of the data, the data is switched from a to b at an arbitrary timing, and the data to be rewritten among the data stored in the memory 5 is rewritten with the created data. Then, b is returned to a.

The convergence adjustment is performed as described above,
In this case, there are the following problems.

That is, while the CPU 10 is operating the memory 5 by switching the address switch 4 and the data switch 6 from a to b, respectively, since the a of the data switch 6 is open, the latch When the attached D / A converter 7 fetches data from a of the data switch 6 in synchronization with the data read timing by the address generator 3 as described above, the data is undefined data unrelated to the convergence correction data. Therefore, if convergence correction is performed based on the data, normal convergence correction is not performed, and convergence correction completely independent of the screen position is performed.

FIG. 9 is an explanatory diagram showing a screen state at the time of convergence adjustment by the digital convergence correction device of FIG.

In the figure, reference numeral 81 denotes a screen of the television receiver, and reference numeral 82 denotes a horizontal display line of the adjustment pattern displayed on the screen 82. The vertical display lines are omitted.

Therefore, while the CPU 10 of FIG. 8 is operating the memory 5, the horizontal display line of the adjustment pattern is based on indefinite data unrelated to the convergence correction data.
Since convergence correction is performed irrespective of the screen position, the image is displayed at an abnormal position as shown at 83 in FIG.

In this way, when the convergence adjustment is performed, if the display line of the adjustment pattern is partially displayed at an abnormal position (hereinafter, this phenomenon is referred to as display position disturbance [convergence disturbance]), the screen becomes difficult to see. This makes it difficult to accurately confirm the convergence state.

Therefore, conventionally, for example, Japanese Patent Laid-Open No. 57-212492
As described in the publication, the address generator 3 reads a small amount of free time (several hundreds) from reading data at a certain address in the memory 5 to reading data at the next address.
ns), during which the CPU 10 performs a series of operations of switching the address switch 4 and the data switch 6 from a to b respectively, operating the memory 5, and returning from b to a again. I have to.

As a result, the D / A converter 7 with the latch operates the data switch 6
When the data from a is taken in, the address switch 4 and the data switch 6 are always in the state of being switched from b to a, respectively.
As described above, normal convergence correction data can be captured without capturing indefinite data, so that normal convergence correction according to the screen position can be performed based on the data.

[Problems to be solved by the invention]

As described above, in the prior art, during a short time (several hundred ns) between the time when the address generator 3 reads data at one address in the memory 5 and the time when the data at the next address is read, the CPU 10 However, since the address switch 4 and the data switch 6 must be switched and the memory 5 must be operated, a certain high-speed operation is required for the memory 5 and the peripheral circuits that control the memory 5. Therefore, when the operation speed of the convergence correction operation is to be further increased (in other words, when the data read timing by the address generator 3 is to be further increased), the memory 5 and the memory 5
Requires a very high-speed operation of the peripheral circuit for controlling the memory 5, but the operating speed of the memory 5 and the peripheral circuit for controlling the memory 5 itself is limited. Therefore, this increases the operating speed of the convergence correction operation. There was a problem that it becomes a restriction in the.

In addition, the CPU 10 switches between the address switch 4 and the data switch 6 and operates the memory 5 during a short idle time, so that complicated timing control is required. There is also a problem that the circuit scale of peripheral circuits and the like increases, and as a result, the cost increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a convergence correction device which can solve the above-mentioned problems of the conventional technology, can increase the operation speed of the convergence correction operation, and can realize low cost.

[Means for solving the problem]

In order to achieve the above object, according to the present invention, when a display screen of a cathode ray tube is divided into a plurality of regions, a memory for storing a convergence correction value in each region as convergence correction data, and a raster scan of the cathode ray tube. An address generating means for reading out the convergence correction data stored in the memory by generating a first address signal in synchronization with the first address signal and inputting the first address signal to the memory; By generating a second address signal at a timing and inputting the second address signal to the memory instead of the first address signal, the second address signal is stored in the memory instead of the address generating means. Processing means for reading or rewriting the convergence correction data; A convergence correction data read from the memory is taken in synchronization with a raster scan of the cathode ray tube, a digital-analog conversion means for converting a digital signal into an address signal and outputting the address signal, and adjusting the convergence adjustment on a display screen of the cathode ray tube. Adjustment pattern generating means for generating and outputting an adjustment pattern signal in synchronism with the raster scan of the cathode ray tube to display the pattern for use, and the processing means replaces the address generation means at the time of convergence adjustment. ,
An adjustment pattern signal erasing unit that erases the adjustment pattern signal output from the adjustment pattern generation unit when the convergence correction data stored in the memory is read or rewritten. I made it.

In addition, in the present invention, in addition to the above configuration, at the time of convergence adjustment, the first address signal generated by the address generating means is input to the processing means,
When the address value of the address signal is within the range that matches the convergence adjustment area, the convergence correction data stored in the memory is not read or rewritten.

[Action]

In the present invention, at the time of convergence adjustment, when the processing means reads or rewrites the convergence correction data stored in the memory in place of the address generation means, the adjustment pattern signal erasing means, The adjustment pattern signal output from the adjustment pattern generation means is deleted.

Therefore, even if the digital-to-analog conversion means takes in indefinite data during that time and performs convergence correction irrespective of the screen position based on the data, during that time, the display line of the adjustment pattern is displayed. Disappears from the screen. That is, a portion of the display line of the adjustment pattern whose display position is disturbed is erased from the screen.

In the present invention, in addition to the above configuration, the processing means inputs the first address signal generated by the address generating means at the time of convergence adjustment, and the address value of the first address signal is adjusted to the convergence adjustment. When the convergence correction data stored in the memory is within the range corresponding to the area, the reading or rewriting of the convergence correction data is not performed.

Therefore, during that period, the convergence correction data is read from the memory by the address generation means and is taken into the digital-analog conversion means, so that normal convergence correction corresponding to the screen position is performed. In addition, since the adjusting pattern signal erasing means does not operate during that period, the adjusting pattern signal from the adjusting pattern generating means is not erased by the adjusting pattern signal erasing means.

In this manner, during the period, normal convergence correction is performed and the adjustment pattern signal is not erased. Therefore, on the display screen, the display position of the display line of the adjustment pattern corresponding to the period is disturbed or the display line is distorted. It will be displayed normally without being erased.

That is, at the time of the convergence adjustment, the display line of the adjustment pattern can be normally displayed in the desired area on the display screen without any disturbance of the display position or the erased portion, so that the accurate convergence state can be obtained. Confirmation can be performed, and convergence adjustment accuracy and adjustment work efficiency can be improved.

As described above, according to the present invention, when performing the convergence adjustment, the processing unit may execute the convergence adjustment of the memory at an arbitrary timing except when the address value of the first address signal is within a specific range. Since the operation can be performed, unlike the related art, the processing means does not need to perform the operation of the memory while using a small free time, so that the memory and the peripheral area for controlling the memory are not required. There is no need to require a high-speed operation of the circuit, so that the operation speed of the convergence correction operation can be increased. In addition, since complicated timing control is not required, the circuit scale of peripheral circuits for controlling the memory does not increase, so that cost reduction can be realized.

〔Example〕

Hereinafter, as a first embodiment of the present invention, the configuration and operation of the circuit will be described with reference to FIG.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, components (1 to 14) that operate in the same manner as in FIG. 8 are given the same numbers as in FIG. Hereinafter, the components of FIG. 1 that are different from FIG. 8 will be described.

In the figure, 15 is a blanking circuit for erasing the adjustment pattern signal generated by the adjustment pattern generator 13, 16 is a delay circuit for adjusting the operation timing of the blanking circuit 15, and 17 is an address generator 3 for the CPU 10. This is an input port for inputting the address signal in which the error occurs.

 Hereinafter, the operation of the present embodiment will be described.

The circuit operation for performing the convergence correction is the same as that of the conventional example shown in FIG. 8, and the description thereof will be omitted.

Next, a circuit operation when convergence adjustment is performed will be described.

At the time of convergence adjustment, the convergence correction operation is always performed so that the adjuster checks the convergence state.

Therefore, first, an adjustment pattern signal is generated from the adjustment pattern generator 13 by a timing signal output separately from the address signal from the address generator 3. The adjustment pattern signal is supplied to the blanking circuit 15.
Is output from the adjustment pattern output terminal 14 via
The adjustment pattern is input to a video processing circuit (not shown) and displayed on the screen of the television receiver.

Next, the adjuster checks the convergence state based on the displayed adjustment pattern while referring to the adjustment pattern. When a part to be adjusted is found, the convergence adjustment instruction is sent from the keyboard 11 for the part.

The CPU 10 receives this instruction via the input port 12, switches the address switch 4 and the data switch 6 from a to b at an arbitrary timing within a certain period (described in detail later), and switches the memory 5 Operate, then b
Return to a.

At this time, a control signal generated by the CPU 10 for the address switch 4 and the data switch 6 is also input to the blanking circuit 15 via the delay circuit 16, whereby the blanking circuit 15 Blanking is applied to the adjustment pattern signal from the adjustment pattern generator 13 during the period from when the switch 4 and the data switch 6 are switched from a to b and back to b again. to erase).

Therefore, even if the D / A converter 7 with latches fetches indefinite data from the data switch 6a during that time, and convergence correction irrelevant to the screen position is performed based on the data, even during that time, The display line of the adjustment pattern is not displayed on the screen. That is, among the display lines of the adjustment pattern, a portion having a distorted display position is erased from the screen.

Note that the delay circuit 16 outputs the convergence correction waveform signal output from the D / A converter 7 to the LPF 8 and CY
In consideration of the delay caused by the amplifier (not shown) or the like, the blanking is performed so that the timing at which the convergence correction irrespective of the screen position is performed and the timing at which the display line of the adjustment pattern is erased coincide. This is for adjusting the operation timing of the circuit 15.

Now, the screen state at this time will be described with reference to FIG.

FIG. 2 is an explanatory diagram showing a screen state at the time of convergence adjustment by the digital convergence correction device of FIG.

In the figure, 81 is the screen of the television receiver as in FIG. 9, and 82 is a horizontal display line of the adjustment pattern displayed on the screen 82. The vertical display lines are omitted.

That is, during the period when the CPU 10 is operating the memory 5 (that is, during the period from when the address switch 4 and the data switch 6 are switched from a to b to when they are returned from b to a), the convergence correction data is The convergence correction independent of the screen position is performed based on the irrelevant indefinite data, but the horizontal display line of the adjustment pattern is the display position corresponding to the period, such as 83 shown in FIG. Since the disturbed portion is erased as shown by 93 in FIG. 2, it is possible to reduce the difficulty in viewing the screen.

However, because of this, the erased portion as shown by 93 in FIG. 2 exists in the display line of the adjustment pattern to be displayed, so that an accurate convergence state is confirmed. Is still insufficient. Therefore,
In the present embodiment, the above-mentioned problem is solved by using the operation described below together with the operation of the blanking circuit 15 described above.

FIG. 3 is an explanatory diagram showing the correspondence between scanning line numbers and screen positions. Here, the scanning line numbers are numbers sequentially assigned from the scanning lines on the screen.

In the figure, 1 is a coordinate indicating a scanning line number, 31 is an effective display screen, and 32 is a flyback period in raster scanning.
Reference numeral 34 denotes a screen position (that is, an adjustment point) where the adjuster intends to perform convergence adjustment. The adjustment point 34 is not displayed on the screen.

As can be seen from the figure, the effective display screen area is the scanning line number
20 to 505, vertical blanking period is scanning line numbers 1 to 19 and 506 to
525 and adjustment point 34 is at scan line number 200.

Therefore, the adjuster now looks at the displayed adjustment pattern and sends a convergence adjustment instruction using the keyboard 11 for the portion to be adjusted for convergence, as described above. Assume that the scanning line number is 200 as shown in FIG.

The CPU 10 receives this instruction via the input port 12 and inputs an address signal generated by the address generator 3 via the input port 17. The address signals generated by the address generator 3 correspond to the scanning line numbers shown in FIG.

Thereafter, the CPU 10 determines the input address signal,
When an address signal corresponding to a scanning line number within a predetermined range is input, the operation of the memory 5 (more precisely, the address switch 4 and the data switch 6 are respectively switched from a to b, and And then from b to a
Is not performed (for example, waiting until memory operation is permitted). When an address signal corresponding to a scanning line number outside the above-mentioned range is input, the operation of the memory 5 is performed at an arbitrary timing.
That is, the CPU 10 prohibits the operation of the memory 5 when an address signal corresponding to a scanning line number within a predetermined range is input by a program, and outputs an address signal corresponding to a scanning line number outside the predetermined range. Allowed if entered.

Here, a period in which the memory operation of the CPU 10 is prohibited and a period in which the memory operation is not prohibited will be described.

FIG. 4 is an explanatory diagram for explaining a period in which the memory operation of the CPU 10 in FIG. 1 is prohibited and a period in which the memory operation is not prohibited.

In the figure, l is the scanning line number corresponding to FIG.
Reference numeral 41 denotes a range of scanning line numbers in which memory operations of the CPU 10 are not prohibited, and reference numeral 42 denotes a range of scanning line numbers in which memory operations of the CPU 10 are prohibited.

 First, a description will be given with reference to FIG.

In FIG. 4A, the range 42 of the scanning line number in which the memory operation of the CPU 10 is prohibited is the range 50 before and after the scanning line number having the adjustment point 34, that is, specifically, the range 42 of the adjustment point 34. Scan line number 150-250 for a certain scan line number 200
It is programmed to be within the range.

Therefore, the CPU 10 does not operate the memory 5 while the address signals corresponding to the scanning line numbers 150 to 250 are being input. Therefore, during this period, the convergence correction data is read from the memory 5 by the address generator 3 and is taken into the D / A converter 7 via the data switch 6a. Normal convergence correction is performed. In addition, since the blanking circuit 15 does not operate during this period, the adjustment pattern signal from the adjustment pattern generator 13 is output from the adjustment pattern output terminal 14 without being erased by the blanking circuit 15. Then, the adjustment pattern is displayed on the screen.

On the other hand, in FIG. 4A, the scan line number range 41 in which the memory operation of the CPU 10 is not prohibited is a range of scan line numbers 1 to 149 and 251 to 525 other than the range 42 described above.

Therefore, the CPU 10 sets the scanning line numbers 1-149,251-525
The operation of the memory 5 is performed at an arbitrary timing while the address signal corresponding to is input. At this time, CPU10
Can rewrite the corresponding convergence correction data for the entire screen including the periphery of the adjustment point 34.

However, while the CPU 10 operates the memory 5, as described above, convergence correction irrelevant to the screen position is performed based on indefinite data irrelevant to the convergence correction data. However, since the blanking circuit 15 operates, the adjustment pattern signal from the adjustment pattern generator 13 is erased by the blanking circuit 15.

FIG. 5 is an explanatory diagram showing a screen state at the time of convergence adjustment by the digital convergence correction device of FIG.

In the figure, 1 is a scanning line number corresponding to FIG. 3, and 82 is a horizontal display line of the adjustment pattern as in FIG. The vertical display lines are omitted. Also,
Numeral 93 is a portion where the display line is deleted as in FIG.

As described above, during the period when the address signals corresponding to the scanning line numbers 150 to 250 are input to the CPU 10, normal convergence correction is performed and the adjustment pattern signal is not erased. As shown in a), the horizontal display lines of the adjustment pattern in the range of the scanning line numbers 150 to 250 are normally displayed without disturbing or erasing the display position. .

That is, at the time of the convergence adjustment, the periphery of the adjustment point 34 that the adjuster will gaze on the screen (that is, the range of the 50th position before and after the scanning line number where the adjustment point 34 is located) always has the disorder of the display position or the like. Since the display line of the adjustment pattern is normally displayed without any erasure or the like, the convergence state can be confirmed accurately, and the convergence adjustment accuracy and the adjustment work efficiency can be improved.

On the other hand, as for the display lines in the horizontal direction of the adjustment pattern in the range of the scanning line numbers 20 to 149 and 251 to 505, the erased portion 93 appears partially as in FIG.

Next, in FIG. 4 (b), the programming is performed so that the range 42 of the scanning line number in which the memory operation of the CPU 10 is prohibited becomes the effective screen range, specifically, the range of the scanning line number 20 to 505. Have been.

Therefore, the CPU 10 does not operate the memory 5 while the address signals corresponding to the scanning line numbers 20 to 505 are being input. For this reason, on the screen, as shown in FIG. 5 (b), the horizontal display lines of the adjustment pattern are normally displayed without disturbing or erasing the display position over the entire screen. Will be displayed.

However, in FIG. 4B, the scan line number range 41 in which the memory operation of the CPU 10 is not prohibited is the scan line numbers 1 to 19,5.
The range is from 06 to 525, which is a period during which an address signal corresponding to this scanning line number is input, that is, a vertical blanking period.
The operation can be performed for a short period of time, so that the processing capacity of the CPU 10 is reduced.

Next, in FIG. 4C, there is no scanning line number range 42 in which the memory operation of the CPU 10 is prohibited.
That is, specifically, programming is performed so that the range of the scan line numbers 1 to 525 is the range 41 in which the memory operation is not prohibited.

Therefore, the CPU 10 can operate the memory 5 at an arbitrary timing during a period in which the address signals corresponding to the scanning line numbers 1 to 525 are input, that is, over the entire period. Therefore, on the screen, FIG. 5 (c)
As shown in (1), the erased portion 93 appears partially on the horizontal display line of the adjustment pattern over the entire screen. However, since the memory operation of the CPU 10 is not prohibited at all, the processing capability of the CPU 10 does not decrease.

Note that the CPU 10 may be controlled by a program based on only one of FIGS. 4 (a), (b) and (c), but FIGS. 4 (a) and 4 (b) , (C)
The optimal screen state and processing capability may always be obtained by sequentially selecting the programs based on the conditions according to the conditions.

As described above, according to the present embodiment, during the convergence adjustment, the CPU 10 can operate the memory 5 at an arbitrary timing other than the period in which the memory operation is prohibited. It is not necessary to request the memory 5 and the peripheral circuits that control the memory 5 to operate at high speed, and the operation speed of the convergence correction operation can be increased. In addition, since complicated timing control is not required, the circuit scale of peripheral circuits for controlling the memory does not increase, so that cost reduction can be realized.

In addition, when performing convergence adjustment, the display line of the adjustment pattern to be displayed does not have a disturbance in the display position, and there is no erased portion within a necessary range. The user can accurately check the convergence state, and can improve the convergence adjustment accuracy and the adjustment work efficiency.

Next, as a second embodiment of the present invention, a case will be described in which the memory operation of the CPU 10 is prohibited by hardware instead of software.

FIG. 6 is a block diagram showing a second embodiment of the present invention.

In the figure, components (1 to 16) that perform the same operations as those in FIG. 1 are given the same numbers as those in FIG. Other, 61
Is an address decoder that determines an address signal output from the address generator 3 and generates a HALT signal for temporarily stopping the operation of the CPU 10.

In this embodiment, the CPU 10 previously sets the address decoder 61 to a range of scanning line numbers for which the memory operation is prohibited as shown in FIG.

The address decoder 61 receives an address signal output from the address generator 3 and determines the address signal.
While the address signal corresponding to the scanning line number in the previously set range is being input, a HALT signal is
To enter.

While the HALT signal is being input from the address decoder 61, the CPU 10 stops its operation. Accordingly, since the CPU 10 does not operate the memory 5 during that time, the display line of the adjustment pattern is displayed on the screen without any disturbance of the display position or the erased portion, as in the first embodiment. Since the images are displayed normally, the convergence state can be confirmed accurately, and the convergence adjustment accuracy and the adjustment work efficiency can be improved.

As described above, according to the present embodiment, the same effects as in the first embodiment can be obtained without imposing a load on the software of the CPU 10. Further, instead of an address signal having a large number of bits (ten and a few bits), a HALT signal having a small number of bits (1 bit) is input to the CPU 10, so that the CPU 10
And the number of connection lines leading to the connection can be reduced.

Next, as a third embodiment of the present invention, a case where the CPU 10 performs a memory operation via an input / output port will be described.

FIG. 7 is a block diagram showing a third embodiment of the present invention.

In the figure, components (1 to 3, 5
1 to 16) are given the same numbers as in FIG. Hereinafter, components of FIG. 7 that are different from FIG. 1 will be described.

In the figure, reference numeral 71 denotes an input / output port for inputting / outputting addresses, data, and control signals for operating the memory 5, of which a control signal is a control output port, an address signal is an address input / output port, and data is data. I / O ports are used. Reference numeral 72 denotes a buffer whose input and output are short-circuited / cut by a control signal output from the input / output port 71.

During the convergence adjustment, during the period when the memory operation of the CPU 10 is prohibited, the CPU 10 short-circuits the buffer 72 by the control signal output from the input / output port 71, and transmits the address signal output from the address generator 3 to the buffer 72. The data is input to the memory 5 and the input / output port 71 via the data switch 6 and the data switch 6 is switched to a. As a result, the convergence correction data is read from the memory 5 by the address generator 3 and is taken into the D / A converter 7 through the data switch 6a, so that the normal convergence correction data corresponding to the screen position is obtained. Is made.

At this time, since the CPU 10 does not output the address signal from the input / output port 71, it does not collide with the address signal output from the address generator 3.

On the other hand, during a period in which the memory operation of the CPU 10 is not prohibited, the CPU 10 transmits the buffer 72 at a given timing by a control signal output from the input / output port 71.
Is disconnected, and the data switch 6 is switched from a to b. Then, the CPU 10 outputs an address signal to the memory 5 through the address input / output port of the input / output port 71, and exchanges data with the memory 5 through the data input / output port. Thereafter, the CPU 10 again short-circuits the buffer 72 and switches the data switch 6 from b to a by the control signal output from the input / output port 71.
Switch to.

Note that whether or not the CPU 10 is in a memory operation inhibition period is determined by the CPU 10 when the buffer 72 is short-circuited.
This is performed based on the address signal of the address generator 3 input through the input unit 1.

Other operations are the same as those of the first embodiment.

As described above, the present embodiment can provide the same effects as those of the first embodiment.

Further, according to this embodiment, the address switch 4 for switching an address signal having a large number of bits (ten and several bits) as shown in FIG. Therefore, the number of input / output terminals can be reduced. Also, since the CPU 10 can operate the memory 5 using only the input / output port 71, a low-cost one-chip CPU having only the input / output port as an external terminal is used.
Can be used as 10. Further, an address output port used by the CPU 10 to output an address signal to the memory 5, an address input port used by the CPU 10 to capture an address signal from the address generator 3,
Can be used as the input / output port 71, so that the number of connection lines connected to the CPU 10 can be reduced as compared with the configuration of FIG.

〔The invention's effect〕

According to the present invention, during the convergence adjustment, the CPU can operate the memory at an arbitrary timing except during the period in which the memory operation is prohibited. Uses a small amount of free time between reading data at one address in the memory and reading data at the next address, during which time the CPU does not need to operate the memory. It is no longer necessary to request the peripheral circuits to be controlled to operate at high speed, so that the operation speed of the convergence correction operation can be increased. Further, since complicated timing control is not required, the circuit scale of peripheral circuits for controlling the memory does not increase, and therefore, cost reduction can be realized.

In addition, during the convergence adjustment, the display line of the adjustment pattern to be displayed does not disturb the display position, and a complete display line can be displayed within a necessary range. Therefore, the adjuster can accurately check the convergence state, and can improve the convergence adjustment accuracy and the adjustment work efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
FIG. 3 is an explanatory diagram showing a screen state at the time of convergence adjustment by the digital convergence correction device of FIG. 1, FIG. 3 is an explanatory diagram showing correspondence between scanning line numbers and screen positions, FIG.
FIG. 5 is an explanatory diagram for explaining a period in which the memory operation of the CPU 10 is prohibited and a period in which the memory operation is not prohibited in FIG. 1. FIG. 5 is an explanatory diagram showing a screen state at the time of convergence adjustment by the digital convergence correction device in FIG. FIG. 6 is a block diagram showing a second embodiment of the present invention, FIG. 7 is a block diagram showing a third embodiment of the present invention, and FIG. 8 is a block diagram showing a configuration of a conventional digital convergence correction device. ,
FIG. 9 is an explanatory diagram showing a screen state at the time of convergence adjustment by the digital convergence correction device of FIG. Description of symbols 3 ... address generator, 5 ... memory, 7 ... D / A converter, 10 ... CPU, 11 ... keyboard, 12,17 ... input port, 13 ... adjustment pattern generator , 15 ... Blanking circuit.

Continued on the front page (72) Inventor Masahiro Kame 2-3, Minamisakae-cho, Kasukabe-shi, Saitama Hitachi Heating Appliances Co., Ltd. Kasukabe Plant (72) Inventor Makoto Shiomi 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. In the laboratory (72) Inventor Michitaka Osawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Home Appliances Research Laboratory, Hitachi, Ltd. (56) References JP-A-62-245791 (JP, A) (58) Fields investigated (Int .Cl. ⁶ , DB name) H04N 9/28

Claims (2)

(57) [Claims] In a television receiver or display using a cathode ray tube of a raster scan system, when a display screen of the cathode ray tube is divided into a plurality of regions, a convergence correction value in each region is stored as convergence correction data. A memory for generating a first address signal in synchronization with a raster scan of the cathode ray tube and inputting the first address signal to the memory to read the convergence correction data stored in the memory; Generating means for generating a second address signal at an arbitrary timing at the time of convergence adjustment, and inputting the second address signal to the memory in place of the first address signal; Instead of the converse stored in the memory Processing means for reading or rewriting the convergence correction data, and digital-analog conversion means for taking in the convergence correction data read from the memory in synchronization with the raster scan of the cathode ray tube, converting the digital signal into an analog signal, and outputting the analog signal. Adjusting pattern generating means for generating and outputting an adjustment pattern signal in synchronization with a raster scan of the cathode ray tube in order to display the adjustment pattern on the display screen of the cathode ray tube at the time of convergence adjustment; At the time of adjustment, when the processing unit reads or rewrites the convergence correction data stored in the memory instead of the address generation unit, the adjustment pattern signal output from the adjustment pattern generation unit Adjustment pattern signal to eliminate A digital convergence correction device comprising: a first address signal generated by the address generating means at the time of convergence adjustment; and an address of the first address signal. A digital convergence correction device wherein reading or rewriting of the convergence correction data stored in the memory is not performed when the value is within a range that matches a convergence adjustment area. 2. In a television receiver or display using a cathode ray tube of a raster scan system, when a display screen of the cathode ray tube is divided into a plurality of regions, convergence correction values in each region are stored as convergence correction data. A memory for generating a first address signal in synchronization with a raster scan of the cathode ray tube and inputting the first address signal to the memory to read the convergence correction data stored in the memory; Generating means for generating a second address signal at an arbitrary timing at the time of convergence adjustment, and inputting the second address signal to the memory in place of the first address signal; Instead of the converse stored in the memory Processing means for reading or rewriting the convergence correction data, and digital-analog conversion means for taking in the convergence correction data read from the memory in synchronization with the raster scan of the cathode ray tube, converting the digital signal into an analog signal, and outputting the analog signal. Adjusting pattern generating means for generating and outputting an adjustment pattern signal in synchronization with a raster scan of the cathode ray tube in order to display the adjustment pattern on the display screen of the cathode ray tube at the time of convergence adjustment; At the time of adjustment, when the processing unit reads or rewrites the convergence correction data stored in the memory instead of the address generation unit, the adjustment pattern signal output from the adjustment pattern generation unit Adjustment pattern signal to eliminate A digital convergence correction device comprising: a first address signal generated by the address generation means at the time of convergence adjustment, wherein an address value of the first address signal is adjusted by the convergence adjustment. A digital convergence correction device, further comprising means for preventing the processing means from reading or rewriting the convergence correction data stored in the memory when the convergence correction data is within a range corresponding to the area.