JP2963671B2 - Chip resistor - Google Patents
Chip resistorInfo
- Publication number
- JP2963671B2 JP2963671B2 JP9059820A JP5982097A JP2963671B2 JP 2963671 B2 JP2963671 B2 JP 2963671B2 JP 9059820 A JP9059820 A JP 9059820A JP 5982097 A JP5982097 A JP 5982097A JP 2963671 B2 JP2963671 B2 JP 2963671B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- bonding layer
- electrodes
- chip
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Non-Adjustable Resistors (AREA)
Description
【0001】[0001]
【発明の属する技術分野】この発明は、チップ抵抗器に
属する。[0001] The present invention relates to a chip resistor.
【0002】[0002]
【従来の技術】一般的に従来のチップ抵抗器は、図6に
示されるようにセラミックやガラス等の絶縁基板101
と、絶縁基板101上にスパッタリング技術や蒸着技術
を用いてNi−Cr薄膜で形成された抵抗体105と、
抵抗体105の両端にCu−Ni薄膜で形成された電極
(図示省略)とを備えている。電極としては、低抵抗金
属の銅が望ましいが、耐候性をもたせる事を主にニッケ
ルとの合金で用いられている。そして、抵抗体105の
表面を樹脂の保護膜106で覆った後、回路基板Sへ半
田109で取り付けるために絶縁基板101の両端面や
底面にもNi−Cr薄膜を介してCu薄膜又はCu−N
i薄膜からなる電極(図示省略)が設けられ、これら電
極全体がNiメッキ膜108で被覆された上、そのNi
メッキ膜に半田がメッキされている。2. Description of the Related Art Generally, a conventional chip resistor includes an insulating substrate 101 made of ceramic, glass or the like as shown in FIG.
And a resistor 105 formed of a Ni—Cr thin film on the insulating substrate 101 by using a sputtering technique or a vapor deposition technique,
An electrode (not shown) formed of a Cu—Ni thin film is provided at both ends of the resistor 105. As an electrode, copper of a low resistance metal is desirable, but an alloy with nickel is mainly used to impart weather resistance. Then, after the surface of the resistor 105 is covered with a resin protective film 106, both ends and the bottom surface of the insulating substrate 101 are also connected to the circuit board S by solder 109 via a Ni-Cr thin film or a Cu thin film or Cu- N
An electrode (not shown) made of an i-thin film is provided.
Solder is plated on the plating film.
【0003】チップ抵抗器において、その信頼性は絶縁
基板に抵抗体が如何に安定に密着しているかに大きく依
存する。この点、上記のように真空着膜されたNi−C
r等の金属薄膜は、セラミックと密着するとともに、汎
用の抵抗値10Ω−1MΩを得るのに十分である。In a chip resistor, its reliability largely depends on how stably the resistor is in close contact with the insulating substrate. In this regard, Ni-C vacuum-deposited as described above
The metal thin film such as r is sufficient to adhere to the ceramic and obtain a general-purpose resistance value of 10Ω-1MΩ.
【0004】[0004]
【発明が解決しようとする課題】チップ抵抗器の用途と
して、例えばコンピューターのハードディスクに流れる
電流を検出するための負荷抵抗がある。その中で検出値
の誤差をより少なくしたり検出可能な電流値をより高く
したりする等のために、1.25mm×2.0mmサイ
ズの基板で、抵抗値0.02Ω−10Ω、定格許容電力
0.1W以上という低抵抗高電力性能が要請されるもの
がある。しかも抵抗の温度係数を小さくすることも要請
されている場合には、抵抗体として使用できる金属が限
られており、抵抗値を下げるために厚みを増すしかな
い。As an application of the chip resistor, for example, there is a load resistor for detecting a current flowing through a hard disk of a computer. In order to reduce the error in the detection value or to increase the detectable current value among them, the resistance value is 0.02Ω-10Ω on a 1.25 mm × 2.0 mm size substrate, There is a demand for a low-resistance high-power performance of 0.1 W or more. In addition, when it is also required to reduce the temperature coefficient of the resistor, the metals that can be used as the resistor are limited, and the only way to reduce the resistance is to increase the thickness.
【0005】しかし、上記従来のチップ抵抗器のように
抵抗体を真空着膜法で設けようとする場合、厚い膜を得
るために、(1)長い着膜時間を必要とする、(2)薄
膜材料となる金属ターゲット等の消耗品の交換寿命が短
くなる、等の理由により、工業的に量産することが困難
である。また、抵抗器はそれ自体が発熱し、そのために
電力の制限を受けるにもかかわらず、上記従来のチップ
抵抗器においては格別の放熱手段が設けられていない。However, when a resistor is to be provided by a vacuum deposition method as in the above-mentioned conventional chip resistor, a long deposition time is required to obtain a thick film, and (2) It is difficult to mass-produce industrially for the reason that the replacement life of a consumable such as a metal target to be a thin film material is shortened. In addition, despite the fact that the resistor itself generates heat and is therefore limited in power, no special heat radiating means is provided in the above-mentioned conventional chip resistor.
【0006】それ故、この発明の第一の目的は、量産に
適した低抵抗のチップ抵抗器を提供することにある。第
二の目的は、従来より格段に高い許容電力を実現するこ
とのできるチップ抵抗器を提供することにある。Therefore, a first object of the present invention is to provide a low-resistance chip resistor suitable for mass production. A second object is to provide a chip resistor capable of realizing a much higher allowable power than before.
【0007】[0007]
【課題を解決するための手段】上記目的を達成するため
に、発明者は「抵抗体は真空着膜されるべき」との固定
観念から脱し、メッキ技術で抵抗体を形成した。すなわ
ち、この発明のチップ抵抗器は、回路基板に搭載されて
接続されるとともに、所定の抵抗値を生ずるチップ抵抗
器において、絶縁基板と、絶縁基板上に薄膜で形成され
た接合層と、接合層の上にメッキされた抵抗体とを備え
ることを特徴とする。Means for Solving the Problems To achieve the above object, the inventor departed from the stereotype that "the resistor should be vacuum-deposited" and formed the resistor by plating. That is, a chip resistor according to the present invention is mounted on a circuit board and connected, and in a chip resistor which generates a predetermined resistance value, a bonding resistor formed of a thin film on the insulating substrate and a bonding layer formed on the insulating substrate. A plated resistor on the layer.
【0008】この発明によれば、絶縁基板と抵抗体の間
に薄膜の接合層が存在するので、抵抗体は絶縁基板に強
固に接着される。そして、抵抗体自体はメッキで形成さ
れるので、抵抗値を下げるために容易に厚みを増すこと
ができ、且つメッキ可能な種々の金属から材質を選択す
ることができる。従って、抵抗の温度係数を小さくした
い場合、抵抗体としてNi−P等のニッケル合金を選択
すると良い。また、薄膜の接合層が存在するので、絶縁
基板としてもアルミナ、窒化アルミニウム、窒化ケイ素
等のセラミックのほか、銅やアルミニウム等の放熱性に
優れた金属の表面に酸化シリコン膜等の絶縁皮膜を有す
るものなど種々適用可能である。According to the present invention, since the thin film bonding layer exists between the insulating substrate and the resistor, the resistor is firmly bonded to the insulating substrate. Since the resistor itself is formed by plating, the thickness can be easily increased to reduce the resistance value, and the material can be selected from various metals that can be plated. Therefore, when it is desired to reduce the temperature coefficient of resistance, it is preferable to select a nickel alloy such as Ni-P as the resistor. In addition, since there is a thin-film bonding layer, an insulating substrate such as a ceramic such as alumina, aluminum nitride, or silicon nitride, or an insulating film such as a silicon oxide film on the surface of a metal having excellent heat dissipation properties such as copper or aluminum is also used as an insulating substrate. Various applications, such as those having, are applicable.
【0009】この発明の抵抗器には、接合層を回路基板
との接続部分にまで延ばし、その接続部分の接合層の表
面に抵抗体に連なる高熱伝導性の皮膜をメッキしたもの
も含まれる。この構成によれば、抵抗体が発した熱が高
熱伝導性の皮膜を伝って回路基板側に速やかに放散す
る。高熱伝導性の皮膜が好ましくは銅Cu又はCu合金
からなる。この場合、Cuは耐半田性に劣るので、これ
をニッケルNi膜で覆うのが望ましい。The resistor of the present invention also includes a resistor in which a bonding layer is extended to a connection portion with a circuit board, and a surface of the bonding layer at the connection portion is plated with a high thermal conductive film connected to a resistor. According to this configuration, the heat generated by the resistor is quickly dissipated to the circuit board through the highly heat conductive film. The high thermal conductive coating preferably comprises copper Cu or a Cu alloy. In this case, since Cu has poor solder resistance, it is desirable to cover this with a nickel Ni film.
【0010】前記接続部分に対応する接合層としては、
1層のものに限らず、2層以上のものもでもよい。特に
絶縁基板に強固に接着するニクロムNi−Cr合金を第
一層とし、その上にNi−Crと強固に接着し且つ抵抗
体とも強固に接着する銅Cuもしくは銅ニッケルCu−
Ni合金を第二層として設けると良い。[0010] As a bonding layer corresponding to the connection portion,
Not only one layer but also two or more layers may be used. In particular, the first layer is made of a Nichrome Ni-Cr alloy which is firmly bonded to the insulating substrate, and the copper Cu or copper nickel Cu which is firmly bonded to Ni-Cr and firmly bonded to the resistor is further formed thereon.
It is preferable to provide a Ni alloy as the second layer.
【0011】更にこの発明の抵抗器は、抵抗体の両端に
一対の電極が設けられ、この一対の電極の中間にそれら
と孤立した島電極が抵抗体に接するように設けられてい
ることをも特徴とする。この構成によれば、抵抗体の両
端の電極間を流れる電流が、途中で島電極を通過する。
そして、島電極は抵抗体よりも低抵抗の導体であるか
ら、その部分での発熱量は抵抗体での発熱量に比べて無
視できる程に少ない。このため、発熱部分が実質的に島
電極で分割され、各部分で発生した熱が近くの電極を介
して速やかに放散する。なお、これら電極は、それ自体
の抵抗を低くするためと、熱放散をより速やかにするた
めに、抵抗体をメッキする前に接合層の上にメッキによ
って設けるのが好ましい。Further, the resistor according to the present invention is provided at both ends of the resistor.
A pair of electrodes is provided, and the
And an isolated island electrode are provided so as to be in contact with the resistor.
It is also characterized by According to this configuration, the current flowing between the electrodes at both ends of the resistor passes through the island electrode halfway.
Since the island electrode is a conductor having a lower resistance than the resistor, the amount of heat generated at that portion is negligibly smaller than the amount of heat generated by the resistor. Therefore, the heat-generating portion is substantially divided by the island electrodes, and the heat generated in each portion is quickly dissipated through the nearby electrodes. These electrodes are preferably provided on the bonding layer by plating before the resistor is plated, in order to reduce the resistance of the electrodes themselves and to dissipate heat more quickly.
【0012】[0012]
【発明の実施の形態】この発明の実施形態を図面ととも
に説明する。図1は実施形態のチップ抵抗器(以下、単
に「抵抗器」という。)の要部を示す断面図、図2は同
じく平面図である。Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a main part of a chip resistor (hereinafter, simply referred to as a “resistor”) according to the embodiment, and FIG. 2 is a plan view of the same.
【0013】抵抗器10は、アルミナセラミックからな
る絶縁基板1と、絶縁基板1の表面に設けられたNi−
Crの第一接合層21と、その上に形成されたCu−N
iの第二接合層22と、その上の両端と中央に4〜30
μmの厚さにCuメッキされた電極41,42,43
と、第二接合層22及び電極41,42,43を覆うよ
うに3〜20μmの厚さにNi−Pメッキされた抵抗体
5とを備える。電極及び抵抗体の厚さは目的抵抗値に応
じて適宜設定される。各接合層は、スパッタリング、蒸
着、イオンプレーティング等の薄膜技術で形成される。
ただし、第一接合層はCrのみでもよい。また、第二接
合層はCu又はNiのみでもよい。両端の電極41,4
3は外部回路と導通接続しているが、中央の島電極42
は抵抗体5を介して接続している以外は電気的に孤立し
ている。The resistor 10 includes an insulating substrate 1 made of alumina ceramic, and a Ni-type substrate provided on the surface of the insulating substrate 1.
Cr first bonding layer 21 and Cu-N formed thereon
i of the second bonding layer 22 and 4 to 30
Electrodes 41, 42, 43 plated with Cu to a thickness of μm
And a resistor 5 Ni-P plated to a thickness of 3 to 20 μm so as to cover the second bonding layer 22 and the electrodes 41, 42, 43. The thicknesses of the electrode and the resistor are appropriately set according to the target resistance value. Each bonding layer is formed by a thin film technique such as sputtering, vapor deposition, or ion plating.
However, the first bonding layer may be made of only Cr. Further, the second bonding layer may be made of only Cu or Ni. Electrodes 41, 4 at both ends
3 is conductively connected to an external circuit, but has a central island electrode 42
Are electrically isolated except that they are connected via the resistor 5.
【0014】抵抗器10は、抵抗体5がメッキによって
十分厚く形成されたNi−Pからなるので、低抵抗であ
り且つ抵抗温度係数が小さい。また、電極41,43間
に電圧を印加すると、電流は矢印のように途中で島電極
42を通過する。そして、島電極42はCuからなる導
体であるから、その部分での発熱量は抵抗体5での発熱
量に比べて無視できる程に少ない。このため、島電極4
2部分に発熱部分がない構造となり発熱部分が実質的に
島電極で分割され、各部分で発生した熱が近くの電極を
介して速やかに放散する。各電極で挟まれた抵抗体部分
51のみが実質的に抵抗体として作用する。The resistor 10 has a low resistance and a small temperature coefficient of resistance because the resistor 5 is made of Ni-P formed sufficiently thick by plating. When a voltage is applied between the electrodes 41 and 43, the current passes through the island electrode 42 halfway as indicated by the arrow. Since the island electrode 42 is a conductor made of Cu, the amount of heat generated at that portion is negligibly smaller than the amount of heat generated by the resistor 5. Therefore, the island electrode 4
There is no heat generating portion in the two portions, and the heat generating portion is substantially divided by the island electrodes, and the heat generated in each portion is quickly dissipated through the nearby electrodes. Only the resistor portion 51 sandwiched between the electrodes substantially functions as a resistor.
【0015】抵抗器10は、一般にレーザートリミング
法で抵抗体を溶解させることにより抵抗値調整がなされ
る。本例では特に抵抗体5の中央部分52のみと接合層
21,22の対応部分とを同時に溶解除去することによ
り、図3に示すように抵抗調整時に抵抗体を分割する。
これにより島電極42による分割と併せて抵抗体が合計
4分割されることとなり、発熱部分の分散化が図られ
る。抵抗調整後、機械的損傷を防止するために、図4に
示すように抵抗体5の表面にエポキシ樹脂6が塗布さ
れ、硬化される。ただし、回路基板との導通接続のため
に両端の電極41,43に対応する表面は露出させてお
く。抵抗器10は、一般に一貫して単独で製造されるこ
とはなく、この段階までは大型の絶縁基板上に多数個分
同時に薄膜形成されメッキされた後、この段階でレーザ
ースクライブ法にて大型基板に溝を入れ、その溝に沿っ
て各個別に割られる。The resistance of the resistor 10 is generally adjusted by dissolving the resistor by a laser trimming method. In this example, particularly, only the central portion 52 of the resistor 5 and the corresponding portions of the bonding layers 21 and 22 are simultaneously dissolved and removed, so that the resistor is divided at the time of resistance adjustment as shown in FIG.
As a result, the resistor is divided into four parts in addition to the division by the island electrodes 42, and the heat generation part is dispersed. After the resistance adjustment, an epoxy resin 6 is applied to the surface of the resistor 5 and cured to prevent mechanical damage, as shown in FIG. However, the surfaces corresponding to the electrodes 41 and 43 at both ends are exposed for conductive connection with the circuit board. In general, the resistor 10 is not manufactured by itself alone. Up to this stage, a large number of thin films are simultaneously formed and plated on a large-sized insulating substrate. And are individually split along the groove.
【0016】次に抵抗器10は、図5に示すように回路
基板Sに表面実装するために、Ni−Cr薄膜の第一接
合層31が絶縁基板1の側面に設けられ、その上にCu
薄膜の第二接合層32が設けられる。そして、第二接合
層の上及び露出した抵抗体5の上に18〜30μmの厚
さのCu皮膜7、3〜7μmの厚さのNi皮膜8及び3
μm以上の厚さの半田皮膜91が順にバレルメッキされ
る。これで抵抗器10が完成する。Next, as shown in FIG. 5, the resistor 10 has a first bonding layer 31 of a Ni—Cr thin film provided on a side surface of the insulating substrate 1 for surface mounting on a circuit board S, and a Cu
A thin film second bonding layer 32 is provided. Then, a Cu film 7 having a thickness of 18 to 30 μm and Ni films 8 and 3 having a thickness of 3 to 7 μm are formed on the second bonding layer and the exposed resistor 5.
The solder coating 91 having a thickness of not less than μm is sequentially barrel-plated. Thus, the resistor 10 is completed.
【0017】抵抗器10を回路基板Sに半田92で接続
して使用される。Ni皮膜8は、抵抗器10を回路基板
Sに半田付けするときに、半田92がCu皮膜7と反応
するのを防止するバリア層となる。使用中に抵抗体が発
した熱は、高熱伝導性のCu電極41,43及びCu皮
膜7を伝って速やかに回路基板S側に放散する。従っ
て、上記のように発熱部分が分散されることと相まって
抵抗体の劣化が防止される。従来、1.25mm×2.
0mmの基板サイズの抵抗器は、定格許容電力が0.1
Wまでであったが、本例の構成によれば同じ基板サイズ
で0.25Wまで十分許容できる。The resistor 10 is used by connecting it to the circuit board S with solder 92. The Ni film 8 serves as a barrier layer that prevents the solder 92 from reacting with the Cu film 7 when the resistor 10 is soldered to the circuit board S. The heat generated by the resistor during use is quickly dissipated to the circuit board S through the high thermal conductivity Cu electrodes 41 and 43 and the Cu film 7. Therefore, the deterioration of the resistor is prevented in combination with the dispersion of the heat generating portion as described above. Conventionally, 1.25 mm × 2.
A resistor with a board size of 0 mm has a rated allowable power of 0.1
Although it was up to W, according to the configuration of this example, it is sufficiently allowable up to 0.25 W with the same substrate size.
【0018】[0018]
【実施例】図1〜5に示した構造の抵抗器であって、絶
縁基板1における厚さ0.4mm、電流方向の長さ2.
0mm、それと異なる方向の長さ1.25mmのものを
10個準備した。抵抗体5の厚さは10μm、電極4
1,42,43の厚さは20μm、Cu皮膜7の厚さは
10μmとした。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A resistor having the structure shown in FIGS. 1 to 5, having a thickness of 0.4 mm on an insulating substrate 1 and a length in a current direction.
Ten pieces having a length of 0 mm and a length of 1.25 mm in a different direction were prepared. The thickness of the resistor 5 is 10 μm,
The thickness of 1, 42, 43 was 20 μm, and the thickness of the Cu film 7 was 10 μm.
【0019】これら10個の抵抗器を温度70℃の恒温
層に入れ、0.158voltの定格直流電圧を印加
し、90分通電し30分切断するサイクルを繰り返し、
抵抗値の変化率を測定した。測定結果を平均して経時的
に表したグラフを図7に示す。グラフから明らかなよう
に、この例の抵抗器はほとんど抵抗体が劣化していなか
った。A cycle of putting these ten resistors in a constant temperature layer at a temperature of 70 ° C., applying a rated DC voltage of 0.158 volts, energizing for 90 minutes, and disconnecting for 30 minutes was repeated.
The rate of change of the resistance value was measured. FIG. 7 is a graph showing the average of the measurement results over time. As is clear from the graph, the resistor of this example had almost no deterioration of the resistor.
【0020】[0020]
【発明の効果】この発明のチップ抵抗器は、以上のよう
に低抵抗で、放熱性に優れているから、同じサイズの従
来抵抗器の定格許容電力を大きく上回る電力を使用して
も抵抗が劣化することがない。従って、例えば、ハード
ディスクの大電流検出用に好適である。As described above, the chip resistor of the present invention has a low resistance and is excellent in heat dissipation as described above, so that even if power exceeding the rated allowable power of the conventional resistor of the same size is used, the resistance can be reduced. There is no deterioration. Therefore, for example, it is suitable for detecting a large current of a hard disk.
【図1】 実施形態のチップ抵抗器の中間体を示す要部
断面図である。FIG. 1 is a sectional view of a main part showing an intermediate body of a chip resistor according to an embodiment.
【図2】 実施形態のチップ抵抗器の中間体を示す平面
図である。FIG. 2 is a plan view showing an intermediate body of the chip resistor according to the embodiment.
【図3】 実施形態のチップ抵抗器の抵抗値調整方法を
説明する平面図である。FIG. 3 is a plan view illustrating a method of adjusting the resistance value of the chip resistor according to the embodiment.
【図4】 実施形態のチップ抵抗器を示す平面図であ
る。FIG. 4 is a plan view showing the chip resistor of the embodiment.
【図5】 実施形態のチップ抵抗器が回路基板に搭載さ
れている状態を示す断面図である。FIG. 5 is a cross-sectional view showing a state where the chip resistor of the embodiment is mounted on a circuit board.
【図6】 従来のチップ抵抗器を示す断面図である。FIG. 6 is a sectional view showing a conventional chip resistor.
【図7】 チップ抵抗器の抵抗変化率の測定結果を示し
たグラフである。FIG. 7 is a graph showing a measurement result of a resistance change rate of the chip resistor.
1,101 絶縁基板 21,22,31,32 接合層 41,42,43 電極 5,105 抵抗体 6,106 保護膜 7 高熱伝導性の皮膜 8,108 Ni皮膜 91,92,109 半田 S 回路基板 DESCRIPTION OF SYMBOLS 1,101 Insulating substrate 21,22,31,32 Bonding layer 41,42,43 Electrode 5,105 Resistor 6,106 Protective film 7 High thermal conductive film 8,108 Ni film 91,92,109 Solder S Circuit board
フロントページの続き (56)参考文献 特開 平8−138902(JP,A) 特開 平8−22903(JP,A) 特開 平3−80501(JP,A) (58)調査した分野(Int.Cl.6,DB名) H01C 7/00 Continuation of the front page (56) References JP-A-8-138902 (JP, A) JP-A-8-22903 (JP, A) JP-A-3-80501 (JP, A) (58) Fields investigated (Int) .Cl. 6 , DB name) H01C 7/00
Claims (6)
に、所定の抵抗値を生ずるチップ抵抗器において、 絶縁基板と、絶縁基板上に薄膜で形成された接合層と、
接合層の上にメッキされた抵抗体とを備えるとともに、 その抵抗体の両端に一対の電極が設けられ、この一対の
電極の中間にそれらと孤立した島電極が抵抗体に接する
ように抵抗体よりも低抵抗導体によって設けられている
ことを特徴とするチップ抵抗器。A chip resistor mounted and connected to a circuit board and producing a predetermined resistance value, comprising: an insulating substrate; a bonding layer formed on the insulating substrate in a thin film;
Together and a plated resistor on the bonding layer, a pair of electrodes are provided on both ends of the resistor, the pair
In the middle of the electrodes, the isolated island electrode contacts the resistor
Characterized in that the chip resistor is provided by a conductor having a lower resistance than the resistor.
ケル合金からなる請求項1に記載のチップ抵抗器。2. The chip resistor according to claim 1, wherein the resistor is made of a nickel alloy such as nickel phosphorus Ni-P.
び、その接続部分の接合層の表面に抵抗体に連なる高熱
伝導性の皮膜がメッキされている請求項1又は2に記載
のチップ抵抗器。3. The chip according to claim 1, wherein the bonding layer extends to a connection portion with the circuit board, and the surface of the bonding layer at the connection portion is plated with a high thermal conductive film connected to a resistor. Resistor.
ケルクロムNi−Cr合金からなり絶縁基板に密着した
第一層とその上の銅Cuもしくは銅ニッケルCu−Ni
等の銅合金からなる第二層とで構成される請求項1〜3
のいずれかに記載のチップ抵抗器。4. A bonding layer corresponding to the connection portion is made of a nickel chromium Ni—Cr alloy, and a first layer closely adhered to an insulating substrate and copper Cu or copper nickel Cu—Ni thereon.
And a second layer made of a copper alloy.
The chip resistor according to any one of the above.
メッキする前にメッキによって設けられている請求項1
に記載のチップ抵抗器。 Wherein said pair of electrodes and the island electrodes, according to claim 1 is provided by plating before plating the resistor
A chip resistor according to claim 1.
からなりニッケルNi膜で覆われている請求項3に記載
のチップ抵抗器。6. The chip resistor according to claim 3, wherein the high thermal conductive film is made of copper Cu or a Cu alloy and is covered with a nickel Ni film.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9059820A JP2963671B2 (en) | 1997-02-26 | 1997-02-26 | Chip resistor |
TW86118156A TW391016B (en) | 1997-02-26 | 1997-12-03 | Chip resistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9059820A JP2963671B2 (en) | 1997-02-26 | 1997-02-26 | Chip resistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10241903A JPH10241903A (en) | 1998-09-11 |
JP2963671B2 true JP2963671B2 (en) | 1999-10-18 |
Family
ID=13124253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9059820A Expired - Lifetime JP2963671B2 (en) | 1997-02-26 | 1997-02-26 | Chip resistor |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2963671B2 (en) |
TW (1) | TW391016B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020010004A (en) * | 2018-07-12 | 2020-01-16 | Koa株式会社 | Resistor and circuit substrate |
JP7089555B2 (en) * | 2020-07-03 | 2022-06-22 | 大同特殊鋼株式会社 | Manufacturing method of current detection resistor, circuit board and current detection resistor |
-
1997
- 1997-02-26 JP JP9059820A patent/JP2963671B2/en not_active Expired - Lifetime
- 1997-12-03 TW TW86118156A patent/TW391016B/en active
Also Published As
Publication number | Publication date |
---|---|
TW391016B (en) | 2000-05-21 |
JPH10241903A (en) | 1998-09-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10354826B2 (en) | Fuse in chip design | |
JP2002057009A (en) | Resistor and method of manufacturing the same | |
US9502161B2 (en) | Power resistor with integrated heat spreader | |
WO2009145133A1 (en) | Resistor | |
US10643769B2 (en) | Resistor element and resistor element assembly | |
US10181367B2 (en) | Resistor element, method of manufacturing the same, and resistor element assembly | |
JPH0760761B2 (en) | Film type power resistor assembly | |
KR20050071330A (en) | Over-current protective device and manufacturing method thereof | |
JP2963671B2 (en) | Chip resistor | |
US9870849B2 (en) | Chip resistor and mounting structure thereof | |
JP2002184601A (en) | Resistor unit | |
JP2003045703A (en) | Chip resistor and manufacturing method therefor | |
JP3215648B2 (en) | Manufacturing method of chip resistor | |
JP2002050501A (en) | Mounting body and using method thereof | |
JP2002057010A (en) | Resistor and method of manufacturing the same | |
WO2023074131A1 (en) | Chip resistor | |
WO2023053594A1 (en) | Chip resistor | |
RU189715U1 (en) | Power Thin Film Resistor | |
US20220270790A1 (en) | Chip resistor component | |
CN110637346B (en) | Chip resistor | |
JP2002208501A (en) | Resistor unit, electronic part using the same, and use of the same | |
JP2000331590A (en) | Circuit protection element and its manufacture | |
JP2022023781A (en) | High power resistor and manufacturing method thereof | |
JPH08181001A (en) | Chip resistor for surface mounting and its surface-mounting method | |
TW200933658A (en) | Chip resistor with thermal layer structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080806 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080806 Year of fee payment: 9 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090806 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090806 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100806 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100806 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110806 Year of fee payment: 12 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120806 Year of fee payment: 13 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120806 Year of fee payment: 13 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130806 Year of fee payment: 14 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |