JP2947650B2 - Failure analysis method for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device failure analysis method.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been miniaturized and highly integrated, and the device structure has become complicated. Such technical trends of miniaturization and high integration inevitably require failure analysis of semiconductor devices. Making it difficult. However, on the other hand, detailed observation of the failure location and composition analysis are indispensable for investigating the cause of the failure.

[0003] Conventional failure analysis of a semiconductor device includes a process of identifying a failure location of the semiconductor device, a process of observing an outer surface of the identified failure location, and a process of removing a multilayer film of the semiconductor device to remove foreign matter at the failure location. It has been performed through a process of exposing and observing and analyzing the surface.

[0004]

However, in the conventional failure analysis method, the surface of the semiconductor device is charged by an electron beam or an ion beam as an observation means such as a scanning electron microscope or a focused ion beam device. Therefore, there is a possibility that a local failure point may be overlooked. In addition, since the semiconductor device is relocated for each process, it is necessary to locate the fault location of the semiconductor device on the coordinates of each process each time the process is performed, and the local fault of the miniaturized and highly integrated semiconductor device is required. There was a problem that a great deal of time and labor was required for observation and analysis of the location.

An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a failure analysis method capable of easily locating a failure point of a semiconductor device on coordinates of an observation means and an analysis means.

[0006]

In order to solve the above-mentioned problems, a failure analysis method of the present invention is to observe a failure location of a semiconductor device with an optical microscope having a laser light source, and to provide a failure location on a coordinate of the optical microscope. The coordinate position of the semiconductor device is stored in the analyzer, and then a laser beam is applied to a position at an appropriate distance from the failure location of the semiconductor device to form a hole reaching the semiconductor substrate as an alignment, and the alignment on the coordinates of the optical microscope is adjusted. The coordinate position is stored in the analysis device, and the relative coordinate position of the failure point with respect to the alignment is transferred from the analysis device to an observation device or an analysis device in a later process. This is a configuration based on the position.

[0007]

According to the above configuration, the coordinate position of the fault location is expressed by the relative coordinates based on the alignment marked on the semiconductor device, so that the coordinate position of the fault location is again displayed on a different coordinate of the observation device and the analysis device in the later process. Therefore, it is not necessary to search for, and it is possible to easily identify the failure point.

[0008]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a failure analysis device for a semiconductor device according to the present invention. In FIG. 1, an optical microscope 1 is provided with a laser light source 2, an infrared light objective lens 3 and a CCD camera 4, and a laser oscillation power supply 5 and a laser guide light source 6 are connected to the CCD camera 4. Is connected to a monitor color TV7.

An XY-axis scanning drive 9 for mounting the semiconductor device 8 is disposed at a position facing the objective lens 3 for infrared light.
A Y-axis scanning drive controller 10 is connected. Further, RC23 is provided in the XY-axis scanning drive controller 10.
A personal computer 12 is connected via a signal transmission cable 11 composed of a 2C cable, and the personal computer 12 is connected via another signal transmission cable 13 to an XY-axis scanning drive controller 15 of a scanning electron microscope 14. It is connected to the.

The operation of the above configuration will be described below.
A method for performing a failure analysis of the semiconductor device of the first embodiment will be described in detail. First, a defective address is specified as a failed portion 16 of a semiconductor device 8, for example, a dynamic memory (DRAM) by electrical measurement.

Then, the semiconductor device 8 is controlled by the optical microscope 1.
After observing the defective address of the XY-axis scanning drive device 9
To move the semiconductor device 8 from the center of the failure location 16 to an arbitrary location, for example, 100 μm to the left. Next, a laser light source 2, for example, an oscillation wavelength of 1.06 μm,
Nd: YAG (yttrium, aluminum, garnet) pulse laser light with an output of 6 nJ / pulse, a pulse width of 8 nsec, and a peak power of 0.75 MW is φ200 μm in diameter.
Semiconductor device 8 through a circular fixed stop, an attenuation filter with a transmittance of 2.5%, and an infrared objective lens with a magnification of 100 times.
To form a processed hole 17 as shown in FIG.
This processing hole 17 is defined as an alignment 17a.

In this case, the diameter of the processing hole 17 is about 4 μm, and the processing hole 17 reaches the semiconductor substrate. Processing hole diameter φd
And the magnification n of the objective lens are expressed by the following equation. φd = φD / n φD is a circular fixed stop diameter.

Similarly, a processing hole 18 is formed in the semiconductor device 8 by Nd: YAG pulsed laser light at a position of 100 μm on the right side of the center of the failure portion 16 to form an alignment 18a.

Then, the semiconductor device 8 is controlled by the optical microscope 1.
The failure location 16 and the alignments 17a and 18a are observed, and the relative position coordinates of the failure location 16 from the alignments 17a and 18a are stored. Next, the relative position coordinates are transferred to the personal computer 12 through the signal transmission cable 11 and the X of the scanning electron microscope 14 is transmitted from the personal computer 12 through the signal transmission cable 13.
The data is transferred to the Y-axis scanning drive controller 15.

A scanning electron microscope (SEM) 14
Thus, the relative position coordinates of the failure location 16 are called, and a secondary electron image of the failure location 16 is observed. Electronic beam is 2
It is accelerated at 0 KV and the beam diameter is 0.01 μm. At this time, the failure location 16 can be instantaneously identified by expressing the coordinate position of the failure location 16 as relative coordinates from the coordinate positions of the arbitrary alignments 17a and 18a. Needless to say, the shorter the distance between the positions of the arbitrary alignments 17a and 18a and the failure location 16, the higher the positional accuracy.

Then, the multilayer film forming the semiconductor device 8 is removed by dry etching with freon gas or the like or wet etching with hydrofluoric acid or the like, thereby exposing the surface of the foreign matter at the failed portion 16. (SEM) 14 to observe a secondary electron image. As described above, the detailed observation of the failure portion 16 can be easily performed.

In this embodiment, the semiconductor device 8 having a pattern is described. However, the same effect can be obtained for failure analysis of a semiconductor substrate having no pattern or a semiconductor substrate formed of a laminated film. In this embodiment, the laser
Although a Nd: YAG pulse laser beam was used as a beam, the same effect can be obtained with a high output laser such as a CO ₂ laser or a ruby laser.

Next, a second embodiment of the present invention will be described.
In this embodiment, a focused ion beam (FIB) device is used instead of a scanning electron microscope (SEM). First, in the same manner as in the first embodiment, marking is performed on an arbitrary portion of the semiconductor device 8 with an Nd: YAG pulse laser beam to form alignments 17a and 18a, and alignment with the failed portion 16 of the semiconductor device 8 is performed. The relative position coordinates of 17a and 18b are stored and transferred to the personal computer 12.

Next, based on the relative position coordinates of the fault location 16 transferred from the personal computer 12, an ion-excited secondary electron image (SIM image) of the fault location 16 is observed by a focused ion beam (FIB) device. . For example, the semiconductor device 8 is scanned with positive Ga ions having an acceleration voltage of 30 KV, an ion beam current of 103 pA, and a beam diameter of 0.1 μm. When the surface of the semiconductor device 8 is an insulating film such as silicon nitride or silicon dioxide, Ga ions positively charge the insulating film, so that the amount of secondary electrons generated by ion excitation is reduced and a SIM image is hardly observed. . Further, since the atomic radius of Ga ions is several orders of magnitude larger than the electron radius, ions cannot pass through the material surface, and the ion-excited secondary electron image reflects the material surface. Therefore, it is more difficult and more time-consuming to observe and identify an abnormality and an insulator due to a base than a scanning electron microscope (SEM).

Further, the failure spot 1 is generated by the focused ion beam.
6 is subjected to cross-section processing by sputter etching, and the cause of the failure can be clarified by observing the structure of the failed portion 16 with a SIM image. In the present embodiment, the semiconductor device 8 having a pattern is described. However, the same effect can be obtained for failure analysis of a semiconductor substrate having no pattern or a semiconductor substrate formed of a laminated film.

Next, a third embodiment of the present invention will be described.
It is important to perform local analysis and surface analysis of the failure location 16 as a failure analysis method of the semiconductor device in order to clarify the cause of the failure. For example, a secondary ion mass spectrometer (SIMS) will be described as an example of the surface analyzer.

Conventionally, the analysis region has been positioned by an optical microscope attached to the main body of a secondary ion mass spectrometer (SIMS). It is becoming difficult to identify a typical failure location. First, in the same manner as in the first embodiment, Nd: YAG
The laser beam is used to mark a processing hole diameter of 20 μm that can be identified by an optical microscope attached to the SIMS main body, thereby forming alignment positions 17a and 18a.

Next, the fault 16 and the alignments 17a and 18a of the semiconductor device 8 are observed with the optical microscope 2,
The relative position coordinates are stored and held. Further, the relative position coordinates are transmitted to the personal computer through the signal transmission cable 11.
To the data 12.

Then, a secondary ion mass spectrometer (SIM)
The semiconductor device 8 is installed in S), and the relative position coordinates of the fault location 16 are called to position the analysis area. This increases the positional accuracy of the analysis area, increases the reliability of the analysis data, and helps to clarify the cause of the failure. As the analysis conditions,
Primary ion Cs, primary ion energy -14.5 Ke
V, primary ion current 20 nA, primary ion beam diameter 20
μm, raster area 100 μm □, analysis area 60 μmφ
And

In this embodiment, a secondary ion mass spectrometer (SIMS), an Auger electron spectrometer (AES), and an energy dispersive X-ray spectrometer (ED) are used as surface analyzers.
X) A similar effect is obtained for a wavelength dispersive X-ray spectrometer (WDX).

[0026]

As described above, according to the present invention, a failure location can be easily identified based on the relative position coordinates from the alignment, and detailed observation and composition analysis of the failure location are possible. In addition, it is possible to feed back to the semiconductor device manufacturing process or the semiconductor device development process, and it is expected that the yield of the semiconductor device will be stable or the effect of early development will be achieved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an analyzer of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a semiconductor device according to the same embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Optical microscope 2 Laser light source 3 Objective lens for infrared light 8 Semiconductor device 9 XY-axis scanning drive device 10 XY-axis scanning drive controller 11 Signal transmission cable 12 Personal computer 14 Scanning type Electron microscope 16 Failure point 17a, 18a Alignment 2

Claims (1)

(57) [Claims] 1. A failure point of a semiconductor device is observed by an optical microscope having a laser light source, and a coordinate position of the failure point on the coordinates of the optical microscope is stored in an analysis device. By irradiating the laser beam to the aligned position, the hole reaching the semiconductor substrate is formed as alignment, the coordinate position of the alignment on the coordinates of the optical microscope is stored in the analyzer, and the relative coordinate position of the failure point with respect to the alignment is analyzed. A failure analysis method for a semiconductor device, wherein the failure is transferred to an observation device or an analysis device in a later process, and a fault location of the semiconductor device is positioned in the observation device or the analysis device based on the relative coordinate position.