JP2912745B2 - Failure analysis method for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure analysis method for simply analyzing a failure location of a semiconductor device.

[0002]

2. Description of the Related Art As shown in FIG. 5, in a conventional method for analyzing a failure location of a semiconductor device, a failure location of the semiconductor device is specified by electrical measurement in step 1, and a failure location is analyzed by a charged beam device in step 2. Was something.

[0003]

However, in the above-described conventional failure analysis method, a local failure location is specified because the surface of the semiconductor device is charged when the failure location in step 2 is analyzed by the charged beam device. However, there was a problem that it took a lot of time and effort, or was overlooked.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a simple and highly accurate failure analysis method.

[0005]

SUMMARY OF THE INVENTION A failure analysis method according to the present invention.
Is used for electrical measurement of failure points in dynamic memory devices.
More specific, and for the identified fault location, up and down, left and right
Marking at 4 locations to charge failure beam
When analyzing with the instrument, the intersection of the four markings
The analysis is performed by specifying the failure location.

[0006]

According to this method, the dynamic memory device
Identify the fault location using an address, etc.
To make markings in four places, up, down, left and right
Therefore, when analyzing the failure location, the four markings
If you find the intersection, you can easily and quickly identify the fault location and analyze it.
I will be able to.

[0007]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a flow chart of a failure analysis method according to the present embodiment. The difference from the conventional example shown in FIG. 5 is that a hole which reaches the semiconductor substrate by irradiating a semiconductor device with an energy beam is provided to mark a failure portion. That is, the process of step 2 is provided.

Here, step 1 is a process of specifying a fault location by electrical measurement, and step 3 is a process of analyzing the fault location by a charged beam device.

According to this method, the contrast of the secondary electron image of the hole reaching the semiconductor substrate is observed to be darker than the surface of the semiconductor device, so that the failure portion can be easily identified.

This embodiment will be described in more detail with reference to FIGS. FIG. 2 is a configuration diagram of a marking device used in the present embodiment, FIG. 3 is a detailed flowchart of an analysis method in the present embodiment, and FIG. 4 is a top view of the semiconductor device.

In FIG. 2, 1 is a laser light source, 2 is an optical microscope, 3 is an objective lens for infrared light, 4 is a CCD camera, 5 is a color TV receiver for monitoring, 6 is a power supply for laser oscillation, and 7 is XY. An axis scan drive controller, 8 is a semiconductor device, 9 is an XY axis scan drive, and 10 is a laser guide light source.

In this embodiment, first, as shown in FIG. 3, a faulty portion of a semiconductor device 8 [for example, a dynamic memory (DRAM)] is specified by electrical measurement. Next, the failure location is marked by the marking device shown in FIG.
According to the method, a failure point specified by electrical measurement is observed with the optical microscope 2. For example, when a step is generated in the pattern due to a foreign substance or the like, a failure portion 11 can be identified at a low magnification in an optical microscope image as shown in FIG. 4 by a difference in the wavelength of the reflected wave or a difference in the depth of focus. Next, the semiconductor device 8 is moved by 20 μm to the left from the center of the fault location by the XY-axis scanning drive device 9. Then, from the laser light source 1, an oscillation wavelength of 1.06 μm and a laser output of 6 nJ / pulse
e, Nd with a pulse width of 8 nsec and a peak power of 0.75 MW:
A YAG (yttrium, aluminum, garnet) pulse laser beam is irradiated on the semiconductor device 8 through a circular fixed stop having a diameter of 200 μm, an attenuation filter having a transmittance of 2.5%, and an infrared objective lens having a magnification of 100 to form a processing hole. The marking 12 is formed. In this case, the processing hole diameter is about 4 μm, and the processing hole reaches the semiconductor substrate. The processing hole diameter φ _d and the magnification n of the objective lens are represented by φ _d = φ _D / n. Here, φ _D is a circular fixed stop diameter. Similarly, the right side, the upper side, and the lower side from the center of the fault location 11
A marking 12 is formed on the semiconductor device 8 at a position of μm using an Nd: YAG pulse laser beam (FIG. 4). Next, a secondary electron image of the failed portion 11 is observed with a scanning electron microscope (SEM). The electron beam is accelerated at 20 KV and the beam diameter is 0.01 μm. Since the hole processed by the pulsed laser beam reaches the semiconductor substrate, the contrast of the secondary electron image is observed to be darker than the surface of the semiconductor device, and the failure portion 11 can be easily identified. This is because, in the case of electron-excited secondary electrons, an easily charged substance such as an insulator generates more secondary electrons than a substance connected to the semiconductor substrate. Next, the multilayer film constituting the semiconductor device 8 is removed by dry etching with freon gas or the like or wet etching with hydrofluoric acid or the like, the foreign matter at the failed portion is exposed, and the secondary electron image is observed by SEM. Detailed observation of the portion 11 can be easily performed.

In this embodiment, a semiconductor device having a pattern is described. However, the same effect can be obtained by the same method for failure analysis of a semiconductor device having no pattern or a semiconductor device formed of a laminated film. In this embodiment, a pulsed Nd: YAG laser beam is used as the energy beam, but the same effect can be obtained by using a focused ion beam or an electron beam. Further, instead of the SEM observation, a focused ion beam (FIB) device can be used to observe the ion-excited secondary electron image (SIM image) of the failure location 11 and analyze the failure location. For example, when positive Ga ions having an acceleration voltage of 30 KV, an ion beam current of 103 pA, and a beam diameter of 0.1 μm are scanned over the semiconductor device 8, when the surface of the semiconductor device 8 is an insulating film such as silicon nitride or silicon dioxide, Ga
The ions positively charge the insulating film, reduce the amount of secondary electrons generated by the ion excitation, and make it difficult to observe a SIM image. Further, since the atomic radius of Ga ions is several orders of magnitude larger than the electron radius and cannot pass through the material surface, the ion-excited secondary electron image reflects the material surface. Therefore, observing and identifying an abnormality due to the groundwork is more difficult and more time-consuming than SEM. In the present invention, since the hole processed by the pulsed laser beam reaches the semiconductor substrate, the irradiated ions flow into the semiconductor substrate through the hole. As a result, the ion-excited secondary electron image has a higher luminance than the surface of the insulator, so that the vicinity of the failure location can be clearly identified.
Therefore, the cause of the failure can be clarified by processing the failure location 11 by the sputter etching using the focused ion beam and observing the structure of the failure location with the SIM image.

Further, similar effects can be obtained by using a surface analyzer, for example, a secondary ion mass spectrometer (SIMS) instead of the SEM observation. That is, the conventional analysis area is positioned by the optical microscope attached to the SIMS main body. However, due to the low magnification, it becomes difficult to identify a local failure part with miniaturization and high integration of the semiconductor device. I have. Therefore, N near the fault location 11 of the semiconductor device 8
d: The YAG pulse laser beam is used to mark a processing hole diameter of 20 μm that can be identified with an optical microscope attached to the SIMS main body, and then the semiconductor device 8 is installed in a secondary ion mass spectrometer (SIMS) to position the analysis region. This increases the positional accuracy of the analysis area, increases the reliability of the analysis data, and helps to clarify the cause of the failure. The analysis conditions were: primary ion Cs, primary ion energy 14.5 KeV, primary ion current 20 nA, primary ion beam diameter 20 μm, raster area 100 μm □, and analysis area 60 μmφ.

As a surface analyzer, an Auger electron spectrometer (AE) is used in addition to a secondary ion mass spectrometer (SIMS).
S), the same effect was obtained by using an energy dispersive X-ray spectrometer (EDX) or a wavelength dispersive X-ray spectrometer (WDX).

[0017]

As described above, according to the present invention, the dyna
Identify the fault location of the memory device by its address, etc.
Marking in four places, up, down, left and right corresponding to the address of
When analyzing the fault location by applying
Easily and quickly find the intersection of the markings
The special effect of being able to identify and analyze obstacles
Play a fruit.

[Brief description of the drawings]

FIG. 1 is a flowchart of a semiconductor device failure analysis method according to the present invention;

FIG. 2 is a configuration diagram of the marking device.

FIG. 3 is a detailed flowchart of the failure analysis method.

FIG. 4 is a top view of the same semiconductor device.

FIG. 5 is a flowchart of a conventional semiconductor device failure analysis method.

[Explanation of symbols]

 Step 1 Electrical measurement Step 2 Marking Step 3 Failure location analysis

Claims (1)

(57) [Claims] 1. A method according to claim 1, wherein the failure location of the dynamic memory device is electrically determined.
Identifying by faulty measurement, and the identified fault location
Marking at four locations: up, down, left and right
And, when analyzing the fault location by a charged beam device,
Identify the fault location by the intersection of the four markings.
A failure analysis method for a semiconductor device, wherein the failure analysis is performed .