JP7468402B2 - How to make a sample - Google Patents

How to make a sample Download PDF

Info

Publication number
JP7468402B2
JP7468402B2 JP2021027657A JP2021027657A JP7468402B2 JP 7468402 B2 JP7468402 B2 JP 7468402B2 JP 2021027657 A JP2021027657 A JP 2021027657A JP 2021027657 A JP2021027657 A JP 2021027657A JP 7468402 B2 JP7468402 B2 JP 7468402B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
observation
resin material
sample
shielding plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2021027657A
Other languages
Japanese (ja)
Other versions
JP2022129094A (en
Inventor
崇史 大月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2021027657A priority Critical patent/JP7468402B2/en
Publication of JP2022129094A publication Critical patent/JP2022129094A/en
Application granted granted Critical
Publication of JP7468402B2 publication Critical patent/JP7468402B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Sampling And Sample Adjustment (AREA)

Description

本開示は、樹脂パッケージの微細な観察箇所の解析前に行うサンプル作成方法に関する。 This disclosure relates to a method for creating samples prior to analysis of minute observation points on a resin package.

近年、半導体製品では低コスト化の要求により樹脂パッケージが急速に普及している。しかし、樹脂パッケージには、不純物による腐食、形成時の応力、動作時の発熱などにより界面剥がれ等の問題が発生する。デバイスの劣化が発生した際に、界面起因の劣化なのか、半導体そのものを原因とした劣化なのかの判別がつかなければ、樹脂材を含むデバイス全体の信頼性を改善できない。界面起因の劣化は樹脂材と半導体の界面において最大数μm程度の範囲にある。このような微細な劣化箇所をSEM、TEM、STEM等で解析する必要がある。 In recent years, the use of resin packages in semiconductor products has rapidly increased due to demands for lower costs. However, resin packages can cause problems such as interface peeling due to corrosion from impurities, stress during formation, and heat generation during operation. When device degradation occurs, unless it can be determined whether the degradation is due to the interface or the semiconductor itself, the reliability of the entire device, including the resin material, cannot be improved. Interface-related degradation is limited to a maximum of a few microns at the interface between the resin material and the semiconductor. Such minute areas of degradation must be analyzed using SEM, TEM, STEM, etc.

一般的な樹脂パッケージ半導体装置の解析方法では、薬液による溶解又はレーザによる灰化で樹脂材を除去し、開封を行う。しかし、解析すべき樹脂材と半導体チップの界面が、開封による影響を受け、最悪の場合には消失してしまう。 The typical method for analyzing resin-packaged semiconductor devices involves removing the resin by dissolving it in a chemical solution or ashing it with a laser, and then opening the package. However, the interface between the resin material to be analyzed and the semiconductor chip is affected by opening the package, and in the worst case scenario, disappears.

また、FIB(Focused Ion Beam)加工装置のみで加工し、SEM等の劣化解析を行う方法もある。しかし、樹脂材の深くに劣化箇所などの微細な観察箇所が存在するため、長時間をかけて広範囲かつデバイスの深くまでFIB加工をしなければならない。また、TEM、STEM解析を実施する場合、デバイスの深い位置から薄片試料を作成せねばならず、実質的に解析は不可能である。これらを解消する方法として、例えば半導体チップ裏面から機械研磨を行い、チップの薄板化を実施した後にFIB加工、イオンミリング等で観察箇所の断面を出し、SEM等で観察する方法がある(例えば、特許文献1参照)。 There is also a method in which processing is performed using only a FIB (Focused Ion Beam) processing device, and degradation analysis is performed using an SEM or similar device. However, because minute observation points such as deteriorated areas exist deep within the resin material, FIB processing must be performed over a wide area and deep into the device over a long period of time. Furthermore, when performing TEM or STEM analysis, a thin sample must be prepared from a deep position in the device, making analysis virtually impossible. To solve these problems, for example, there is a method in which mechanical polishing is performed from the back of the semiconductor chip, the chip is thinned, and then a cross section of the observation point is produced using FIB processing, ion milling, or the like, and observed using an SEM or similar device (see, for example, Patent Document 1).

特開2009-288029号公報JP 2009-288029 A

しかし、機械研磨による応力が樹脂材と半導体チップの界面に影響を与える。従って、半導体が樹脂材より脱離する危険性がある。また、外部光による半導体の劣化を抑制するために樹脂材は不透明であるため、チップ厚みを測定することが出来ず、過剰に研磨してしまう危険性もある。また、最終的にデバイス中の観察箇所の樹脂界面をTEM、STEM等で解析する場合、FIB加工装置を用いて観察箇所を厚み数十~数百nmの薄片にしなければならない。薄片の縦横サイズが大きすぎるとたわみによる破損が発生するため、縦横20μm以下での切り出しが限界である。厚み数μmの界面部を含む断面を縦横20μm以下で切り出すには、チップ基板部分の厚みを10μm程度まで薄板化しなければならないが、機械研磨では10μm程度の精度で加工を行うのは非常に困難である。 However, the stress caused by mechanical polishing affects the interface between the resin material and the semiconductor chip. Therefore, there is a risk that the semiconductor will detach from the resin material. In addition, since the resin material is opaque to prevent semiconductor deterioration due to external light, the chip thickness cannot be measured, and there is a risk of over-polishing. Furthermore, when the resin interface at the observation point in the device is finally analyzed using TEM, STEM, etc., the observation point must be cut into a slice with a thickness of tens to hundreds of nm using an FIB processing device. If the length and width of the slice is too large, damage will occur due to bending, so the limit is cutting to 20 μm or less in length and width. In order to cut out a cross section including an interface part with a thickness of several μm in length and width to 20 μm or less, the thickness of the chip substrate part must be thinned to about 10 μm, but it is very difficult to process with an accuracy of about 10 μm using mechanical polishing.

また、観察箇所を光学観察又はX線透過観察で特定し、観察箇所を半分遮蔽板で覆った状態でArイオンを照射することで観察箇所の断面を切り出す方法もある。この方法は半導体チップにかかる応力が微小なため界面観察に適している。しかし、光学観察又はX線透過観察ができない数μm程度の微小リークなどの位置特定及び加工は困難である。また、広領域のイオンミリングにより掘り進めて観察箇所を探索する方法もあるが、探索の過程で観察箇所が消失する危険性がある。 There is also a method in which the observation location is identified by optical observation or X-ray transmission observation, and a cross section of the observation location is cut out by irradiating Ar ions while the observation location is half covered with a shielding plate. This method is suitable for interface observation because the stress on the semiconductor chip is very small. However, it is difficult to identify and process the location of micro-leaks of about a few micrometers that cannot be observed by optical observation or X-ray transmission observation. There is also a method in which the observation location is searched for by digging through a wide area using ion milling, but there is a risk that the observation location will disappear during the search process.

以上のように樹脂材と半導体チップの界面にある最大数μmの微細な観察箇所の解析に従来のサンプル作成方法は適応できなかった。 As described above, conventional sample preparation methods were not suitable for analyzing minute observation points measuring up to a few microns at the interface between the resin material and the semiconductor chip.

本開示は、上述のような課題を解決するためになされたもので、その目的は樹脂材と半導体チップの界面にある微細な観察箇所の解析に適応できるサンプル作成方法を得るものである。 This disclosure has been made to solve the problems described above, and its purpose is to provide a sample creation method that can be applied to the analysis of minute observation points at the interface between a resin material and a semiconductor chip.

本開示に係るサンプル作成方法は、樹脂パッケージの樹脂材と半導体チップの上面との界面にある観察箇所を解析するためのサンプルを作成する方法において、前記樹脂材から露出した前記半導体チップの下面に密着し、平面視で前記観察箇所を覆いつつ前記観察箇所の周囲を覆わない遮蔽板を前記樹脂パッケージの下面に取り付ける工程と、前記遮蔽板を取り付けた前記樹脂パッケージの下面にイオンビームを照射して前記半導体チップの側面を前記樹脂材から露出させる工程と、前記遮蔽板を除去し、露出した前記半導体チップの側面に光学的測長機器の焦点を合わせて前記半導体チップの厚みを測定しながら前記イオンビームを照射して前記半導体チップを薄板化する工程とを備えることを特徴とする。 The sample preparation method according to the present disclosure is a method for preparing a sample for analyzing an observation location at the interface between the resin material of a resin package and the upper surface of a semiconductor chip, and is characterized by comprising the steps of: attaching a shielding plate to the lower surface of the resin package, which is in close contact with the lower surface of the semiconductor chip exposed from the resin material and covers the observation location in a plan view but does not cover the periphery of the observation location; irradiating an ion beam to the lower surface of the resin package to which the shielding plate is attached, thereby exposing the side surface of the semiconductor chip from the resin material; and removing the shielding plate, focusing an optical length measuring device on the exposed side surface of the semiconductor chip to measure the thickness of the semiconductor chip while irradiating the ion beam to thin the semiconductor chip.

本開示では、遮蔽板で観察箇所を覆ってイオンミリングして半導体チップの側面を露出させ、光学的測長機器で厚みを測定しながら半導体チップを所望の厚みまで薄板化する。これにより、観察箇所が試料表面から半導体チップの薄板化を制御性良く実施することができる。また、加工応力の小さいイオンミリングで半導体チップを薄板化するため、樹脂パッケージの樹脂材と半導体チップの上面との界面にある観察箇所への応力の影響を抑えることができる。従って、本開示に係るサンプル作成方法は、樹脂材と半導体チップの界面にある微細な観察箇所の解析に適応できる。 In the present disclosure, the observation area is covered with a shielding plate and the side of the semiconductor chip is exposed by ion milling, and the semiconductor chip is thinned to the desired thickness while the thickness is measured with an optical length measuring device. This allows the semiconductor chip to be thinned with good controllability from the observation area being the sample surface. In addition, because the semiconductor chip is thinned by ion milling, which has a small processing stress, the effect of stress on the observation area at the interface between the resin material of the resin package and the top surface of the semiconductor chip can be suppressed. Therefore, the sample creation method according to the present disclosure can be applied to the analysis of a minute observation area at the interface between the resin material and the semiconductor chip.

劣化解析対象である樹脂パッケージを示す断面図である。1 is a cross-sectional view showing a resin package that is the subject of degradation analysis; 実施の形態に係るサンプル作成方法のフローチャートである。1 is a flowchart of a sample preparation method according to an embodiment. 実施の形態に係るサンプル作成方法を示す断面図である。1A to 1C are cross-sectional views showing a sample preparation method according to an embodiment. 実施の形態に係るサンプル作成方法を示す断面図である。1A to 1C are cross-sectional views showing a sample preparation method according to an embodiment. 実施の形態に係るサンプル作成方法を示す断面図である。1A to 1C are cross-sectional views showing a sample preparation method according to an embodiment. 実施の形態に係るサンプル作成方法を示す断面図である。1A to 1C are cross-sectional views showing a sample preparation method according to an embodiment. 実施の形態に係るサンプル作成方法を示す断面図である。1A to 1C are cross-sectional views showing a sample preparation method according to an embodiment. 半導体チップを薄板化した樹脂パッケージを示す斜視図である。FIG. 1 is a perspective view showing a resin package in which a semiconductor chip is thinned. 半導体チップを薄板化した樹脂パッケージを示す側面図である。1 is a side view showing a resin package in which a semiconductor chip is thinned; 半導体チップを薄板化した樹脂パッケージを示す下面図である。1 is a bottom view showing a resin package in which a semiconductor chip is thinned. 作成したサンプルをSTEMで観察した結果を示す図である。FIG. 13 is a diagram showing the results of observing the prepared sample with an STEM.

図1は、劣化解析対象である樹脂パッケージを示す断面図である。半導体チップ1が樹脂材2で覆われて樹脂パッケージ3が構成されている。半導体チップ1は、例えばGaN-HEMT(High Electron Mobility Transistor)チップである。半導体チップ1の下面に金属板4が設けられている。金属板4は金属フレーム又は裏面メタル等である。樹脂パッケージ3の下面において金属板4は樹脂材2から露出している。 Figure 1 is a cross-sectional view of a resin package that is the subject of degradation analysis. A semiconductor chip 1 is covered with a resin material 2 to form a resin package 3. The semiconductor chip 1 is, for example, a GaN-HEMT (High Electron Mobility Transistor) chip. A metal plate 4 is provided on the underside of the semiconductor chip 1. The metal plate 4 is a metal frame or a backside metal, etc. At the underside of the resin package 3, the metal plate 4 is exposed from the resin material 2.

半導体チップ1は上面に配線及び電極5と絶縁膜6を有する。樹脂パッケージ3の樹脂材2と半導体チップ1の上面との界面に、劣化箇所などの微細な観察箇所7が存在する。観察箇所7は最大数μm程度の範囲に存在する。 The semiconductor chip 1 has wiring and electrodes 5 and an insulating film 6 on its top surface. At the interface between the resin material 2 of the resin package 3 and the top surface of the semiconductor chip 1, there are minute observation points 7, such as deteriorated areas. The observation points 7 exist in a range of up to several μm.

本実施の形態では、上記の樹脂パッケージを加工して、樹脂パッケージ3の樹脂材2と半導体チップ1の上面との界面にある観察箇所7をSEM、TEM又はSTEMを用いて解析するためのサンプルを作成する。図2は、実施の形態に係るサンプル作成方法のフローチャートである。図3から図7は、実施の形態に係るサンプル作成方法を示す断面図である。 In this embodiment, the resin package is processed to create a sample for analyzing the observation point 7 at the interface between the resin material 2 of the resin package 3 and the top surface of the semiconductor chip 1 using SEM, TEM, or STEM. Figure 2 is a flowchart of the sample creation method according to the embodiment. Figures 3 to 7 are cross-sectional views showing the sample creation method according to the embodiment.

まず、図3に示すように、機械研磨等により金属板4を除去して半導体チップ1の下面を露出させる。なお、金属板4が存在せず半導体チップ1の下面が露出した樹脂パッケージを用いてもよく、その場合には金属板4を除去する工程は省略できる。 First, as shown in FIG. 3, the metal plate 4 is removed by mechanical polishing or the like to expose the underside of the semiconductor chip 1. Note that a resin package in which the metal plate 4 is not present and the underside of the semiconductor chip 1 is exposed may be used, in which case the step of removing the metal plate 4 can be omitted.

次に、図4に示すように、遮蔽板8を樹脂パッケージ3の下面に取り付け、樹脂材2から露出した半導体チップ1の下面に密着させる(ステップS1)。ここで、遮蔽板8は、半導体チップ1の下面に対して垂直方向から見た平面視で、観察箇所7を覆いつつ観察箇所7の周囲を覆わないように配置する。遮蔽板8の端部は、樹脂材2と半導体チップ1の側面の1つの境界に配置されているが、当該境界よりも半導体チップ1の内側に配置されていてもよい。例えば、矩形の半導体チップ1の最低1辺の側面が露出するように遮蔽板8を取り付ける場合は、遮蔽板8は矩形のものが望ましい。なお、観察箇所7の特定が必要な場合は、光学観察、OBIRCH(Optical Beam Induced Resistance CHange)、発光解析、又は発熱解析等の公知の特定方法を用いる。 Next, as shown in FIG. 4, the shielding plate 8 is attached to the bottom surface of the resin package 3 and is brought into close contact with the bottom surface of the semiconductor chip 1 exposed from the resin material 2 (step S1). Here, the shielding plate 8 is arranged so as to cover the observation point 7 but not to cover the periphery of the observation point 7 in a plan view seen from a direction perpendicular to the bottom surface of the semiconductor chip 1. The end of the shielding plate 8 is arranged at one boundary between the resin material 2 and the side surface of the semiconductor chip 1, but may be arranged inside the semiconductor chip 1 from the boundary. For example, when the shielding plate 8 is attached so that at least one side surface of the rectangular semiconductor chip 1 is exposed, it is preferable that the shielding plate 8 is rectangular. If it is necessary to identify the observation point 7, a known identification method such as optical observation, OBIRCH (Optical Beam Induced Resistance CHange), light emission analysis, or heat generation analysis is used.

次に、樹脂パッケージ3をイオンミリング装置に入れる。イオンミリング装置は、半導体チップ1の厚みを測定する光学的測長機器9と、イオンミリングによる飛散物から光学的測長機器9を保護するために透明体10とを有する。遮蔽板8を取り付けた樹脂パッケージ3の下面にイオンビーム11を照射して樹脂材2をイオンミリングして、半導体チップ1の側面を樹脂材2から露出させる(ステップS2)。これにより、半導体チップ1の側面からチップ厚みが測定可能となる。図5に示すように、半導体チップ1の側面を観察し(ステップS3)、チップ側面からチップ厚みが測定可能な状態になっていれば本工程を完了する(ステップS4)。チップ側面の観察には、イオンミリング装置からチップを取り出して光学観察又はSEM観察などを用いるか、又は、光学的測長機器9を用いる。 Next, the resin package 3 is placed in an ion milling device. The ion milling device has an optical length measuring device 9 for measuring the thickness of the semiconductor chip 1, and a transparent body 10 for protecting the optical length measuring device 9 from debris caused by ion milling. An ion beam 11 is irradiated onto the underside of the resin package 3 to which the shielding plate 8 is attached, ion milling the resin material 2, and exposing the side of the semiconductor chip 1 from the resin material 2 (step S2). This makes it possible to measure the chip thickness from the side of the semiconductor chip 1. As shown in FIG. 5, the side of the semiconductor chip 1 is observed (step S3), and if the chip thickness can be measured from the chip side, this process is completed (step S4). To observe the chip side, the chip is removed from the ion milling device and optical observation or SEM observation, or the optical length measuring device 9 is used.

なお、必ずしも半導体チップ1の側面全体が露出する必要はなく、チップ側面からチップ厚みが測定可能な状態になっていればよい。また、遮蔽板8で遮蔽されていない領域がイオンビーム11により完全に除去される必要はない。イオンビーム11の加速電圧、加工時間は加工する材質に応じて適宜調整する。観察箇所7は遮蔽板8で覆われているためイオンミリングされない。 Note that it is not necessary for the entire side of the semiconductor chip 1 to be exposed, as long as the chip thickness can be measured from the side of the chip. Furthermore, it is not necessary for the area not shielded by the shielding plate 8 to be completely removed by the ion beam 11. The acceleration voltage and processing time of the ion beam 11 are adjusted appropriately according to the material to be processed. The observation point 7 is not ion milled because it is covered by the shielding plate 8.

次に、図6に示すように、遮蔽板8を除去し、樹脂パッケージ3の下面にイオンビーム11を照射して半導体チップ1を薄板化する(ステップS5)。この際に、露出した半導体チップ1の側面に光学的測長機器9の焦点を合わせて半導体チップ1の厚みを測定しながらイオンミリングを実施する。イオンビーム11の加速電圧、照射ビーム中心位置は観察対象の半導体チップ1の形状、材質に応じて適宜調整する。 Next, as shown in FIG. 6, the shielding plate 8 is removed, and the underside of the resin package 3 is irradiated with an ion beam 11 to thin the semiconductor chip 1 (step S5). At this time, the optical length measuring device 9 is focused on the exposed side of the semiconductor chip 1 to measure the thickness of the semiconductor chip 1 while performing ion milling. The acceleration voltage of the ion beam 11 and the center position of the irradiated beam are adjusted appropriately according to the shape and material of the semiconductor chip 1 to be observed.

図7に示すように半導体チップ1の厚みを測定し(ステップS6)、所望の厚みに達した時点でイオンビーム11を停止する(ステップS7)。なお、TEM又はSTEMの解析を実施する場合には薄片試料を作成する必要があるため、半導体チップ1を概ね10μm程度の厚みまで薄板化する必要がある。 As shown in FIG. 7, the thickness of the semiconductor chip 1 is measured (step S6), and the ion beam 11 is stopped when the desired thickness is reached (step S7). Note that when performing TEM or STEM analysis, it is necessary to prepare a thin sample, so the semiconductor chip 1 needs to be thinned to a thickness of approximately 10 μm.

光学的測長機器9は、例えば対物レンズ、接眼レンズ、CCDセンサのような電子的な撮像素子を用いる機器である。この場合、レンズ倍率だけではなく撮像素子の画素数、画素サイズにも光学的測長機器9の分解能が依存する。チップを薄板化する工程で所望の厚みに達したか否かを判定する必要があるため、光学的測長機器9は半導体チップ1の側面に焦点を合わせた際に十分な分解能を有する必要がある。そして、加工したサンプルをTEM観察する場合、縦横~10μmの薄片試料を作成する必要がある。最終的なチップ厚さが厚すぎるとTEM観察を実施する薄片試料が自重でたわむ、ハンドリングで破損するなどの問題がある。従って、チップ側面部を観察した時に数μmの段差を認識する必要がある。このため、光学的測長機器9は数μmの分解能を有することが必要である。 The optical length measuring device 9 is a device that uses an electronic imaging element such as an objective lens, an eyepiece lens, or a CCD sensor. In this case, the resolution of the optical length measuring device 9 depends not only on the lens magnification but also on the number of pixels and pixel size of the imaging element. Since it is necessary to determine whether the desired thickness has been reached in the process of thinning the chip, the optical length measuring device 9 needs to have sufficient resolution when focusing on the side of the semiconductor chip 1. When observing the processed sample with a TEM, it is necessary to create a thin slice sample with a length and width of 10 μm. If the final chip thickness is too thick, there are problems such as the thin slice sample used for TEM observation bending under its own weight and being damaged during handling. Therefore, it is necessary to recognize a step of several μm when observing the side of the chip. For this reason, the optical length measuring device 9 needs to have a resolution of several μm.

図8は、半導体チップを薄板化した樹脂パッケージを示す斜視図である。図9は、半導体チップを薄板化した樹脂パッケージを示す側面図である。図10は、半導体チップを薄板化した樹脂パッケージを示す下面図である。薄板化した半導体チップ1の下面からFIB加工等を行って観察箇所7を図8のI-IIに沿って断面加工する。さらに薄片加工を行うことで観察箇所を解析するためのサンプルを作成することができる。 Figure 8 is a perspective view showing a resin package in which a semiconductor chip has been thinned. Figure 9 is a side view showing a resin package in which a semiconductor chip has been thinned. Figure 10 is a bottom view showing a resin package in which a semiconductor chip has been thinned. FIB processing or the like is performed from the bottom surface of the thinned semiconductor chip 1 to cross-process the observation area 7 along I-II in Figure 8. Further thin-section processing can be performed to create a sample for analyzing the observation area.

図11は、作成したサンプルをSTEMで観察した結果を示す図である。観察箇所7の特定はOBIRCHによって実施した。樹脂材2と半導体チップ1の界面がSEMとSTEMの両方法で観察可能であることがわかる。 Figure 11 shows the results of observing the prepared sample with an STEM. The observation point 7 was identified by OBIRCH. It can be seen that the interface between the resin material 2 and the semiconductor chip 1 can be observed by both the SEM and STEM methods.

ここで、樹脂材2と半導体チップ1の界面にある最大数μmの微細な観察箇所を解析するためのサンプル作成方法は以下の3つの要件を満たす必要がある。
(1)樹脂材と半導体チップの界面への応力等の影響を最小限に抑えること。
(2)劣化箇所などの微細な観察箇所が試料表面から最大10μm程度の位置になるよう制御された厚み方向への加工が可能なこと。
(3)空間分解能数μm程度で断面解析及びTEM、STEM解析するための薄片試料の作成が可能であること。
Here, the method of preparing a sample for analyzing a minute observation point of up to several μm in size at the interface between the resin material 2 and the semiconductor chip 1 must satisfy the following three requirements.
(1) The effects of stress on the interface between the resin material and the semiconductor chip must be minimized.
(2) It is possible to perform controlled processing in the thickness direction so that minute observation points such as deteriorated areas are located at a maximum of about 10 μm from the sample surface.
(3) It is possible to prepare thin specimens for cross-sectional analysis and TEM and STEM analysis with a spatial resolution of about several micrometers.

これに対して、本実施の形態では、遮蔽板8で観察箇所7を覆ってイオンミリングして半導体チップ1の側面を露出させ、光学的測長機器9で厚みを測定しながら半導体チップ1を所望の厚みまで薄板化する。これにより、観察箇所7が試料表面から最大10μm程度の位置になるように半導体チップ1の薄板化を制御性良く実施することができる。また、加工応力の小さいイオンミリングで半導体チップ1を薄板化するため、樹脂パッケージ3の樹脂材2と半導体チップ1の上面との界面にある観察箇所7への応力の影響を抑えることができる。そして、薄板化した半導体チップ1の下面からFIB加工等を行って観察箇所7を断面加工する。これより、空間分解能数μm程度で断面解析及びTEM、STEM解析するための薄片試料の作成が可能である。 In contrast, in this embodiment, the observation point 7 is covered with a shielding plate 8, ion milling is performed to expose the side of the semiconductor chip 1, and the semiconductor chip 1 is thinned to the desired thickness while measuring the thickness with an optical length measuring device 9. This allows the semiconductor chip 1 to be thinned with good control so that the observation point 7 is located at a maximum of about 10 μm from the sample surface. In addition, since the semiconductor chip 1 is thinned by ion milling, which has a small processing stress, the effect of stress on the observation point 7 at the interface between the resin material 2 of the resin package 3 and the upper surface of the semiconductor chip 1 can be suppressed. Then, FIB processing or the like is performed from the lower surface of the thinned semiconductor chip 1 to cross-process the observation point 7. This makes it possible to create a thin slice sample for cross-sectional analysis and TEM and STEM analysis with a spatial resolution of about several μm.

よって、本実施の形態に係るサンプル作成方法は、樹脂材と半導体チップの界面にある微細な観察箇所の解析に適応できる。 Therefore, the sample creation method according to this embodiment can be applied to the analysis of minute observation points at the interface between the resin material and the semiconductor chip.

1 半導体チップ、2 樹脂材、3 樹脂パッケージ、7 観察箇所、8 遮蔽板、9 光学的測長機器、11 イオンビーム 1 Semiconductor chip, 2 Resin material, 3 Resin package, 7 Observation point, 8 Shielding plate, 9 Optical length measuring device, 11 Ion beam

Claims (2)

樹脂パッケージの樹脂材と半導体チップの上面との界面にある観察箇所を解析するためのサンプルを作成する方法において、
前記樹脂材から露出した前記半導体チップの下面に密着し、平面視で前記観察箇所を覆いつつ前記観察箇所の周囲を覆わない遮蔽板を前記樹脂パッケージの下面に取り付ける工程と、
前記遮蔽板を取り付けた前記樹脂パッケージの下面にイオンビームを照射して前記半導体チップの側面を前記樹脂材から露出させる工程と、
前記遮蔽板を除去し、露出した前記半導体チップの側面に光学的測長機器の焦点を合わせて前記半導体チップの厚みを測定しながら前記イオンビームを照射して前記半導体チップを薄板化する工程とを備えることを特徴とするサンプル作成方法。
1. A method for preparing a sample for analyzing an observation location at an interface between a resin material of a resin package and an upper surface of a semiconductor chip, comprising:
a step of attaching a shielding plate to a lower surface of the resin package, the shielding plate being in close contact with a lower surface of the semiconductor chip exposed from the resin material, and covering the observation area in a plan view but not covering a periphery of the observation area;
a step of irradiating an ion beam onto a lower surface of the resin package to which the shielding plate is attached, thereby exposing a side surface of the semiconductor chip from the resin material;
and removing the shielding plate, and measuring the thickness of the exposed side of the semiconductor chip by focusing an optical length measuring device on the side of the semiconductor chip and irradiating the ion beam while thinning the semiconductor chip.
薄板化した前記半導体チップの前記観察箇所を断面加工する工程を更に備えることを特徴とする請求項1に記載のサンプル作成方法。 The sample creation method according to claim 1, further comprising a step of cross-machining the observation portion of the thinned semiconductor chip.
JP2021027657A 2021-02-24 2021-02-24 How to make a sample Active JP7468402B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2021027657A JP7468402B2 (en) 2021-02-24 2021-02-24 How to make a sample

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2021027657A JP7468402B2 (en) 2021-02-24 2021-02-24 How to make a sample

Publications (2)

Publication Number Publication Date
JP2022129094A JP2022129094A (en) 2022-09-05
JP7468402B2 true JP7468402B2 (en) 2024-04-16

Family

ID=83150521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021027657A Active JP7468402B2 (en) 2021-02-24 2021-02-24 How to make a sample

Country Status (1)

Country Link
JP (1) JP7468402B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009288029A (en) 2008-05-28 2009-12-10 Toyota Motor Corp Sample preparing method, and jig for performing the same
JP2010230665A (en) 2009-03-05 2010-10-14 Jeol Ltd Device and method for preparing sample cross section using ion beam
JP2015109263A (en) 2013-10-24 2015-06-11 株式会社日立ハイテクサイエンス Cross section processing method, and cross section processing device
WO2019224993A1 (en) 2018-05-25 2019-11-28 三菱電機株式会社 Preparation method for specimen for transmission electron microscope
JP2020085548A (en) 2018-11-20 2020-06-04 日本電子株式会社 Section sample preparation method by ion beam processing device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009288029A (en) 2008-05-28 2009-12-10 Toyota Motor Corp Sample preparing method, and jig for performing the same
JP2010230665A (en) 2009-03-05 2010-10-14 Jeol Ltd Device and method for preparing sample cross section using ion beam
JP2015109263A (en) 2013-10-24 2015-06-11 株式会社日立ハイテクサイエンス Cross section processing method, and cross section processing device
WO2019224993A1 (en) 2018-05-25 2019-11-28 三菱電機株式会社 Preparation method for specimen for transmission electron microscope
US20210102872A1 (en) 2018-05-25 2021-04-08 Mitsubishi Electric Corporation Method of producing test-sample for transmission electron microscope
JP2020085548A (en) 2018-11-20 2020-06-04 日本電子株式会社 Section sample preparation method by ion beam processing device

Also Published As

Publication number Publication date
JP2022129094A (en) 2022-09-05

Similar Documents

Publication Publication Date Title
TWI676203B (en) Pattern matching using a lamella of known shape for automated s/tem acquisition and metrology
JP5711204B2 (en) Methods and apparatus for sample extraction and handling
CN104008956B (en) Opening method for flip chip devices
JP6356397B2 (en) Substrate outside position analysis system and method
CN102062710B (en) Preparation method of observation sample for transmission electron microscope
JP2007155524A (en) Manufacturing method of sample for transmission type electron microscope, observation method and structure
JP2012073069A (en) Preparation method of specimen for observing defective part of semiconductor device substrate
WO2012157160A1 (en) Defect review apparatus
CN116298810B (en) Failure analysis method for high-order chip
CN104155156A (en) Preparation method of TEM plane sample
JP2013114854A (en) Sample observation device and marking method
JP2004022318A (en) Transmission electron microscope and sample analysis method
JP7468402B2 (en) How to make a sample
US7682844B2 (en) Silicon substrate processing method for observing defects in semiconductor devices and defect-detecting method
CN104792585B (en) Preparation method for TEM sample
JP4091060B2 (en) Wafer inspection processing apparatus and wafer inspection processing method
KR102495078B1 (en) Defect Analysis
TWI240422B (en) Method of preparing for structural analysis of deep trench capacitors and structural analysis method thereof
US20080171448A1 (en) System and method for selectively etching an integrated circuit
JP2007033461A (en) Wafer inspection device
JP2013246001A (en) Charged particle beam device and sample preparation method
KR100826763B1 (en) Manufacturing method for vertical analysis piece and analysis method thereby
EP3070731A1 (en) Pattern matching using a lamella of known shape for automated s/tem acquisition and metrology
CN113871313A (en) Chip detection system and detection method
JP2912745B2 (en) Failure analysis method for semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20230808

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20240221

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20240305

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20240318

R150 Certificate of patent or registration of utility model

Ref document number: 7468402

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150