JP2941347B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Purpose of the Invention] (Industrial application field) The present invention relates to a semiconductor device such as a conduction modulation type MOSFET having a pnpn structure.

(Prior Art) FIG. 9 shows a structure of a turn-off portion of a conventional conduction modulation type MOSFET. The surface of the high-resistance n-type base layer 1 has p
A mold base layer 2 is selectively formed by diffusion, and a p-type emitter layer (drain layer) 4 is formed by diffusion through an n-type buffer layer 3 on the back surface. On the surface of the p-type base layer 2, an n-type emitter layer (source layer) 5 is selectively formed. n
Around the emitter layer 5, an n-type turn-off channel forming layer 6 is formed.
Inside, a p-type drain layer 7 is formed in contact with n-type emitter layer 5. A gate electrode 9 is formed on a surface of the n-type turn-off channel forming layer 6 in a region interposed between the p-type drain layer 7 and the p-type base layer 2 via a gate insulating film 8. The cathode electrode 10 is formed over the n-type emitter layer 5 and the p-type drain layer 6 in contact therewith. An anode electrode 11 is formed on the p-type emitter layer 4.

The turn-off operation of the conduction modulation type MOSFET is as follows. At the time of turning off, a negative voltage is applied to the gate electrode 9. As a result, the turn-off channel CH under the gate electrode 9 is inverted, and the p-type base layer and the p-type drain layer 7 are short-circuited via the channel CH. As a result, a part of the current flowing in the n-type emitter layer 5 is shunted through the channel CH and flows to the cathode electrode 10 as shown by a broken line. Eventually, the pn between the n-type emitter layer 5 and the p-type base layer 2
Is restored, the electron injection that is open from the n-type emitter layer 5 stops, and the element is turned off.

Conventional conductive modulation type MO with such a turn-off structure
In the SFET, there was a problem that the turn-off capability was low.
This is because the current flowing through the channel CH at the time of turn-off flows around under the n-type turn-off channel forming layer 6 in the p-type base layer 2 as shown by the broken line in the figure. Therefore, since this current path is long and flows through a deep portion where the sheet resistance of the p-type base layer 2 is high, the voltage drop due to the shunt current is large. Because of this voltage drop, a forward bias is applied to the junction between the n-type emitter layer 5 and the p-type base layer 2, and it takes a long time until the junction is recovered, or in some cases, the junction is not recovered. .

A similar problem occurs when a similar turn-off structure is employed in a gate turn-off thyristor or the like.

(Problems to be Solved by the Invention) As described above, at the time of turn-off, in the conventional conduction modulation type MOSFET or the like which shunts the current flowing through the cathode electrode using the turn-off MOS channel,
There is a problem in that the turn-off capability is low because the current of the MOS channel flows a long distance in a lateral direction in a region having a high sheet resistance under the channel forming layer.

An object of the present invention is to provide a semiconductor device having a turn-off MOS channel structure with improved turn-off capability based on a pnpn element structure.

[Structure of the Invention] (Means for Solving the Problems) In a semiconductor device according to the present invention, a first conductivity type emitter layer is in contact with the first conductivity type emitter layer directly or via a second conductivity type buffer layer. A second conductivity type base layer, a first conductivity type base layer selectively formed on the second conductivity type base layer surface portion, and a first conductivity type base layer formed on the first conductivity type base layer surface portion at a distance from each other. A first and a second conductive type emitter layer; and a second conductive layer formed on the surface of the first conductive type base layer in contact with or adjacent to one end of the second second conductive type emitter layer. Type turn-off channel formation layer, a first conductivity type impurity layer formed in the turn-off channel formation layer, the first conductivity type impurity layer and the first conductivity type base layer on the surface of the turn-off channel formation layer. Gate on the sandwiched area A gate electrode formed via a Enmaku, first electrically connected to the first conductive type emitter layer 1
Main electrode, the first and second emitter layers of the second conductivity type and the first
A second main electrode electrically connected to the conductivity type impurity layer, wherein the first second conductivity type emitter layer and the turn-off channel forming layer sandwich the first conductivity type base layer. Are adjacent to each other.

(Operation) According to the present invention, when a voltage is applied to the gate electrode at the time of turn-off to shunt the current flowing in the second conductivity type emitter layer through the channel on the surface of the turn-off channel layer, the shunt current is applied to the second conductivity type emitter layer. Since the current flows from below into the adjacent channel through the first conductivity type base layer surface portion, the path of the shunt current is shortened. Moreover, this shunt current is the first
Since the current flows through the surface of the conductive type base layer having a low sheet resistance, the voltage drop in the first conductive type base layer is small. Majority carriers are collected on the surface of the first conductivity type base layer adjacent to the turn-off channel below the gate electrode by applying a gate voltage, and this also has an effect of reducing a voltage drop in the first conductivity type base layer. As a result, the pn junction between the emitter layer of the second conductivity type and the base layer of the first conductivity type can be quickly recovered, and the turn-off capability is improved.

(Example) Hereinafter, an example of the present invention will be described.

FIG. 1 is a plan view showing a conductive modulation type MOSFET according to one embodiment of the present invention. 2 (a) and 2 (b) are AA 'in FIG.
3 and 3 are perspective views.
Parts corresponding to those in FIG. 7 of the conventional example are denoted by the same reference numerals as in FIG. A p-type base layer 2 is selectively formed on one surface of a high-resistance n-type base layer 1 by diffusion, and a p-type emitter layer 4 is formed on the other surface by diffusion via an n-type buffer layer 3. On the surface of the p-type base layer 3, a plurality of stripe-shaped n-type emitter layers 5 are formed by diffusion. The surface of the p-type base layer 3 is also in contact with one long side of each of the n-type emitter layers 5 and the n-type turn-off channel forming layer 6.
Are formed by diffusion. Turn-off channel forming layer 6
Are formed deeper than the n-type emitter layer 5 by diffusion. An n-type emitter layer 5 is formed on the surface of the turn-off channel forming layer 6.
, A p-type impurity layer 7 is formed by diffusion.

The surface of the turn-off channel forming layer 6 sandwiched between the p-type base layer 2 and the p-type impurity layer 7 is a turn-off channel CH ₁ , and the p-type base sandwiched between the n-type base layer 1 and the n-type emitter layer 5. surface portion of the layer 2 is in the off channel CH _2. That is, the turn-off channel CH is adjacent to the long side of the striped n-type emitter layer 5.
₁ is formed, and the turn-off channel CH ₂ is adjacent to the short side.
Are formed. The p-type impurity layer 7 for drawing the cathode current shunted at the time of turn-off is provided only on one long side of the n-type emitter layer 5, and the other long side is
Turn-off channel forming layer 6 via mold base layer 2
Is adjacent to So as to cover these channel regions,
A gate electrode 9 is provided via a gate insulating film 8. A cathode electrode 10 is formed on the n-type emitter layer 5 surrounded by the gate electrode 9 so as to extend over the p-type impurity layer 7. The entire surface of the p-type emitter layer 4 is an anode electrode
11 are formed.

The conduction modulation type MOSFET of this embodiment is turned on by applying a positive voltage to the gate electrode. At this time, the turn-on channel CH ₂ is inverted and electrons are injected from the n-type emitter layer 5 into the n-type base layer 1 via the p-type base layer 2. When these electrons enter the p-type emitter layer 4 via the n-type buffer layer 3, holes are injected from the p-type emitter layer 4, and as a result, conduction modulation occurs in the n-type base layer 1.

The turn-off operation is performed by applying a negative voltage to the gate electrode. At this time, the current flowing through the element is shunted as shown by the broken line in FIG. That is, the shunt current passes from below the n-type emitter layer 5 to the surface of the p-type base layer 2 below the gate electrode 9, passes through the channel CH 1 on the surface of the turn-off channel formation layer 6, and flows from the p-type impurity layer 7 to the cathode. It flows to the electrode 10. The path of the shunt current is shorter than that in the case of detouring under the turn-off channel forming layer as in the related art, and flows through a shallow portion of the p-type base layer where the sheet resistance is low, so that the voltage drop is small.
Further, since a majority of the majority carriers are gathered on the surface of the p-type base layer 2 by the negative voltage applied to the gate electrode 9, the voltage drop is also reduced.

As a result, according to this embodiment, the p-type base layer 2 and n
The pn junction between the mold emitter layers 5 recovers quickly. That is, the turn-off ability is improved.

FIGS. 4 (a) and 4 (b) show another embodiment of a conductive modulation type MOSFET.
3A and 3B are a plan view and an AA 'sectional view thereof. Parts corresponding to those in the previous embodiment are denoted by the same reference numerals, and detailed description is omitted. In this embodiment, a plurality of n-type turn-off channel forming layers 6 are formed in a ring shape, and an n-type emitter layer 5 is formed inside each of them with a predetermined distance therebetween. Then, a p-type impurity layer 7 is formed in the n-type turn-off channel formation layer 6. ring turnoff gate electrodes 9 ₁ so as to straddle between the p-type impurity layer 7 and the n-type emitter layer 5 is formed. Apart from the gate electrode 9 ₁ for this turn-off, the gate electrode 9 ₂ for turn-on to the end portion of the p-type base layer 2 is formed. N-type emitter layer in the region surrounded by the gate electrode 9 ₁ 5 and the gate electrode 9 ₁
The cathode electrode 10 is formed in contact with the p-type impurity layer 7 outside. Although the plan view shows separate the portion in contact with the part and the p-type impurity layer 7 in contact with the n-type emitter layer 5 of the cathode electrode 10, in fact continuously arrangement astride the gate electrode 9 ₁ above Is established.

Also in the conduction modulation type MOSFET of this embodiment, at the time of turn-off, part of the cathode current can be discharged to the cathode electrode 10 via the p-type impurity layer 7 without bypassing below the n-type turn-off channel forming layer 6. . Therefore, the turn-off capability is high as in the previous embodiment.

FIG. 5 is a sectional view corresponding to FIG. 2 (a) of a conductive modulation type MOSFET of another embodiment. The structure on the cathode side is the same as that of the embodiment described with reference to FIGS. 1 to 3, and accordingly, portions corresponding to FIG. 2 (a) are denoted by the same reference numerals, and detailed description is omitted. In this embodiment, the same MOS gate structure as the cathode side is introduced for the anode side. That is, a plurality of divided p-type emitter layers 42 are formed on the surface of the n-type buffer layer 3, and the p-type turn-off channel forming layer is in contact with one long side of each p-type emitter layer 42.
41 are formed, and p in the turn-off channel forming layer 41 is formed.
An n-type impurity layer 43 is formed in a portion in contact with the type emitter layer 42. N-type impurity layer of turn-off channel forming layer 41
Region sandwiched by 43 and the n-type buffer layer 3 and the turn-off channel CH _3, the gate electrode 45 is formed via a gate insulating film 44 on the channel region. The anode electrode 11 is divided, and each p-type emitter layer 42 and an n-type impurity layer 43 in contact with the p-type emitter layer 42 are formed so as to straddle.

In the conduction modulation type MOSFET of this embodiment, at the time of turn-off,
A negative voltage is applied to the gate electrode 9 on the cathode side, and a positive voltage is applied to the gate electrode 44 on the anode side. On the cathode side, as described in the embodiment of FIGS.
The hole current flowing through the type emitter layer 5 is shunted through the channel CH _1. On the anode side, the electron current flowing through the p-type emitter layer 42 is shunted through the channel CH ₃ to form the n-type impurity layer 4.
From 3 flows to the anode electrode 11. This shunt on the anode side is similar to the shunt on the cathode side, and the voltage drop due to this is small. Therefore, the recovery of the pn junction between the n-type buffer layer and the p-type emitter layer 42 is promptly performed, so that the turn-off capability is significantly improved.

FIG. 6 shows an embodiment in which the structure on the cathode side of the embodiment shown in FIG. 2 (a) or FIG. 5 is modified. In this embodiment, the n-type emitter layer 5 is formed to be deeper than the n-type turn-off channel forming layer 6. In order to form the n-type emitter layer having a higher concentration shallower than the turn-off channel formation layer, a heat diffusion step is required for each. However, when the n-type emitter layer 5 is formed deep as in this embodiment, Can perform their heat diffusion process once,
It becomes advantageous in the process.

FIG. 7 shows an embodiment in which the structure on the cathode side of the embodiment shown in FIG. 2 (a) or FIG. 5 is modified, and the n-type emitter layer is formed so as to be in contact with the n-type turn-off channel forming layer 7. , P-type impurity layer 6 in turn-off channel layer 7
Are formed separately from the n-type emitter layer 5. In this way, the peak of the total amount of impurities per unit area of the n-type emitter layer 5 and the n-type turn-off channel layer 7 exists in the n-type emitter layer 5, and the emitter resistance is reduced.

FIG. 8 shows an embodiment in which the present invention is applied to a GTO thyristor. The structure on the anode side is the same as in FIG. On the cathode side, a plurality of n-type emitter layers 5 are divided and arranged.
A gate electrode 46 that is in direct contact with the mold base layer 2 is formed.

The turn-on and turn-off operations of the GTO thyristor are performed by applying a positive voltage and a negative voltage to the gate electrode 46 on the cathode side, respectively. During the turn-off operation, a positive voltage of the gate electrode 44 on the anode side is simultaneously applied. As a result, the current flowing into the p-type emitter layer 42 is divided and discharged from the cathode electrode 11, as described in the embodiment of FIG. Therefore, also in this embodiment, a high-speed turn-off operation can be performed.

[Effects of the Invention] As described above, according to the present invention, the shunt current at the time of gate turn-off is discharged without bypassing the high-resistance region below the turn-off channel forming layer, thereby improving the turn-off capability. Semiconductor device can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view showing a conductive modulation type MOSFET according to an embodiment of the present invention. FIGS. 2 (a) and 2 (b) are cross-sectional views taken along lines AA 'and BB' of FIG. 1, respectively. FIG. 3 is a perspective view of the same, FIGS. 4 (a) and 4 (b) are a plan view and a sectional view taken along the line AA 'of a conductive modulation type MOSFET of another embodiment, and FIG. FIG. 6 is a cross-sectional view of a conductive modulation type MOSFET according to still another embodiment, FIG. 7 is a cross-sectional view of a conductive modulation type MOSFET according to still another embodiment, and FIG. FIG. 9 is a sectional view of a conventional conduction modulation type MOSFET applied to a thyristor. 1. High resistance n-type base layer, 2. p-type base layer, 3.
... n-type buffer layer, 4 ... p-type emitter layer, 5 ... n-type emitter layer, 6 ... ... n-type turn-off channel forming layer, 7
... P-type impurity layer, 8 gate insulating film, 9 gate electrode, 10 cathode electrode, 11 anode electrode, 41
... p-type turn-off channel formation layer, 42 ... p-type emitter layer, 43 ... n-type impurity film, 44 ... gate insulating film, 45 ...
Gate electrode, CH ₁ turn-off channel, CH ₂ turn-on channel.

Claims (6)

(57) [Claims] A first conductive type emitter layer; a second conductive type base layer in contact with the first conductive type emitter layer directly or via a second conductive type buffer layer; and a surface portion of the second conductive type base layer. A first conductive type base layer selectively formed on the first conductive type base layer; first and second second conductive type emitter layers formed on a surface portion of the first conductive type base or the like at a distance from each other; A second conductivity type turn-off channel formation layer formed on or in contact with one end of the second second conductivity type emitter layer on a surface portion of the conductivity type base layer; and formed in the turn-off channel formation layer. A first conductive type impurity layer, and a gate electrode formed on a surface of the turn-off channel formation layer on a region between the first conductive type impurity layer and the first conductive type base layer via a gate insulating film. And the first conductivity type emitter. A first main electrode electrically connected to the first conductive layer, a second main electrode electrically connected to the first and second second conductive type emitter layers and the first conductive type impurity layer, When,
Wherein the first second conductivity type emitter layer and the turn-off channel forming layer are adjacent to each other with the first conductivity type base layer interposed therebetween. 2. The semiconductor device according to claim 1, wherein said first and second emitter layers are formed so as to be shallower than said turn-off channel forming layer. 3. The semiconductor device according to claim 1, wherein said first and second emitter layers are formed deeper than said turn-off channel forming layer. 4. The semiconductor device according to claim 1, wherein the gate electrode is formed on a surface of the base layer of the first conductivity type between the first emitter layer of the second conductivity type and the turn-off channel forming layer via the gate insulating film. The semiconductor device according to claim 1, wherein the semiconductor device is formed. 5. The semiconductor device according to claim 1, wherein said first conductivity type emitter layer comprises first and second first conductivity type emitter layers formed in said second conductivity type buffer layer at a distance from each other. A first conductivity type turn-off channel formation layer is formed in contact with an end of the first conductivity type emitter layer, and a second conductivity type impurity is formed in the turn-off channel formation layer in contact with the second first conductivity type emitter layer. A layer is formed, and the first main electrode is electrically connected to the first and second emitter layers of the first conductivity type and the impurity layer of the second conductivity type. 2. The semiconductor device according to claim 1, wherein a gate electrode is formed on a surface of the first conductivity type turn-off channel formation layer in a region sandwiched between the buffer layer and the two conductivity type via a gate insulating film. 6. A high resistance base layer, a first conductivity type base layer formed on one surface of the high resistance base layer, and a second conductivity type selectively formed on the first conductivity type base layer. An emitter layer; a second conductivity type buffer layer formed on the other surface of the high resistance base layer; first and second first and second first conductivity type buffer layers formed on the surface of the second conductivity type buffer layer at an interval from each other. A first conductivity type emitter layer; a first conductivity type turn-off channel formation layer formed on the surface of the buffer layer in contact with the second first conductivity type emitter layer; A second conductivity type impurity layer formed in contact with the first conductivity type emitter layer; a first gate electrode formed on the first conductivity type base layer; and a second conductivity type on a surface of the turn-off channel formation layer. Buffer layer and second conductivity type impurities A second gate electrode formed on a region interposed between the first and second layers through a gate insulating film; and electrically connected to the first and second first conductivity type emitter layers and the second conductivity type impurity layer. And a second main electrode electrically connected to the second conductive type emitter layer, wherein the first first conductive type emitter layer and the turn-off channel forming layer are A semiconductor device adjacent to the second conductivity type buffer layer.