JPS62252168A - Insulated gate type self-turn-off thyristor - Google Patents

Abstract

PURPOSE:To turn ON an MOSFET while maintaining high turning OFF capacity by setting the channel width of a turning OFF MOSFET to sufficiently larger value than that of a turning ON MOSFET. CONSTITUTION:An n-type emitter layer 4 is used as a source region, an n-type base layer 2 is used as a drain region, the surface of a p-type base layer 3 interposed therebetween is used as a channel region CH1 to form a gate electrode 6 through a gate insulating film 5, thereby forming a turning ON n-channel MOSFET. The surface of the layer 3 of a region interposed between an n-type layer 10 to become a drain region and the layer 4 is used as a channel region CH2 to form a gate electrode 12 through a gate insulating film 11, thereby composing a turning OFF n-channel MOSFET. The channel region CH2 of the turning OFF MOSFET is formed along the long side of the layer 4, very large channel width and sufficiently low shortcircuiting resistance are performed to obtain a high turning OFF capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an insulated gate self-turn-off thyristor that performs on/off control using an insulated gate.

(Prior Art) A self-turn-off thigh lifter that performs on-off control using an insulated gate is conventionally known as shown in FIG. 8. This is the n-type base [
122 is formed, and has a pnpn thyristor structure in which an n-type base layer 23 and an n-type emitter layer 24 are sequentially diffused into this n-type base layer 22. n-type emitter layer 2
1 has an anode electrode 32 formed thereon, and an n-type emitter layer 24 has a cathode electrode 27 formed thereon. The surface of the p-type base layer 23 sandwiched between the n-type emitter layer 24 and the n-type base layer 22 is used as a channel region CH1, and a gate electrode 26 is formed thereon via a gate insulator 1!25 to form an n-channel for turn-on. It constitutes MO3FET. Further, an n-type layer 28 is provided in the n-type base layer 23 adjacent to the n-type emitter layer 24, and the surface portion of the p-type substitute layer 23 between this n-type layer 28 and the n-type emitter layer 24 is used as the channel region CH2. A gate electrode 30 is formed thereon via a gate insulating film 29 to constitute a turn-off n-channel MOSFET. The n-type layer 28 is short-circuited to the n-type base layer 23 by an electrode 31.

The operation of this element is as follows. MO3 for turn-on
When a positive voltage is applied to the gate electrode 26 (Gt) of the FET, the channel region CH1 underneath becomes conductive, electrons are injected from the n-type emitter layer 24 to the n-type base layer 22, and corresponding holes are injected into the n-type base layer 22. is injected from the type emitter layer 21, resulting in the thyristor being turned on. When the voltage of the gate electrode 26 is set to zero and a positive voltage is applied to the gate electrode 30 (G2) of the turn-off MOSFET, the n-type emitter 1
124 is short-circuited to the n-type layer 28 via the channel region CH2 under the gate electrode 30, and further short-circuited to the n-type base layer 23 by the electrode 31. This turns off the thyristor.

Figure 8 shows MOSFET for turn-on and M for turn-off.
In this example, both OSFETs are n-channel, but the turn-on MOSFET is n-channel, and the turn-off MOSFET is n-channel.
A structure in which a 3FET is an n-channel is also known. Its structure is shown in FIG.

N-type emitter layer 21. n-type base layer 22. n-type base layer 23. It has a pnpn structure with an n-type emitter layer 24, and seven node electrodes 32. The basic structure including the cathode electrode 27 is the same as in FIG. The difference from FIG. 8 is that there is a p-type layer in the n-type emitter layer 24 (actually, as per oral tradition, a low-concentration n-type layer is diffused and formed continuously with the high-concentration n-type emitter layer outside the high-concentration n-type emitter layer). 33 is formed, and this p-type layer 33 is the cathode electrode 2.
7, the n-type emitter layer 24 is short-circuited, and the p-type layer 33 and n
One gate electrode 26 is continuously formed on the surface of the region sandwiched between the mold base layer 22+\11 with a gate insulating film 25 interposed therebetween. That is, a turn-off n-channel MOSF in which the surface of the n-type emitter layer 24 in the region sandwiched between the p-type layer 33 and the n-type base layer 23 is used as the channel region CH2.
ET and a turn-on n-channel MOSFET whose channel region CH1 is the surface of the p-type base layer 23 between the n-type emitter WI24 and the n-type base 122 are formed using the gate electrode 26 in common.

In this device, when a positive voltage is applied to the gate electrode 26, the n-channel MOSFET becomes conductive and the thyristor is turned on. When a negative voltage is applied to the same gate electrode 26, the p-channel MOSFET becomes conductive and the thyristor is turned off.

In the conventional structure of such a self-turn-off thyristor that performs on-off control using an insulated gate (MOS gate), the turn-off thyristor, which should originally be placed on both sides of the n-type emitter layer, is
One of the OS gates must be replaced with a turn-on MOS gate, and there is a problem in that the turn-off ability is reduced to approximately 1/2 compared to the case where turn-off MOS gates are provided on both sides of the n-type emitter layer. .

That is, in the structure (n-channel MO8GTo) in which the n-channel M″03FET in FIG. 8 is provided for turn-off,
Since only one of the channel regions CHr and CH2 of the MOSFET, which is located on both sides of the n-type emitter layer and accounts for most of the short-circuit resistance, is used for turn-off, the short-circuit resistance is twice that of the case where both sides are used for turn-off. Therefore, the peak turn-off current becomes 1/2. In addition, since there is lateral resistance in the n-type base layer 23 under the n-type emitter layer 24, when the turn-off operation is performed, the portion close to the channel region CHI under the turn-on gate electrode 26 is the slowest (turns off). Become.

Therefore, if the lateral resistance of the n-type base layer 23 is greater than a certain level, turn-off will not be possible.

In the thyristor (p-channel MO8GTo) having a structure in which the n-type emitter layer 24 and the p-type base layer 23 are short-circuited by a p-channel MOSFET shown in FIG. On both sides. However, in this case as well, the channel region CH2 in contact with the turn-on channel region CH1 hardly contributes to the turn-off operation. This is because the surface portion of the n-type base layer 23 that is electrically connected to the p-type layer 33 through the channel region CH2 during turn-off is the channel region CH for turn-on.
I, the resistance of this part is quite large, and almost no short circuit current can flow through it. Therefore, in this structure as well, the portion close to the channel region CH1 turns off the latest, and if the lateral resistance of the n-type base layer 23 is large, it cannot be turned off.

Furthermore, in both the structures shown in FIGS. 8 and 9, the resistance of the p-type base 1lI23 is large. This is because the channel region CH1 is formed on the surface of the p-type base layer, so the impurity concentration cannot be increased to set the threshold value to an appropriate value, and if the diffusion depth of the p-type base layer is increased,
This is because the channel length of the turn-on channel region CHr increases, and the resistance of the turn-on MOSFET increases.

(Problems to be Solved by the Invention) As described above, the conventional insulated gate type self-turn-off thyristor has a problem in that when a turn-on MOS gate is provided, the turn-off ability is significantly reduced.

An object of the present invention is to provide an insulated gate self-turn-off thyristor that solves these problems.

[Structure of the Invention] (Means for Solving the Problems) The insulated gate self-turn-off thyristor according to the present invention has a second conductivity type base layer in contact with the first conductivity type emitter layer, and the second conductivity type base layer is in contact with the first conductivity type emitter layer. A base layer of a first conductivity type and an emitter layer of a second conductivity type are diffused and formed on the surface of the mold base layer, a first main electrode is formed on the emitter layer of the first conductivity type, and a second main electrode is formed on the emitter layer of the second conductivity type. are provided respectively, and the first
The basic structure is that an insulated gate type element for turn-off and an insulated gate type element for turn-on are provided on the surface of a conductive base layer. In the present invention, in such a structure, in order to maintain high turn-off capability, the channel width of the turn-off insulated gate type element is made longer than that of the turn-on insulated gate type element. The easiest way to realize this structure is to form the second conductivity type emitter layer into an elongated rectangular shape (
(including a stripe shape), forming a channel of an insulated gate type element for turn-on along the short side of the rectangular region, and forming a channel of an insulated gate type element for turn-off along the long side of the rectangular region. It is.

The plurality of rectangular second conductivity type emitter layers may not be completely independent, but may be connected to each other on their short sides, and in this case, an insulated gate type element for turn-on is also connected to the short sides of the rectangular emitter layers. Just form a channel.

(Function) In the device structure of the present invention, an insulated gate type element for turn-on is formed only in a small part of the end of the second conductivity type emitter layer, and an insulated gate type element for turn-off is formed in most of the remaining part. Therefore, high turn-off ability can be obtained. Especially in the case where the second conductivity type emitter layer has a striped pattern, even if an insulated gate element for turn-on is not provided, it is normal that an insulated gate element for turn-off is not formed on the short side of the emitter layer. If an insulated gate type element for turn-on is formed in this portion, the turn-off ability is almost the same as that of the conventional device.

Regarding the turn-on operation, once carrier injection is started in a small region of the second conductivity type emitter layer by the turn-on insulated gate element, the turn-on region quickly spreads to the entire second conductivity type emitter layer due to plasma spread. . Therefore, it is sufficient if the insulated gate type element for turn-on is formed only in a small portion. If a particularly large current increase rate is required, the second conductivity type emitter layer of the stripe pattern is cut into rectangular regions of appropriate length, and an insulated gate for turn-on is placed on the short side of each rectangular region. What is necessary is to form a mold element.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. In all of the following examples, p type is used as the first conductivity type, and n type is used as the second conductivity type.

FIG. 1(a) is a plan view showing the element structure of the first embodiment, and FIG. 1(b) and (C) are respectively A-A-
, is a BB cross-sectional view. n in contact with n-type emitter layer 1
A type base layer 2 is formed, and an n-type base layer 3 and an n-type emitter layer 4 are successively diffused into this n-type base layer 2 to form a pnpn structure. An anode electrode (first main electrode) 9 is formed on the n-type emitter layer 1, and a cathode electrode (second main electrode) 8 is formed on the n-type emitter layer 4. The n-type emitter layer 4 is divided into a plurality of rectangular regions as shown in FIG. 1(a), and the cathode electrode 1f1B is in low-resistance contact with each of these n-type emitter layers 4.

Each n-type emitter 114 has one short side overlapped with the end of the n-type base layer 3 (actually, as shown in FIG. 1(b), separately from the main body of the p-type base layer). The surface of the n-type base layer 3 sandwiched between the n-type emitter layer 4 as a source region and the n-type base JI2 as a drain region is defined as the channel region CH1, and a gate insulating layer g15 is formed on the channel region CH1.
A gate electrode 6 is formed through the gate electrode 6 to constitute a turn-on n-channel MOSFET. As shown in FIG. 1(a), this turn-on gate electrode 6 is disposed continuously along the side of the n-type base layer 3 facing the striped opening of the n-type base 1li2, and type emitter 1
A channel region CHt of the MO3FET for turn-on is formed on one short side of the transistor 14.

In the p-type base layer 3, an n-type layer 10 serving as a drain region is formed adjacent to both long sides of each n-type emitter layer 4, and a region sandwiched between the n-type layer 10 and the n-type emitter 14 A gate electrode 12 is formed on the surface of the p-type base layer as a channel region CH2 via a gate insulator 111,
A turn-off n-channel MO5FET is configured. This gate electrode 12 is formed continuously in a comb-like shape as shown in FIG. 1(a), and a channel region CH2 is formed along the long side of each n-type emitter layer 4. There is. A drain electrode 13 is formed on the n-type layer 10 to short-circuit between it and the p-type heath layer 3.

In this embodiment, as is clear from FIG. 1(a), the gate electrode 6 of the turn-on MOSFET and the gate electrode 12 of the turn-off MOSFET are separated from each other and formed separately. . The cathode electrode 8 is connected to an interlayer insulating film 7 so as to partially overlap these gate electrodes.
is formed through.

A specific example of the manufacturing process for this element will be described next.

First, the specific resistance of the n-type base 112 is 120 to 150Ω.
- Prepare an n-type S1 substrate α with a thickness of 350 μm, and form an n-type emitter layer 1 with a thickness of about 30 μm by diffusing p-type impurities at a high concentration. Next, p-type consumables are selectively diffused onto the opposite surface of the substrate to form an n-type base layer 3. Thereafter, approximately 1000 gate insulators WA5.11 are formed by thermal oxidation, and 5000 polycrystalline silicon films are deposited and patterned to form gate electrodes 6 and 12. Next, using the gate electrode 6 as part of a mask, n
A continuous, low concentration, shallow p-type layer is formed at the end of the mold base layer 3. In the figure, this low concentration p-type layer is also shown as part of the n-type base layer 3. After this, the n-type emitter layer 4 and the
A mold layer 10 is simultaneously formed by diffusion. In order to reduce the resistance of the n-type emitter layer, a high-concentration n-type layer may be formed by diffusion before the low-concentration p-type layer so as not to reach the channel region CHI. Then, a glabellar insulating film 7 is formed on the cathode side surface, a contact hole is made in this to form a cathode electrode 8 and a short-circuit source electrode wA13, and a 7-node electrode 9 is formed on the back surface of the substrate to complete the process.

The operation of this element is as follows. The turn-on operation is
This is done by applying a positive voltage to the gate electrode 6.

As a result, the channel region CH1 becomes conductive, electrons are injected from the n-type emitter 114 to the n-type base layer 2, and corresponding holes are injected from the n-type emitter 111, and as a result, the vicinity of the channel region CH1 is first turned on. . The turn-on region quickly spreads over the entire n-type emitter layer 4 due to plasma spread, and the entire device turns on. At turn-off, the voltage of the gate electrode 6 is set to zero, and a positive voltage is applied to the gate electrode 12. As a result, the channel region CH2 becomes conductive, and the n-type emitter 114 passes through the channel region CH2 to the n-type layer 10. Short circuit electrode 13
It is short-circuited to the n-type base 113 via.

As described above, in this embodiment, the turn-on operation is performed by the n-channel MOSFET formed on the short side of each rectangular n-type emitter layer 4.

The principle is the same as the conventional MO8GTO. The turn-off MOSFET has a channel region formed along the long side of each n-type emitter layer, has a very large channel width, and achieves a sufficiently low short circuit resistance. Therefore, a turn-off capability approximately twice as high as that of the conventional MO8GTO equipped with a turn-on MOSFET can be obtained.

This embodiment also has advantages in terms of manufacturing process.

That is, by forming the p-type layer portion for forming the channel region CH1 of the turn-on MOSFET separately from the p-type base layer main body, the gate electrode 5 of the turn-on MOSFET and the gate electrode 12 of the turn-off MOSFET are formed separately.
It becomes possible to simultaneously form . If a low concentration p-type layer is not formed, the turn-on M
A gate electrode 5 of the OSFET is formed, a p-type base layer is formed using this as a mask, and then a turn-off MOS is formed.
This is because it is necessary to take the step of forming the gate electrode 12 of the FET.

FIG. 2(a) is a plan view showing the element structure of the second embodiment, and FIGS. 2(b) and 2(c) are sectional views taken along the line AA' and 8-8. In this example, the turn-on MOSFET
is an n-channel, and the turn-off MOSFET is an n-channel, and the gate electrode of both is made common. Since the basic structure of the thyristor is the same as that in the previous embodiment, parts corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. 1, and detailed description thereof will be omitted. In this embodiment as well, a plurality of n-type emitters 114 are arranged in a rectangular shape. Then, the end of the p-type base layer 3 on one short side of each n-type emitter layer 4 is used as a channel region CHr, and a gate insulating film 5 is formed on this.
A turn-on n-channel MOSFET is formed by forming a gate electrode 6 via the gate electrode 6. In addition, p-type W, which becomes a source region, is provided in the n-type emitter layer 4 on both sides along its long side.
! 114 is diffused and formed, and the surface of the n-type emitter layer 4 in the region sandwiched between this and the p-type base layer 3 is used as a channel region CH.
2, a gate electrode 1 is placed on top of this via a gate insulating film.
2 to form a p-channel MOSFET for turn-off.
is configured. Here, n-channel M for turn-on
The gate electrode 6 of the O3FET and the gate electrode 12 of the p-channel MO8FET for turn-off are shown in FIG. 2(a).
As is clear from the figure, it is integrally formed in a lattice shape. A cathode electrode 8 is formed on the entire surface so as to be in contact with each n-type emitter layer 4, and this is a p-channel MOSFE.
The n-type layer 14 and the n-type emitter 114 are the source region of T.
It also serves as an electrode to short-circuit the wire.

Note that the channel region CHI of the turn-on MOSFET
The part where is formed is the end of the p-type base layer 3,
The actual manufacturing process is the same as in the previous embodiment, and as shown in FIG. 2(b).
As can be seen from the figure, a shallowly diffused low concentration p-type layer is used separately from the main body of the p-type base layer. M for turn-off
The same applies to the part forming the channel region CH2 of the OSFET, and in practice, as understood from FIG. 2(C), n
A shallow, low concentration n-type layer is used which is formed by diffusion separately from the main body of the emitter layer. The low concentration p-type layer and the low concentration n-type layer in which these channel regions are formed are connected to the gate electrode 6.
．． After forming gate electrode 12, impurities are diffused using this as a mask, and n-type layer 14, which becomes the source region of the p-channel MOSFET, is also formed using gate electrode 12 as part of the mask. In the figure, the turn-on n-channel MOSFET has each n-type emitter layer 4.
Although it is formed along one short side, it can also be formed along the other short side.

The turn-on operation of this device is the same as the device of the previous embodiment. That is, by applying a positive voltage to the gate electrodes 6 and 12, the turn-on n-channel MO5FET is turned on.
The vicinity of the channel region CHt is turned on, and the turn-on region spreads over the entire n-type emitch layer due to plasma spread, and the thyristor is turned on. At turn-off, a negative voltage is applied to the gate electrode 6.12. As a result, the channel region CH2 of the turn-off n-channel MOS FET becomes conductive, the n-type emitter layer 4 and the p-type base 1I3flt are short-circuited, and the device is turned off.

In this embodiment as well, the MO3FET for turn-off is formed along the long side of the elongated rectangular n-type emitter layer, and the MO3FET for turn-on is formed on the short side, so that high turn-off ability is achieved as in the previous embodiment. MO8G with
TO is obtained.

FIG. 3 is a plan view showing the element structure of the third embodiment,
Figures (b) and (c) are A-A= and B- of (a), respectively.
8- is a sectional view. In this example.

are MOSFET for turn-on, MOSF for turn-off
Both ET uses n-channel, but MO for turn-on
An amplification gate structure is introduced in the SFET part. The difference from the embodiment shown in FIG.
is continuously formed along the short side of the p-type base layer 3. And this n-type layer 15 and n-type base Ji2
The surface of the p-type base layer 3 sandwiched between is used as a channel region CHs, and a gate electrode 6 is formed thereon via a gate insulator 1gl5, thereby forming a turn-on n-channel MO5FET. The end portion of the p-type base layer 3 is actually a low concentration p-type layer that is shallowly diffused and formed separately from the main body portion, as in the previous embodiments.

Then, an amplification gate electrode 16 is formed which contacts the n-type layer 15 and the p-type base layer 3 at the same time.

In the turn-off n-channel MO5FET, an n-type layer 10 serving as a drain region is formed adjacent to both long sides of a rectangular n-type emitter layer 4, as in the embodiment shown in FIG. The surface of the p-type base layer 3 between the and n-type emitter layer 4 is used as a channel region CH2, and the gate insulating layer 1 is
A gate electrode 12 is formed through the gate electrode 111.

The gate electrode 12 of this turn-off MOSFET is continuously formed in the shape of a comb, and the cathode electrode 8 is disposed in contact with each n-type emitter layer 4 so as to mesh with the comb. The amplification gate N pole 16 is also arranged so as to mesh with the comb teeth of the gate electrode 12, and is used as the yIi electrode between the n-type layer 1o and the p-type base layer 3.

The operation of this device is basically similar to the device of FIG.

MOSF for turn-on by applying a positive voltage to the gate electrode 6
By making the channel region tiic)-1t of ET conductive, the device is turned on. Also, MOS for turn-off
By applying a positive voltage to the FET gate electrode 12 and making the channel region CH2 conductive, the device is turned off. Then, as in each of the previous embodiments, a turn-off MOSFE
Since the width of the channel region WiCH 20 of T is sufficiently large, a high turn-off ability can be obtained. This embodiment has improved turn-on characteristics compared to the device of FIG. By using the source electrode of the turn-on MOSFET as the cathode electrode 8 and another amplification gate electrode 16, and integrating this with the short-circuit electrode of the turn-off MOSFET as shown in FIG. 3(a), the n-type emitter layer 4 is This is because the gate current is supplied not only from the short side but also from the long side, and faster turn-on of the entire n-type emitter layer 4 is realized.

As described above, in the device of this example, the turn-on ability is greatly improved while maintaining the high turn-off ability.

FIG. 4(a) is a plan view showing the element structure of the fourth embodiment, and FIG. is a turn-on MOSFET
This is a combination of the embodiment of FIG. 2 in which the MOSFET for turn-on is an n-channel and the MOSFET for turn-off is a p-channel, and the embodiment of FIG. 3 in which an amplification gate structure is introduced in the MOSFET for turn-on. Therefore, parts corresponding to those in FIGS. 2 and 3 are designated by the same reference numerals, and detailed description thereof will be omitted. In this case, as in the embodiment shown in FIG.
A turn-on MOSFET can be formed along both short sides of the transistor.

The turn-on and turn-off operations of this device are similar to those of the device shown in FIG. 2, and a high turn-off ability and U-turn-on ability can be obtained.

FIG. 5(a) is a plan view showing the element structure of the fifth embodiment, and FIG. , CC" sectional view. This embodiment is a modification of the device of the embodiment shown in FIG. 1. In this embodiment, a plurality of rectangular n-type emitter layers 4 are formed independently The structure is such that they are connected in common on one short side.Also, along with this, a turn-off n
n-type layer 10 that becomes the drain region of the channel MOSFET
It is formed in a U-shape, and its gate electrode 12 is also formed to form a closed circuit so as to surround the shorted drain electrode 13. Therefore, the CC cross section in FIG. 5(a), that is, FIG. 5<(
The structure of j) is similar to the conventional one shown in FIG.

In the device of this example, an n-channel MO3 for turn-on is used.
Since the channel region CHt of the FET is also formed at the connecting portion of the n-type emitter 1114, the channel width is large, and the initial turn-on region becomes correspondingly large, so even when the Il current rise rate is large, turn-on can be performed safely. .

Furthermore, since the plurality of n-type emitter layers 4 are not completely independent, the entire device operates uniformly. Since the channel region CH2 of the turn-off n-channel MOSFET is formed in a U-shape with a large width between the n-type emitter layers connected to each other, the turn-off ability is as large as in each of the previous embodiments. Become.

The sixth factor is the turn-off MOSF of the element of the sixth embodiment.
It is a top view which shows the 27th part. This is a modification of the turn-off MOSF 27 section of the embodiment shown in FIG. That is, this embodiment differs from FIG. 2 in that the channel region CH2 of the turn-off MOSFET formed along the long side of the n-type emitter layer 4 has a zigzag pattern.

According to this embodiment, the channel width of the MO8FET for turn-off can be made larger, thereby further reducing the short-circuit resistance, and higher turn-off capability can be obtained. Figures 1 and 3.

A similar modification can be made to the embodiment shown in FIG. 4, and a high turn-off capability can also be obtained.

FIG. 7(a) is a plan view showing the element of the seventh embodiment, and FIG. 7(b) is a cross-sectional view taken along the line A-A''. On the contrary, a basic structure is adopted in which the n-type emitter layer 4 is continuously formed in a lattice shape, and a plurality of turn-on and turn-off gate electrodes are separated from each other and arranged in an array. For example, in such a structure, as shown in FIG. 7(a), a plurality of turn-off MOSFETs (
7) MOS FET(7)'7''-upper electrode 12 (
G2) is placed. Therefore, for the entire device, the channel width of the turn-off MOSFET is the same as that of the turn-on MOSFET.
It is sufficiently large compared to that of SFET.

In this embodiment, the turn-on MOSFET is n-channel, and the turn-off MOSFET is n-channel, and the structure thereof is the same as that of the embodiment shown in FIG.

This embodiment also makes it possible to maintain high turn-off capability while providing a turn-on MOSFET.

The present invention is not limited to the embodiments described above, and can be implemented with various modifications.

For example, in each of the above embodiments, a case has been described in which the MOS gate is electrically driven from the outside, but a pnp transistor consisting of an n-type emitter layer, an n-type base layer, and an n-type base layer is driven with light. M for turning on its collector current
When using a trigger method in which the turn-on MOSFET is turned on by supplying the voltage to the gate electrode of the OSFET, or when the collector current is supplied to the turn-off MOSFET,
The present invention is also effective when using a light quenching method in which a turn-off MOSFET is turned on by supplying light to the gate electrode of the SFET.

[Effects of the Invention] As described above, according to the present invention, the turn-off MOS
By setting the channel width of the FET to be sufficiently larger than that of the MO3FET for turn-on, it is possible to realize a MO8GTO that allows turn-on by a MOSFET while maintaining high turn-off capability.

[Brief explanation of drawings]

FIG. 1 (a>(b) and (c) is a plan view showing the element structure of the first embodiment of the present invention, and its AA-, B-8' sectional view;
FIGS. 2(a), 2(b), and 2(c) are plan views showing the device structure of the second embodiment and their A-A-. 3(a), (b), and (c) are plan views showing the element structure of the third embodiment, and its A-/M and B-B-
4(a), (b), and (c) are a plan view showing the element structure of the fourth embodiment, and its AA", B-8" sectional views;
FIGS. 5(a), (b), (c), and (d) are plan views showing the element structure of the fifth embodiment and their A-A", B-8=, C-C"
6 is a plan view showing the device structure of the sixth embodiment, and FIGS. 7(a) and 7(b) are plan views and AA cross-sectional views showing the device structure of the seventh embodiment. , FIG. 8, and FIG. 9 are cross-sectional views showing a conventional element structure. 1... n-type emitter layer, 2... n-type base layer, 3...
... n-type base layer, 4... n-type emitter layer, 5...
Gate insulating film, 6... gate electrode (for turn-on),
7... Interlayer insulating film, 8... Cathode electrode, 9...
Anode electrode, 10... n-type layer (drain@region), 1
DESCRIPTION OF SYMBOLS 1... Gate insulating film, 12... Gate electrode (for turn-off), 13... Short circuit drain electrode, 14... p
Type layer (source region), 15...n type layer (source region)
, 16... Amplification gate electrode, Cl-1+... Channel region of MO3FET for turn-on, CH2... Channel region of MOSFET for turn-off. Applicant's agent Patent attorney Takehiko Suzue (a) Figure 1 (1) Figure 1 (2) (a) Figure 2 (1) Figure 2 (b) (C) Figure 2 (2) (a) Figure 3 Figure (1) So (b) So (c) Figure 3 (2) (a) Figure 4 (1) Figure 4 (2) (a) v, Figure 5 (1) Figure 5 (2) ( d) Figure 5 (3)

Claims (9)

[Claims] (1) having a second conductivity type base layer in contact with the first conductivity type emitter layer, the first conductivity type base layer and the second conductivity type emitter layer being diffused and formed on the surface of the second conductivity type base layer;
It has a thyristor structure in which a first main electrode is formed in the first conductivity type emitter layer and a second main electrode is formed in the second conductivity type emitter layer, and an insulated gate for turn-off is provided on the surface of the first conductivity type base layer. In the insulated gate self-turn-off thyristor in which a type element and a turn-on insulated gate type element are formed, the channel width of the turn-off insulated gate type element is set to be longer than that of the turn-on insulated gate type element. Insulated gate self-turn-off thyristor. (2) The second conductivity type emitter layer is divided into a plurality of rectangular regions, and the channel of the turn-off insulated gate type element is formed along the long side of each rectangular region, and the turn-on 2. The insulated gate self-turn-off thyristor according to claim 1, wherein a channel of the insulated gate device is formed along a short side of each rectangular region. (3) The second conductivity type emitter layer is divided into a plurality of rectangular regions in which adjacent ones are connected at one short side, and the channel of the turn-off insulated gate type element is arranged in each of the rectangular regions. The insulated gate type device according to claim 1, wherein the insulated gate type device is formed along a long side of a rectangular region, and the channel of the turn-on insulated gate device is formed along a connecting portion of each of the rectangular regions. turn-off thyristor. (4) The turn-on insulated gate element
A second conductive channel MOSFET configured by using a conductive type emitter layer as a source region, the second conductive type base layer as a drain region, and providing an insulated gate on the surface of the first conductive type base layer sandwiched between these regions. An insulated gate self-turn-off thyristor according to claim 1. (5) The turn-on insulated gate type element includes the first
It has a second conductivity type source region formed separately from the second conductivity type emitter layer in the conductivity type base layer, and has a source electrode that shorts between the source region and the second conductivity type base layer, and The insulated gate according to claim 1, which is a second conductive channel MOSFET configured by providing an insulated gate on the surface of the first conductive type base layer sandwiched between the source region and the second conductive type base layer. Type self-turn-off thyristor. (6) The turn-off insulated gate type element includes the second
A conductivity type emitter layer is used as a source region, and a second conductivity type drain region is formed in the first conductivity type base layer at a predetermined distance from the source region, and between the drain region and the first conductivity type base layer. a second conductive type base layer having a drain electrode short-circuiting the source and drain regions, and an insulated gate provided on the surface of the first conductivity type base layer sandwiched between the source and drain regions.
The insulated gate self-turn-off thyristor according to claim 1, which is a conductive channel MOSFET. (7) The turn-off insulated gate element
a first conductivity type source region formed within the conductivity type emitter layer and short-circuited to the second conductivity type emitter layer by the second main electrode; the first conductivity type base layer serving as a drain region; 2. The insulated gate self-turn-off thyristor according to claim 1, which is a first conductive channel MOSFET configured by providing an insulated gate on the surface of said second conductive type emitter layer sandwiched between both regions. (8) The insulated gate type device according to claim 1, wherein both the turn-on insulated gate type device and the turn-off insulated gate type device are second conductive channels, and the gate electrodes of both devices are formed separately. turn-off thyristor. (9) The turn-on insulated gate element is a second conductive channel, the turn-off insulated gate element is a first conductive channel, and the gate electrodes of both elements are continuously formed integrally. The insulated gate self-turn-off thyristor according to item 1.