JP2938028B1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

Kind Code: A1 A semiconductor device capable of reducing the contact resistance between a resistance element and a metal wiring formed thereover without increasing the number of steps, and preventing occurrence of a defect due to variation in resistance. Provision of manufacturing method. When forming a gate electrode of a transistor, a member made of the same material as the gate electrode, that is, a dummy electrode is provided in a predetermined region, so that the transistor is formed via a first interlayer insulating film. The end side of the polycrystalline silicon film 208 is pushed up to the substrate surface side. Further, by polishing the second interlayer insulating film 209 formed thereon, the end of the polycrystalline silicon film is exposed, and the metal wiring 21 is removed.
2 is connected without passing through the contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a resistance element made of a polycrystalline silicon film and connecting to a metal wiring provided thereover and a method of manufacturing the same. .

[0002]

2. Description of the Related Art Conventionally, in order to form an analog circuit or the like using a resistive element made of a polycrystalline silicon film, a polycrystalline silicon film whose electric conductivity is adjusted by injecting impurities and an insulating film deposited on the polycrystalline silicon film are formed. A method is used in which a metal wiring provided on a film is connected via a contact hole provided in an insulating film.

[0003] A conventional method will be described below with reference to the drawings. FIG. 4 is a diagram for schematically explaining the structure of a conventional semiconductor device. FIG. 4 (a) is a view of B in FIG. 4 (b).
FIG. 4B is a cross-sectional view taken along the line B ′, and FIG. 4B and FIG.
It is a top view.

Referring to FIG. 4, a conventional semiconductor device includes an impurity diffusion layer 306 formed on a semiconductor substrate 301 with a gate electrode 305 interposed therebetween, a field oxide film 302 for isolating elements outside the impurity diffusion layer 306, And a first interlayer insulating film 307 formed so as to cover.

[0005] Furthermore, a polycrystalline silicon film 308 serving as a resistance element and a second interlayer insulating film 309 are formed thereover.
In the interlayer insulating film 307 and the second interlayer insulating film 309, contact holes 311 penetrating the impurity diffusion layer 306 or the polycrystalline silicon film 308, respectively, are formed.

[0006] A metal wiring is provided inside the contact hole 311 and above the second interlayer insulating film 309, and is electrically connected to the impurity diffusion layer 306 or the polycrystalline silicon film 308, respectively. As described above, the polysilicon film 308 serving as a resistance element and the metal wiring 312 are connected via the contact hole 311 formed in the second interlayer insulating film 309.

[0007]

In such a conventional semiconductor device, since the metal wiring 312 and the polycrystalline silicon film are connected only at the opening of the contact hole 311, the contact resistance increases. Manufacturing variations are likely to occur.

To solve this problem, as shown in FIG. 4B, the number of contact holes is increased,
As shown in (c), there is a method of increasing the contact hole, but with the increase in the degree of integration and miniaturization of the semiconductor device, it is difficult to reduce the contact resistance by such a method. I have.

Here, there is disclosed a method of reducing the contact resistance of the connection between the gate electrode and the metal wiring, instead of the connection between the resistance element and the metal wiring described above (Japanese Patent Laid-Open No. 9-1997).
36358).

However, in this method, in order to directly connect the gate electrode and the metal wiring, (a) a step of filling the space between the gate electrodes with an insulating film, (b) flattening by etching or the like, and cueing of the gate electrode And (c) a step of patterning the metal wiring pattern separately from the gate electrode pattern.

In a semiconductor device such as a memory element, reduction of the number of steps is an important theme along with improvement of reliability. According to this method, reduction in contact resistance between a polycrystalline silicon film and a metal wiring is performed without increasing the number of steps. Can not be planned.

The present invention has been made in view of the above problems, and a main object of the present invention is to reduce the contact resistance between a resistance element and a metal wiring formed thereover without increasing the number of steps. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can prevent occurrence of a defect due to variation in resistance.

[0013]

In order to achieve the above object, a semiconductor device according to a first aspect of the present invention comprises a transistor having a gate electrode and an impurity diffusion layer on a semiconductor substrate, and a conductive member. A resistive element, wherein a member made of the same material as the gate electrode is provided in a predetermined region together with the formation of the gate electrode, and the member is used to form a resistive element on both sides of the conductive element. But,
The cross-sectional shape is a shape pushed up to the substrate surface side, and connection regions are provided at both ends of the resistance element.
Is what it is.

In a second aspect of the semiconductor device according to the present invention, a transistor having a gate electrode and an impurity diffusion layer on a semiconductor substrate, a resistance element formed of a conductive member, and an interlayer insulating film are provided. And a metal wiring provided, wherein a member made of the same material as the gate electrode is provided in a predetermined region together with the formation of the gate electrode, and the member is formed of the conductive member. In the cross-sectional shape of the resistive element, the region pushed up to the substrate surface side has an exposed connection over the entire width of the resistive element.
A region may be formed and connected to the metal wiring.

According to a third aspect of the present invention, there is provided a process for forming a transistor including a gate electrode and an impurity diffusion layer on a semiconductor substrate; Forming a metal wiring, comprising: (a) a member made of the same material as the gate electrode in a predetermined region when forming the gate electrode; In the width direction
A portion large enough to cover at least the entire width of the resistance element.
The semiconductor substrate via a first interlayer insulating film formed so as to cover the gate electrode and a member made of the same material as the remaining gate electrode. when viewed from the normal direction, and forming a resistive element made of the conductive member so that the both ends overlap on the member consisting of the remaining gates electrodes of the same material, (c) said conductive a second interlayer insulating film formed to cover the resistive element composed of members, by a CMP method, and etching to both ends of the conductive member is exposed, both ends of the conductive member exposed (d) (E) forming metal wires on both ends of the silicidized conductive member.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION In a preferred embodiment of the semiconductor device according to the present invention, when forming a gate electrode of a transistor (205 in FIG. 3A), a gate electrode is formed in a predetermined region. By providing a member made of the same material as the material to be formed, that is, a dummy electrode (205a in FIG. 3A), the first interlayer insulating film (207 in FIG. 3A) is provided.
The polycrystalline silicon film formed through the film (2 in FIG. 3A)
08) is pushed up to the substrate surface side, and the second interlayer insulating film further formed thereon (209 in FIG. 3A)
The end of the polycrystalline silicon film exposed by polishing or etching is connected to a metal wiring (212 in FIG. 3A) without passing through a contact hole.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIGS. 1 to 3 are views for explaining a semiconductor device according to one embodiment of the present invention. 1 and 2 are cross-sectional views schematically illustrating a manufacturing process of the semiconductor device. FIG. 3A is a cross-sectional view of the semiconductor device taken along line AA ′ in FIG. FIG. 3B is a plan view of the semiconductor device.

The manufacturing process of this embodiment will be described with reference to FIGS. First, as shown in FIG. 1A, a field oxide film 102 serving as an element isolation region for forming a MOS transistor is formed on a semiconductor substrate 101 by using a known photolithography technique, and a gate insulating film of the MOS transistor is formed. 103 and a gate electrode film 104 are formed.

Next, as shown in FIG. 1B, the gate electrode film 104 is patterned using a known photolithography technique to form a gate electrode 105. At this time, M
Simultaneously with the formation of the gate electrode 105 of the OS transistor,
In a later step, patterning is performed so that the gate electrode film 104 remains even in a region to be a connection portion between the resistance element and the metal wiring, and a dummy electrode 105a made of the same material as the gate electrode 105 is formed.

Subsequently, as shown in FIG. 1C, a first interlayer insulating film 107 is deposited, and a polycrystalline silicon film 108 serving as a resistance element is grown thereon. The polycrystalline silicon film 108 is processed by implanting impurity ions by ion implantation or the like so as to obtain a desired resistance value, and then patterned by a known photolithography technique.

Next, as shown in FIG. 1D, the semiconductor substrate 1
Then, a second interlayer insulating film 109 is deposited on the entire surface of the substrate 01. At this time, the thickness of the second interlayer insulating film 109 is adjusted so as to be thicker than the upper surface of the polycrystalline silicon film 108 even in the depressed portion.

Thereafter, as shown in FIG.
P (Chemical Mechanical Pol)
The second interlayer insulating film 109 is flattened by using an etching technique. This flattening is performed until the end of the polycrystalline silicon film 108 is exposed, so that sufficient contact with the metal wiring formed thereover can be obtained.

Next, as shown in FIG. 2 (f), the exposed portion of the polycrystalline silicon film 108 is silicided with a high melting point metal to reduce the resistance and form a silicide layer 110.

Finally, as shown in FIG. 2G, a contact hole 111 penetrating through the impurity diffusion layer 106 is provided, a metal is deposited on the entire surface, and patterning is performed by using a known photolithography technique to form a metal wiring. Form 112. At this time, the polycrystalline silicon film 108 becomes the silicide layer 110
Is connected directly to the metal wiring 112 via the second interlayer insulating film 109, so that there is no need to form a contact hole in the second interlayer insulating film 109, and a connection with low contact resistance can be made.

The structure of the present embodiment will be described with reference to FIG. 3. The semiconductor device according to the present embodiment has a resistance element region 213 made of a polycrystalline silicon film 208. Since the regions located at both ends of the resistive element region 213 are pushed up to the substrate surface side by dummy electrodes formed thereunder, the surface is exposed by planarization by CMP, It is in contact with a metal wiring 212 formed thereover via a silicide layer 210.

[0027]

As described above, according to the present invention,
By providing a dummy electrode made of the same material as the gate electrode when forming the gate electrode, the polycrystalline silicon film serving as a resistance element can be directly connected to the metal wiring, and the contact resistance can be reduced without increasing the number of steps. This has the effect of preventing the occurrence of defects due to variations.

The reason is as follows. That is, when forming the gate electrode 205, dummy electrodes are provided in regions located at both ends of the polycrystalline silicon film serving as a resistance element,
When a polycrystalline silicon film is formed thereover via a first interlayer insulating film, both ends of the polycrystalline silicon film are pushed up to the substrate surface side by the thickness of the dummy electrode.

Therefore, after further depositing the second interlayer insulating film, the CMP
When planarization is performed by the method, only both end portions of the polycrystalline silicon film can be exposed on the surface, and can be directly connected to a metal wiring formed thereover.

Further, the exposed portions of the surfaces at both ends of the polycrystalline silicon film are silicided with a high melting point metal to form a silicide layer, so that the contact resistance can be further reduced. This is because it is possible to prevent the occurrence of a defect due to a variation in resistance between the wiring and the metal wiring.

As described above, according to the present invention, there is no need to add a special step as compared with the conventional method, and therefore, the contact resistance between the resistance element and the metal wiring can be reduced without increasing the number of steps. In addition, since there is no need to provide a contact hole, the connection region can be formed in a self-aligned manner, so that the pattern of the resistive element can be reduced and the semiconductor device can be miniaturized. Some of them have an excellent effect that they can be produced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing process of one embodiment of the present invention in the order of processes.

FIG. 2 is a cross-sectional view for describing a manufacturing process of one embodiment of the present invention in the order of processes.

FIG. 3 is a diagram for explaining a structure of a semiconductor device according to one embodiment of the present invention, and FIG.
FIG. 3B is a cross-sectional view taken along line -A ′, and FIG. 3B is a plan view.

4A and 4B are views for explaining the structure of a conventional semiconductor device. FIG. 4A is a cross-sectional view taken along line BB ′ of FIG. 4B, and FIG. FIG. 4C is a plan view.

[Explanation of symbols]

 101, 201, 301 Semiconductor substrate 102, 202, 302 Field oxide film 103, 203, 303 Gate insulating film 104 Gate electrode film 105, 205, 305 Gate electrode 105a, 205a Dummy electrode 106, 206, 306 Impurity diffusion layer 107, 207 , 307 First interlayer insulating film 108, 208, 308 Polycrystalline silicon film 109, 209, 309 Second interlayer insulating film 110, 210 Silicide layer 111, 211, 311 Contact hole 112, 212, 312 Metal wiring 213 Resistive element region 214 Contact silicide area

Claims (6)

(57) [Claims] 1. A semiconductor device comprising: a transistor having a gate electrode and an impurity diffusion layer on a semiconductor substrate; and a resistance element made of a conductive member, wherein the gate electrode is formed in a predetermined region together with the formation of the gate electrode. A member made of the same material as the electrode is provided, and
Both sides of the resistance element made of the conductive member, in its cross section, is shaped pushed up on the substrate surface, the
A semiconductor device, wherein connection regions are provided at both ends of a resistance element . 2. A semiconductor device comprising: a transistor having a gate electrode and an impurity diffusion layer on a semiconductor substrate; a resistance element formed of a conductive member; and a metal wiring provided via an interlayer insulating film. Along with the formation of the gate electrode, a member made of the same material as the gate electrode is provided in a predetermined region,
In the cross-sectional shape of the resistance element made of the conductive member, a region pushed up to the substrate surface side is the resistance element.
A semiconductor device , wherein an exposed connection region is formed over the entire width of the device and is connected to the metal wiring. 3. A method for manufacturing a semiconductor device, comprising: a step of forming a transistor including a gate electrode and an impurity diffusion layer on a semiconductor substrate; and a step of forming a resistor element made of a conductive member. upon formation of the gate electrode, wherein when viewed from the normal direction of the semiconductor substrate, Ri Do from the gate electrode of the same material in the area located on the edge side of the resistive element made of the conductive member, prior to
In the width direction of the resistance element, at least the resistance element
A method of manufacturing a semiconductor device, comprising: leaving a member large enough to cover the entire width . 4. A method for manufacturing a semiconductor device, comprising: a step of forming a transistor including a gate electrode and an impurity diffusion layer on a semiconductor substrate; and a step of forming a resistive element formed of a conductive member. a) a step of leaving a member made of the same material as the gate electrode in a predetermined region when forming the gate electrode; and (b) a member made of the same material as the gate electrode and the remaining gate electrode. And the second formed to cover
A resistance element made of the conductive member such that an end thereof overlaps a member made of the same material as the remaining gate electrode when viewed from a normal direction of the semiconductor substrate via one interlayer insulating film; And (c) forming so as to cover the resistance element made of the conductive member.
The formed second interlayer insulating film is subjected to the conductive method by a CMP method.
Etching the substrate until both ends of the member are exposed . 5. A member made of the same material as the gate electrode
Is at least the resistance in the width direction of the resistance element.
A contractor sized to cover the entire width of the element.
A method for manufacturing a semiconductor device according to claim 4. 6. A gate electrode and impurity diffusion on a semiconductor substrate.
Forming a transistor including a layer and a conductive member
Forming a metal wiring via a resistor element consisting of
A step of a method for manufacturing a semiconductor device having, upon formation of (a) the gate electrode, in a predetermined region, before
A member made of the same material as the gate electrode,
In the width direction of the element, at least the entire width of the resistance element
Leaving a member of a size to cover; (b) the gate electrode; and the remaining gate electrode.
And a member made of the same material.
Through a first interlayer insulating film, in a direction normal to the semiconductor substrate;
From the same material as the remaining gate electrode.
The conductive member so that both ends overlap the member
Forming a resistive element comprising the conductive member ; and (c) forming a resistive element comprising the conductive member.
The formed second interlayer insulating film is subjected to the conductive method by a CMP method.
Etching until both ends of the member are exposed; and (d) silicidizing both ends of the exposed conductive member.
A step of processing, the gold on both sides of the conductive member in the silicide (e)
Forming a genus wiring, a method of manufacturing a semiconductor device, which comprises.