JP2936894B2 - Data storage circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage circuit having an error correction / detection function using an error correction code.

[0002]

2. Description of the Related Art Error correction using a conventional error correction code
FIG. 3 shows a configuration of a data storage circuit having a detection function.

The data storage circuit includes an error correction code control circuit 14, a memory (data section) 15, a memory (error correction code section) 16, a memory selection signal (CS) input terminal 17,
It comprises a read signal (RD) input terminal 18 and a write enable signal (WE) input terminal 19. Note that the address and other control signals are omitted because they are unnecessary for the description.

When storing data, the data 20 to be stored is input to the error correction code control circuit 14 so that an error correction code corresponding to the data is generated in the error correction code control circuit 14. 21 and the error correction code 22 are output. These are input to the memory 15 and the memory 16 respectively, and the memory 21 and the error correction code 22 are stored in the respective memories 15 and 16 when the memory selection signal (CS) and the write enable signal (WE) to the memory are simultaneously set to the low level. 16 are written simultaneously. The memories 15 and 16 shown in this example perform writing of data and reading of stored data under the following signal input conditions.

Data write condition Memory select signal (CS): low level write enable signal (WE): low level read signal (RD): high level Data read condition Memory select signal (CS): low level write enable signal (WE) : High level Read signal (RD): Low level

When reading data, each of the memories 15,
At the same time, the memory selection signal (CS) and the read signal (RD) of the memory become low level, so that the data 21 and the error correction code 22 stored in the memories 15 and 16 are changed to the memories 15 and 16. And input to the error correction code control circuit 14. Then, error correction using the error correction code is performed in the error correction code control circuit 14, and the corrected data (the data as it is when there is no error) is output from the error correction code control circuit 14.

In other words, the data storage circuit of this example adds an error correction code corresponding to data at the time of writing data, stores the data together with the data, and performs error correction using the stored data and the error correction code at the time of reading data. It has a function to output the converted data.

[0008]

As described above, in a conventional data storage circuit having an error correction / detection function, when data is stored, the data and the error correction code corresponding to the data are always written to the memory at the same time. Therefore, there is a problem that an error is generated in the data stored in the memory, and the operation of the error correction / detection function cannot be confirmed.

If a mechanism for setting an error is provided in a part of the error correction code control circuit in the above-described example, an error can be generated in a pseudo manner and the operation of the error correction / detection function can be confirmed. However, if many error occurrence patterns can be handled, there is a disadvantage that the hardware becomes very complicated.

The present invention has been made in view of such circumstances, and an object of the present invention is to realize the occurrence of a pseudo error required for confirming an error correction and detection operation by adding simple hardware. Is to do.

[0011]

According to the present invention, there is provided a data storage circuit having an error correction / detection function using an error correction code. An error correction code control circuit for performing correction / detection; a first memory for storing data output from the error correction code control circuit; and a second memory for storing an error correction code output from the error correction code control circuit. Memory and an externally provided error setting control signal,
Supply read / write signal and the first memory
Input the selected memory selection signal, and
If the write signal indicates the read state,
Regardless of the state of the setting control signal.
The supplied memory selection signal is stored in the memory of the second memory.
The memory is also supplied to the second memory as a memory selection signal,
If the read / write signal indicates a write state,
The error setting control signal indicates an error setting prohibited state.
A memory supplied to the first memory only in a case
The selection signal is used as a memory selection signal for the second memory.
And a gate circuit that also supplies the second memory .

[0012]

In the data storage circuit of the present invention, the gate circuit is provided with an externally applied error setting control signal, readout signal,
/ Write signal and the memory supplied to the first memory.
Input the memory selection signal and read / write signal
Error setting control signal is incorrect if the
It is supplied to the first memory only when it indicates the setting prohibited state.
The selected memory selection signal of the second memory.
By supplying the data output from the error correction code control circuit and the error correction code to the first memory and the second memory by supplying the data to the second memory as a signal. On the other hand, the read / write signal indicates the write state.
Error setting control signal is
If it is not in the prohibited state, that is, if the error setting is permitted,
Since the memory selection signal is not supplied to the second memory, only the data of the output of the error correction code control circuit is written to the first memory, and the contents of the second memory remain unchanged. Therefore, if data different from the original data is written only in the first memory, a pseudo error can be generated. In addition, the gate circuit has a read / write signal
Error setting control signal when
Memo supplied to the first memory regardless of the state of
The second reselection signal is used as a memory selection signal of the second memory.
Error setting control signal.
Even if the address is set incorrectly,
Data can be read.

[0013]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The data storage circuit of this embodiment includes an error correction code control circuit 1, a memory (data section) 2, a memory (error correction code section) 3, a gate circuit 40 composed of a NOR circuit 4 and an OR circuit 5, an error setting control circuit. Signal (ERR SET)
The input terminal 6 includes a read / write signal (R / W) input terminal 7, a memory selection signal (CS) input terminal 8, a read signal (RD) input terminal 9, and a write enable signal (WE) input terminal 10.

Each input signal to the data storage circuit has the following meaning.

Error setting control signal (ERR SET) High level: Error setting disabled state Low level: Error setting enabled state Read / write signal (R / W) High level: Read operation Low level: Write operation Memory selection signal (CS) High level: Memory not selected Low level: Memory selection ・ Read signal (RD) High level: Read prohibited Low level: Read enabled ・ Write signal (WE) High level: Write prohibited Low level: Write enabled

The memories 2 and 3 are provided with a memory selection signal (C) for controlling data writing / reading.
S), write enable signal (WE), read signal (R
D), and write data and read stored data under the following signal input conditions.

Data write condition Memory select signal (CS): Low level Write enable signal (WE): Low level Read signal (RD): High level Data read condition Memory select signal (CS):
Low level Write enable signal (WE): High level Read signal (RD): Low level

The connection between the input terminal of each signal and each circuit will be described below. Error setting control signal (ERR SET)
The input terminal 6 and the read / write (R / W) signal input terminal 7 are connected to the input of the NOR circuit 4 of the gate circuit 40, and the output of the NOR circuit 4 is input to one of the inputs of the OR circuit 5.

Further, a memory selection signal (CS) input terminal 8
Is connected to the remaining input of the OR circuit 5 and the memory selection signal (CS) input terminal of the memory 2, and the output of the OR circuit 5 is connected to the memory selection signal (CS) input terminal of the memory 3. Further, the read signal (RD) input terminal 9 is connected to the read signal (RD) input terminals of both memories 2 and 3, and the write enable signal (WE) input terminal 10 is connected to the write enable signal of both memories 2 and 3. (WE) Connected to input terminal.

In the configuration diagram shown in FIG. 1, only a part of signals necessary for writing / reading data and memory is shown, and other control signals, address signals, and signals for error correction function are provided. The details of the circuit are omitted because they are not particularly necessary for describing the present invention.

Next, the operation of this embodiment will be described. When the error setting control signal (ERR SET) is at a high level, the output of the NOR circuit 4 is always at a low level. Therefore, when the memory selection signal (CS) at the CS signal input terminal 8 goes to a low level, the OR circuit 5 The output goes low. That is, when the memory selection signal (CS) at the CS signal input terminal 8 is at a low level, a low level signal is simultaneously input to both the memory selection signal (CS) input terminals of the memories 2 and 3. The operation in this case is exactly the same as the example shown in FIG.

That is, when storing data, the data 11 to be stored is input to the error correction code control circuit 1 so that an error correction code corresponding to the data is generated in the error correction code control circuit 1, 12 and the error correction code 13 are output. These are input to the memories 2 and 3, respectively, and when the memory selection signal (CS) and the write enable signal (WE) of the memory go low at the same time, the data 12 and the error correction code 13 are stored in each of the memories 2 and 3. 3 are written simultaneously.

When data is read out, the memory selection signal (CS) and the readout signal (RD) to the memories are simultaneously set to low level for each of the memories 2 and 3, so that the data is stored in the memories 2 and 3. The data and the error correction code are read from the memories 2 and 3 and input to the error correction code control circuit 1. Then, error correction using the error correction code is performed in the error correction code control circuit 1, and the corrected data (data as it is when there is no error) is output from the error correction code control circuit 1.

Next, an error setting control signal (ERR SET)
The operation when is low level will be described. When the error setting control signal (ERR SET) is at a low level, the error setting is permitted.

When the read / write signal (R / W) is set to a low level in order to store data while the error setting control signal (ERR SET) is at a low level,
Since the output of the NOR circuit 4 is at a high level, the output of the OR circuit 5 is always at a high level. That is, even if the input signal to the memory selection signal (CS) input terminal 8 is low level,
The input of the memory selection signal (CS) input terminal of the memory 3 becomes high level, and only the input of the memory selection signal (CS) input terminal of the memory 2 becomes low level. That is, when data is stored in a state where the error setting control signal (ERR SET) signal is at a low level, the data is written only in the memory 2 and the content stored in the memory 3 is not rewritten. Therefore, by writing the erroneous data while the error setting control signal (ERR SET) is at the low level, a pseudo error can be freely generated in the data in the memory.

When reading data, since the read / write signal (R / W) goes high,
Since the output of the NOR circuit 4 is at a low level, when the input signal to the memory selection signal (CS) input terminal 8 is at a low level, both the memory selection signal (CS) input terminals of the memories 2 and 3 are at a low level. The operation is the same as the operation at the time of data reading described above.

With the function described above, a pseudo error can be generated in the data stored in the memory, and the error correction function can be confirmed.

FIG. 2 is a flowchart showing an example of a procedure for confirming the error correction function of the error correction code control circuit 1. First, data of an address for setting an error is read from the memory 2 (S1), and then an error setting control signal (ERR SE
T) The input is set to a low level, and an error can be set (S2). Next, an error is set in the read data and written to the same address (S3). At this time, since the error correction code is not written in the memory 3, the previous state is maintained. Next, an error setting control signal (ERR SET) input is set to a high level, and error setting is prohibited (S4). Next, the data at the address where the error is set is read (S
5) Compare with the first data and confirm the error correction / detection operation (S6).

Thus, the error correction / detection operation for one error occurrence pattern has been confirmed, and the same applies to the other error occurrence patterns.

[0031]

As described above, according to the present invention, in a data storage circuit having an error correction function, a condition for writing to a second memory for storing an error correction code is determined by setting a condition for writing to a first memory for storing data. A simple configuration in which a gate circuit that is established only when both the data write condition and the condition based on an external input signal are satisfied is provided, and the error correction code in the first memory can be stored in the first memory without changing the contents of the second memory. It is possible to rewrite only the contents of data corresponding to.

For this reason, all possible errors can be set in a pseudo manner for the data stored in the memory, and the actual operation of the error detection / correction function can be confirmed. Testability is improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a flowchart showing a procedure of an error correction function confirmation method in the embodiment of FIG. 1;

FIG. 3 is a configuration diagram of a conventional data storage circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Error correction code control circuit 2 ... Memory (data part) 3 ... Memory (error correction code part) 4 ... NOR circuit 5 ... OR circuit 6 ... ERR set signal input terminal 7 ... R / W signal input terminal 8 ... CS signal Input terminal 9 RD signal input terminal 10 WE signal input terminal 11 Data 12 Data 13 Error correction code 14 Error correction code control circuit 15 Memory (data part) 16 Memory (error correction code part) 17 CS signal input terminal 18 RD signal input terminal 19 WE signal input terminal 20 data 21 data 22 error correction code 40 gate circuit

Claims (1)

(57) [Claims] 1. A data storage circuit having an error correction / detection function using an error correction code, comprising: an error correction code control circuit for generating an error correction code and performing error correction / detection using the error correction code; A first memory for storing data output from the control circuit, a second memory for storing the error correction code output from the error correction code control circuit, an externally provided error setting control signal, read / write
And a memo supplied to the first memory.
A reselection signal is input and the read / write signal is read.
If the error setting control signal
Is supplied to the first memory regardless of the state of
The memory selection signal is the same as the memory selection signal of the second memory.
To the second memory to read / write the data.
If the write signal indicates a write state, the error
Only when the setting control signal indicates an error setting prohibited state
The memory selection signal supplied to the first memory is
The second memory as a memory selection signal for a second memory;
And a gate circuit that also supplies the data to the data storage circuit.