JPH0778494A - Dynamic ram - Google Patents

Abstract

PURPOSE:To correct an error with a good economicity and to make an incorri gible error be not generated at the time of a refresh. CONSTITUTION:The error of a data read out from a data storage part 11 is corrected with an error control code read out from an error control code storage part 12 in an error correction circuit 13. The data is stored again in the data storage part 11 and also an error control code with respect to the error corrected data is newly produced in an error control code adding part 14 to be stored in the error control code storage part 12. This refreshing operation is repeated in a RAM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM which performs error correction even on data being refreshed.

[0002]

2. Description of the Related Art Generally, when a semiconductor memory device is used and bit errors due to the characteristics of the memory device are avoided and reliability is improved, an error correction circuit is constructed by an external circuit of the memory device to perform error correction. There is.

[0003]

However, such a conventional device has to have an error correction circuit outside the memory element, resulting in high cost. In addition, even if an error correction circuit is added later to improve reliability of an already designed device, redesign is required, which is also uneconomical. In addition, even if such error correction is performed, in the dynamic RAM, the refresh operation is performed inside the memory element. Therefore, if an error occurs during refresh, it cannot be corrected, and the error does not occur inside the memory element. However, there is a problem that an error that cannot be corrected by the error correction circuit is finally generated. The present invention has been made in view of such a situation, and is intended to correct an error economically and prevent an uncorrectable error from being generated at the time of refreshing.

[0004]

In order to solve such a problem, the present invention provides a data storage unit for storing data, an error control code storage unit for storing an error control code of data,
An error correction circuit that performs error correction using the error control code read from the error control code storage unit when the data content read from the data storage unit is incorrect at the time of refreshing or when a read signal is supplied. An error control code adding unit for generating an error control code for the data error-corrected by the correction circuit and storing it in the error control code storage unit is integrally incorporated.

[0005]

The data read out from the data storage unit is error-corrected by the error control code read out from the error control code storage unit, and the error control code is stored again in the data storage unit. An error control code is newly created for the error-corrected data, and the refresh operation of storing the error control code in the error control code storage unit is repeated.

[0006]

FIG. 1 is a block diagram showing an embodiment of the present invention. A dynamic RAM 1 includes a data storage unit 11 for storing data, an error control code storage unit 12 for storing error control codes, and a data storage unit 11. From the error correction circuit 13 that performs error correction with the read data and the error control code read from the error control code storage unit 12, from the error code addition unit 14 that adds the error control code to the error corrected data It is configured. Note that symbol 2 is an I / O switch, which controls whether or not an input signal is taken in by a control signal (not shown).

In the apparatus thus configured, at the time of refreshing, data is read from the data storage section 11 by a refresh signal (not shown) supplied from the outside, and corresponding data is read from the error control code storage section 12. The error control codes are read out and supplied to the error correction circuit 13. As a result, the error correction circuit 13 detects whether or not there is an error in the read data by using the error control code, corrects any error, and sends the corrected data.

The data sent from the error correction circuit 13 is sent to the output terminal and the error control code adding section 1
4 is supplied. The error control code adding unit 14 generates a control code for performing error correction on the supplied data and supplies it to the error control code storage unit 12. The error control code generated thereby is stored in the error control code storage unit 12.

On the other hand, since the data sent from the error correction circuit 13 is supplied to the data storage unit 11, it is stored there. This completes the refresh of both the data and the error control code.

When an address input signal is supplied from the outside, the data of the address signal is read from the data storage unit 11 and the error control code storage unit 12 and is supplied to the error correction circuit 13 respectively. An error check is performed there, and if there is a read error, it is corrected and the corrected data is sent to the output terminal. Of course, if there is no error, the read data is directly supplied to the output terminal.

In order to write data from the outside, data to be written is supplied to the input terminal, and a signal for turning on the I / O switch 2 is then supplied from an external circuit (not shown). Turns on the I / O switch 2. Therefore, the data to be written is supplied to and stored in the data storage unit 11, and the error control code storage unit 12 generates an error control code for error correction of the written data. Are stored in the error control code storage unit 12.

The dynamic RAM needs a clock signal, a write signal, a read signal, a refresh signal, a signal for turning on the I / O switch 2, and the like, but these signals are well known. , Its details are omitted.

[0013]

As described above, according to the present invention, the error control code is stored together with the data at the time of storage, both the data and the error control code are read at the time of reading, and the read data is erroneous by using the error control code. When the data is corrected and refreshed, the error-corrected data is stored again, an error control code is newly generated for error correction of the stored data, and the error control code is also stored. Therefore, reliable error correction can be performed. In addition, since the error correction circuit is integrated, the economy is improved, and in the past, read errors that occurred during refresh were accumulated and eventually became uncorrectable. It is possible to correct immediately, and there is an effect that an uncorrectable error due to a read error does not occur.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

[Explanation of symbols]

 1 Dynamic RAM 11 Data Storage Unit 12 Error Control Code Storage Unit 13 Error Correction Circuit 14 Error Control Code Addition Unit 2 I / O Switch

Claims (1)

[Claims] 1. A data storage unit for storing data, an error control code storage unit for storing an error control code of the data, and a data content read from the data storage unit at the time of refreshing or by supplying a read signal. Error correction circuit that performs error correction using the error control code read from the error control code storage unit when an error is present, and an error control code that generates error control code for the data error-corrected by the error correction circuit A dynamic RAM characterized in that an error control code addition section to be stored in a control code storage section is integrally incorporated.