JP2933105B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2933105B2 JP2933105B2 JP3269645A JP26964591A JP2933105B2 JP 2933105 B2 JP2933105 B2 JP 2933105B2 JP 3269645 A JP3269645 A JP 3269645A JP 26964591 A JP26964591 A JP 26964591A JP 2933105 B2 JP2933105 B2 JP 2933105B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- lead
- external
- upper resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、樹脂封止型の多ピンの
半導体装置に関する。The present invention relates to a resin-sealed multi-pin semiconductor device.
【０００２】近年、半導体装置の高集積化より多ピン化
が進むと共に、小型化が常に要求される。これに伴い微
小ピッチで配列される外部リードの幅、厚みが小さくな
り、強度が極めて低くなってきている。そのため、製造
から実装まで、外部リードにストレスを加えないことが
重要となる。In recent years, as the number of pins has increased due to higher integration of semiconductor devices, miniaturization has always been required. As a result, the width and thickness of the external leads arranged at a fine pitch have become smaller, and the strength has become extremely low. Therefore, it is important not to apply stress to the external leads from manufacturing to mounting.
【０００３】[0003]
【従来の技術】図６（Ａ），（Ｂ）に従来の半導体装置
の断面図を示す。図６（Ａ）は平面断面図、図６（Ｂ）
は図６（Ａ）のＡ−Ａ断面図である。図６（Ａ），
（Ｂ）において、半導体装置３０は、いわゆるＱＦＰ
（Quad FlatPackage)型のもので、リードフレーム３１
の中央部分のステージ３２上に半導体チップ３３が搭載
される。そして、半導体チップ３３とリードフレーム３
１の内部リード３４とがワイヤ３５によりボンディング
され、封止樹脂３６によりモールドされる。また、リー
ドフレーム３１の外部リード３７がＬ型形状に加工され
る。2. Description of the Related Art FIGS. 6A and 6B are sectional views of a conventional semiconductor device. FIG. 6A is a plan cross-sectional view, and FIG.
FIG. 7 is a sectional view taken along the line AA of FIG. FIG. 6 (A),
In (B), the semiconductor device 30 is a so-called QFP
(Quad FlatPackage) type lead frame 31
The semiconductor chip 33 is mounted on the stage 32 at the center of the semiconductor chip 33. Then, the semiconductor chip 33 and the lead frame 3
The first internal lead 34 is bonded with a wire 35 and molded with a sealing resin 36. Further, the external leads 37 of the lead frame 31 are processed into an L-shape.
【０００４】例えば、外部リード３７がピッチ０．５ｍ
ｍで３００ピンを越えるものや、ピッチ０．４ｍｍ，
０．３ｍｍで１００ピンを越えるパッケージが開発され
ている。この場合の外部リード３７の厚さも約２００μ
ｍから約１００μｍに移行してきている。For example, when the external leads 37 have a pitch of 0.5 m
over 300 pins in pitch m, pitch 0.4mm,
Packages exceeding 100 pins at 0.3 mm have been developed. In this case, the thickness of the external lead 37 is also about 200 μm.
from about m to about 100 μm.
【０００５】このような半導体装置３０について、メー
カーの出荷、ユーザーの受け入れ等の特性試験を行う場
合、試験装置におけるプローブ又はソケットにより、当
該半導体装置３０の外部リード３７の先端部をコンタク
トさせて行っている。When such a semiconductor device 30 is subjected to a characteristic test such as shipment from a manufacturer, acceptance of a user, or the like, the tip of the external lead 37 of the semiconductor device 30 is brought into contact with a probe or a socket in the test device. ing.
【０００６】[0006]
【発明が解決しようとする課題】しかし、上述のように
外部リード３７の幅、厚みが小さくなって強度が極めて
低くなってきていることから、試験時におけるプローブ
又はソケットとのコンタクトの際に、外部リード３７が
変形する危険性が高いという問題がある。However, as described above, the width and thickness of the external lead 37 have become smaller and the strength has become extremely low. There is a problem that the risk of deformation of the external lead 37 is high.
【０００７】また、当該半導体装置３０の特性試験を行
う際、プローブ又はソケットのコンタクト、外部リード
長を含めたパスが長くなり、インピーダンスの影響で高
速素子の特性に変動を生じ易くなるという問題がある。Further, when a characteristic test of the semiconductor device 30 is performed, a path including a probe or socket contact and an external lead length becomes long, and the characteristic of the high-speed element tends to fluctuate due to the influence of impedance. is there.
【０００８】そこで、本発明は上記課題に鑑みなされた
もので、外部リードの変形を防止して確実な特性試験が
可能な半導体装置を提供することを目的とする。The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device capable of preventing deformation of external leads and performing a reliable characteristic test.
【０００９】上記課題は、リードフレームのステージ上
にチップが搭載され、該リードフレームの内部リードと
の接続後、外部リードを延出させて樹脂モールドにより
パッケージングされる半導体装置において、前記パッケ
ージングにより形成されるパッケージの、実装面に対す
る前記外部リードより上方の上部樹脂を、該外部リード
の下面の表出部を表出させて下部樹脂より大に形成する
と共に、前記上部樹脂の端部より外側で前記外部リード
が前記実装面側に折り曲げられた構成とすることにより
解決することができる。 [0009] The above object is to provide a semiconductor device in which a chip is mounted on a stage of a lead frame, and after connecting with an internal lead of the lead frame, external leads are extended and packaged by resin molding. The upper resin above the external lead with respect to the mounting surface of the package formed by exposing the exposed portion of the lower surface of the external lead to be larger than the lower resin and from the end of the upper resin This can be solved by adopting a configuration in which the external lead is bent toward the mounting surface on the outside .
【００１０】また、リードフレームのステージ上にチッ
プが搭載され、該リードフレームの内部リードとの接続
後、外部リードを延出させて樹脂モールドによりパッケ
ージングされる半導体装置において、前記パッケージン
グにより形成されるパッケージの、実装面に対する前記
外部リードより上方の上部樹脂と下部樹脂の大きさを異
ならせ、該外部リードの一面の表出部表出させて形成
し、該上部樹脂と該下部樹脂との大きさの差部分で表出
する該表出部間に、突出部を一体で形成することによっ
ても解決される。In a semiconductor device in which a chip is mounted on a stage of a lead frame and connected to internal leads of the lead frame, external leads are extended and packaged by resin molding. The size of the upper resin and the lower resin above the external lead with respect to the mounting surface of the package to be formed is made different, and the exposed portion of one surface of the external lead is exposed to form the upper resin and the lower resin. The problem can also be solved by integrally forming the protruding portion between the exposed portions exposed at the difference in size.
【００１１】[0011]
【作用】上述のように、上部樹脂と下方の下部樹脂の大
きさを異ならせて形成し、 その大きさの差部分で外部
リードの上面又は下面の表出部を表出させている。 As described above, the size of the upper resin and the size of the lower resin below are large.
Formed with different sizes, and the difference in size
The exposed portion on the upper or lower surface of the lead is exposed.
【００１２】これにより、半導体装置の特性試験を行う
際、上記外部リードの表出した下面の表出部に試験を行
うためのプローブ又はソケットを接触導通させて行うこ
とが可能となる。すなわち、外部リードの先端で試験を
行なわないことから、該外部リードの幅が狭く、厚みが
小さくても、試験時に外部リードを変形させることを防
止することが可能となる。This makes it possible to conduct a characteristic test of the semiconductor device by bringing a probe or a socket for conducting the test into contact with the exposed portion of the exposed lower surface of the external lead. That is, since the test is not performed at the tip of the external lead, it is possible to prevent the external lead from being deformed during the test even if the external lead is narrow and thin.
【００１３】また、試験の際には上述の外部リードの下
面の表出部をプローブ又はソケットに搭載接触させると
共に、該表出部の接触位置がチップに近い位置であるこ
とから、試験時の信号パスが短縮されることになり、高
速素子の特性変動を防止することが可能となる。In the test, the exposed portion on the lower surface of the external lead is brought into contact with the probe or the socket, and the contact position of the exposed portion is close to the chip. Since the signal path is shortened, it is possible to prevent the characteristic fluctuation of the high-speed element.
【００１４】また、上部樹脂と下部樹脂の何れかを他方
より大に形成し、その差部分で表出している外部リード
の一面の表出部間に突出部を形成させる。Further, one of the upper resin and the lower resin is formed larger than the other resin, and a protruding portion is formed between the exposed portions of one surface of the external lead exposed at the difference.
【００１５】これにより、上述の外部リードの変形や高
速素子の特性変動が前述と同様に防止されると共に、表
出させた外部リードの表出部と、特性試験時のプローブ
又はソケットの接触位置のずれを該突出部より規制させ
ることが可能となり、確実な試験を行うことが可能とな
る。As a result, the deformation of the external lead and the variation in the characteristics of the high-speed element are prevented in the same manner as described above, and the exposed portion of the external lead and the contact position of the probe or the socket at the time of the characteristic test are prevented. Can be regulated by the projecting portion, and a reliable test can be performed.
【００１６】[0016]
【実施例】図１に、本発明の第１の実施例の構成図を示
す。図１（Ａ）は側部断面図であり、図１（Ｂ）は底面
図である。FIG. 1 shows a configuration diagram of a first embodiment of the present invention. FIG. 1A is a side sectional view, and FIG. 1B is a bottom view.
【００１７】図１（Ａ），（Ｂ）の半導体装置１Ａにお
いて、リードフレーム２のステージ３上にチップ４が搭
載され、リードフレーム２の内部リード５との間でワイ
ヤ６によりボンディングされる。そして、モールド樹脂
によりパッケージ７が形成され、その後リードフレーム
２の外部リード８が回路基板の表面に実装が可能となる
ような形状に足曲げ加工される。In the semiconductor device 1A shown in FIGS. 1A and 1B, a chip 4 is mounted on a stage 3 of a lead frame 2 and is bonded to an internal lead 5 of the lead frame 2 by a wire 6. Then, a package 7 is formed by a mold resin, and thereafter, the external leads 8 of the lead frame 2 are bent in a shape such that the external leads 8 can be mounted on the surface of the circuit board.
【００１８】この場合、パッケージ７の外部リード８よ
り上方の上部樹脂７ａは下部樹脂７ｂより大に形成さ
れ、上部樹脂７ａと下部樹脂７ｂとの大きさの差部分、
すなわち上部樹脂７ａの下面縁端部分で外部リード８の
下面が表出する表出部８ａが形成される。そして、表出
部８ａ周辺の面は上部樹脂７ａの下面縁端部分に埋設さ
れる。なお、該上部樹脂７ａの下面縁端部分における外
部リード８は少なくとも下面の表出部８ａが表出してい
ればよい。In this case, the upper resin 7a above the external leads 8 of the package 7 is formed to be larger than the lower resin 7b, and a difference in size between the upper resin 7a and the lower resin 7b,
That is, an exposed portion 8a is formed at the edge of the lower surface of the upper resin 7a so that the lower surface of the external lead 8 is exposed. The surface around the exposed portion 8a is buried in the lower edge of the upper resin 7a. The external lead 8 at the lower edge of the upper resin 7a only needs to be exposed at least at the exposed portion 8a on the lower surface.
【００１９】例えば、外部リード８の幅が０．１ｍｍ〜
０．２ｍｍ、厚さが１００μｍでピッチを０．３ｍｍ〜
０．４ｍｍとして１００本以上配列される。For example, when the width of the external lead 8 is 0.1 mm to
0.2mm, 100μm thickness, 0.3mm pitch
100 or more are arranged as 0.4 mm.
【００２０】この場合、表出部８ａは、リード長さで４
００μｍ表出される。すなわち、この４００μｍは、後
述する特性試験におけるプローブとの接触のために必要
なリード長である。In this case, the exposed portion 8a has a lead length of 4
It is expressed as 00 μm. That is, this 400 μm is a lead length necessary for contact with the probe in a characteristic test described later.
【００２１】ここで、図２に、図１の製造工程を説明す
るための図を示す。図２において、まず、リードフレー
ム２のステージ３上にチップ４を搭載して、内部リード
５とワイヤ６によりボンディング後、上金型９ａ及び下
金型９ｂにより形成されるキャビティ１０内にチップ４
周辺のモールド部分が位置される。Here, FIG. 2 is a view for explaining the manufacturing process of FIG. In FIG. 2, first, the chip 4 is mounted on the stage 3 of the lead frame 2, and after bonding with the internal lead 5 and the wire 6, the chip 4 is placed in the cavity 10 formed by the upper mold 9a and the lower mold 9b.
A peripheral mold portion is located.
【００２２】この場合、上金型９ａの空間は下金型９ｂ
の空間より大に形成されており、リードフレーム２の内
部リード５と外部リード８の一部を上金型９ａにより覆
っている。そして、リードフレーム２の位置決めのため
に、下金型９ｂに突起１１が形成され、リードフレーム
２を貫通して上金型９ａに嵌合する。In this case, the space of the upper mold 9a is
The inner lead 5 and a part of the outer lead 8 of the lead frame 2 are covered by an upper mold 9a. Then, a projection 11 is formed on the lower mold 9b for positioning the lead frame 2, and penetrates through the lead frame 2 to fit into the upper mold 9a.
【００２３】そして、上金型９ａに形成されているゲー
ト１２よりモールド樹脂を注入してパッケージングする
ものである。Then, a molding resin is injected from the gate 12 formed on the upper mold 9a to perform packaging.
【００２４】そこで、図３に、本発明による特性試験を
説明するための図を示す。図３において、試験装置１３
におけるソケット１４より、半導体装置１Aの外部リー
ド８の数に応じたプローブ１５が設けられている。そし
て、このプローブ１５上に、半導体装置１A における外
部リード８の表出部８ａが接触導通するように載置され
ることにより特性試験が行われるものである。FIG. 3 is a diagram for explaining a characteristic test according to the present invention. In FIG. 3, the test device 13
Are provided with probes 15 corresponding to the number of external leads 8 of the semiconductor device 1A . Then, a characteristic test is performed by placing the exposed portion 8a of the external lead 8 in the semiconductor device 1A on the probe 15 so as to be in contact with and conduction.
【００２５】すなわち、半導体装置１A の特性試験を行
うにあたり、ソケット１４上に載置すれば足り、また、
プローブ１５との接触を外部リード８の先端ではなく、
上部樹脂７ａに３面が埋設された外部リード８の表出部
８ａで行っている。これにより、外部リード８の強度が
低くても変形を防止して容易に特性試験を行うことがで
きる。That is, in conducting a characteristic test of the semiconductor device 1 A , it is sufficient to mount the semiconductor device 1 A on the socket 14.
The contact with the probe 15 is not the tip of the external lead 8,
This is performed at the exposed portion 8a of the external lead 8 in which three surfaces are embedded in the upper resin 7a. Thereby, even if the strength of the external lead 8 is low, deformation can be prevented and the characteristic test can be easily performed.
【００２６】また、試験を行うに際し、信号経路となる
プローブ１５を長く設ける必要がなく、また該プローブ
１５とチップ４に近い位置で接触させることができるこ
とから、信号パスが短くなってインピーダンスの増加を
回避することができる。これにより、チップ４が高速素
子の場合に、インピーダンスの影響を受けず、特性変動
が防止されて正確な特性試験を行うことができるもので
ある。In conducting a test, it is not necessary to provide a long probe 15 as a signal path, and the probe 15 can be brought into contact with the probe 4 at a position close to the chip 4, so that the signal path is shortened and the impedance is increased. Can be avoided. Thereby, when the chip 4 is a high-speed element, the characteristic fluctuation is prevented without being affected by impedance, and an accurate characteristic test can be performed.
【００２７】次に、図４に、図１のリード形状の変形例
の構成断面図を示す。図１では、外部リード８の表面実
装用にＬ型形状に形成した場合を示したが、図４（Ａ）
は、外部リード８A を下方に約直角に足曲げ加工したも
のである。また、図４（Ｂ）は外部リード８B を足曲げ
加工せずに直線形状としたものである。図４（Ａ），
（Ｂ）両方共に外部リード８A ，８B には、上述と同様
に、表出部８ａが形成されるもので、効果は図１と同様
である。Next, FIG. 4 is a sectional view showing the configuration of a modification of the lead shape shown in FIG. FIG. 1 shows a case where the external lead 8 is formed in an L-shape for surface mounting, but FIG.
Is obtained by legs bent approximately at right angles to the outer leads 8 A downward. Further, FIG. 4 (B) is obtained by a linear shape without bending legs outer leads 8 B. FIG. 4 (A),
The outer leads 8 A, 8 B in (B) both, in the same manner as described above, those exposed portions 8a are formed, the effect is the same as that shown in FIG.
【００２８】次に、図５に、本発明の第２の実施例の構
成図を示す。図５は、底面から観た斜視図を示したもの
である。図５における半導体装置１B は、外部リード８
の下面に表出部８ａを形成させて、上部樹脂７ａを下部
樹脂７ｂより大に形成するのは図１と同様である。この
場合、外部リード８の表出部８ａの間に突出部１６を上
部樹脂７ａと一体に形成したものである。Next, FIG. 5 shows a configuration diagram of a second embodiment of the present invention. FIG. 5 is a perspective view as viewed from the bottom. The semiconductor device 1 B is shown in FIG. 5, the outer leads 8
The upper portion 7a is formed larger than the lower portion resin 7b by forming the exposed portion 8a on the lower surface of the substrate as in FIG. In this case, the protrusion 16 is formed integrally with the upper resin 7a between the exposed portions 8a of the external leads 8.
【００２９】この半導体装置１B は、基本的に図１に示
す半導体装置１A の効果と同様であり、これに加えて特
性試験時に突出部１６が表出部８ａに接触するプローブ
（図３参照）の位置規制の役割を果たす。すなわち、プ
ローブの位置ずれを防止して確実な試験を行うことがで
きるものである。[0029] The semiconductor device 1 B is similar to the effect of essentially the semiconductor device 1 A shown in FIG. 1, a probe was added protrusion 16 at the time characteristics testing is this contact with the exposed portion 8a (FIG. 3 Plays a role in position regulation (see Ref.). That is, it is possible to perform a reliable test while preventing the displacement of the probe.
【００３０】なお、図５では、パッケージ７を上部樹脂
７ａを下部樹脂７ｂより大に形成する場合を示したが、
搭載されるチップが試験時にインピーダンスの影響を受
けない場合には、下部樹脂７ｂを上部樹脂７ａより大に
形成してもよい。この場合、表出部８ａは外部リード８
の上面に形成され、表出部８ａ間には突出部１６が形成
されるものである。そして、特性試験時には上方にプロ
ーブが位置し、突出部１６により位置規制されて確実に
表出部１６と接触導通させることができる。FIG. 5 shows a case where the package 7 is formed so that the upper resin 7a is larger than the lower resin 7b.
If the mounted chip is not affected by the impedance during the test, the lower resin 7b may be formed larger than the upper resin 7a. In this case, the exposed portion 8a is the external lead 8
Are formed on the upper surface, and a protruding portion 16 is formed between the exposed portions 8a. During the characteristic test, the probe is located above, and the position is regulated by the protruding portion 16 so that the probe can be reliably brought into contact with the exposed portion 16.
【００３１】なお、第２の実施例における外部リード８
の形状は、図１及び図４と同様に形成される。Note that the external leads 8 in the second embodiment
Is formed in the same manner as in FIGS.
【００３２】[0032]
【発明の効果】以上のように本発明によれば、パッケー
ジの上部樹脂を下部樹脂より大に形成し、その大きさの
差部分で外部リードの下面を表出させることにより、ま
た、表出部間に突出部を形成することにより、特性試験
時における外部リードの変形を防止して、確実に試験を
行うことができる。According to the present invention as described above, according to the present invention, to form an upper resin package larger than the lower resin, by to expose the lower surface of the outer leads by the size difference between the portion of its, also, Table By forming the protruding portions between the protruding portions, deformation of the external leads during the characteristic test can be prevented, and the test can be reliably performed.
【図１】本発明の第１の実施例の構成図である。FIG. 1 is a configuration diagram of a first embodiment of the present invention.
【図２】図１の製造を説明するための図である。FIG. 2 is a view for explaining the manufacture of FIG. 1;
【図３】本発明による特性試験を説明するための図であ
る。FIG. 3 is a diagram for explaining a characteristic test according to the present invention.
【図４】図１のリード形状の変形例の構成断面図であ
る。FIG. 4 is a sectional view of a configuration of a modification of the lead shape of FIG. 1;
【図５】本発明の第２の実施例の構成図である。FIG. 5 is a configuration diagram of a second embodiment of the present invention.
【図６】従来の半導体装置の断面図である。FIG. 6 is a cross-sectional view of a conventional semiconductor device.
１A ，１B 半導体装置 ２ リードフレーム ３ ステージ ４ チップ ５ 内部リード ６ ワイヤ ７ パッケージ ７ａ 上部樹脂 ７ｂ 下部樹脂 ８ 外部リード ８ａ 表出部 １６ 突出部 DESCRIPTION OF SYMBOLS 1 A , 1B semiconductor device 2 Lead frame 3 Stage 4 Chip 5 Internal lead 6 Wire 7 Package 7a Upper resin 7b Lower resin 8 External lead 8a Exposure 16 Projection
Claims (4)
搭載され、前記リードフレームの内部リードとの接続
後、外部リードを延出させて樹脂モールドによりパッケ
ージングされる半導体装置において、 前記パッケージングにより形成されるパッケージの、実
装面に対する前記外部リードより上方の上部樹脂を、前
記外部リードの下面の表出部を表出させて下部樹脂より
大に形成すると共に、前記上部樹脂の端部より外側で前
記外部リードが前記実装面側に折り曲げられていること
を特徴とする半導体装置。1. A semiconductor device in which a chip is mounted on a stage of a lead frame, connected to an internal lead of the lead frame, and then external leads are extended and packaged by resin molding. The upper resin above the external lead with respect to the mounting surface of the package to be formed is formed larger than the lower resin by exposing the exposed portion of the lower surface of the external lead, and is formed outside the end of the upper resin. The semiconductor device according to claim 1, wherein the external lead is bent toward the mounting surface.
搭載され、前記リードフレームの内部リードとの接続
後、外部リードを延出させて樹脂モールドによりパッケ
ージングされる半導体装置において、 前記パッケージングにより形成されるパッケージの、実
装面に対する前記外部リードより上方の上部樹脂と下方
の下部樹脂の大きさを異ならせ、前記外部リードの一面
の表出部を表出させて形成し、 前記上部樹脂と前記下部樹脂との大きさの差部分で表出
する前記表出部間に、突出部を一体で形成することを特
徴とする半導体装置。 2. A chip is provided on a stage of a lead frame.
Mounted and connected with the internal lead of the lead frame
Then, extend the external leads and package with resin mold.
In a semiconductor device to be packaged, the actual size of the package formed by the packaging is reduced.
Upper resin above and below the external leads relative to the mounting surface
The size of the lower resin of the
Is formed by exposing the exposed portion of the upper resin and is exposed at a difference in size between the upper resin and the lower resin.
The projection is integrally formed between the exposed portions.
Semiconductor device.
の差部分による前記外部リードの前記下面の表出部周辺
の面を、前記上部樹脂に埋設させることを特徴とする請
求項１記載の半導体装置。 3. The size of the upper resin and the lower resin
Around the exposed portion of the lower surface of the external lead due to the difference between
Characterized in that the surface is embedded in the upper resin.
The semiconductor device according to claim 1.
の差部分による前記外部リードの前記一面の表出部周辺
の面を、大きく形成された該上部樹脂又は該下部樹脂に
埋設させることを特徴とする請求項２記載の半導体装
置。 4. The size of the upper resin and the lower resin
Around the exposed portion of the one surface of the external lead due to the difference portion
The surface of the upper resin or the lower resin formed large
3. The semiconductor device according to claim 2, wherein the semiconductor device is buried.
Place.
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3269645A JP2933105B2 (en) | 1991-10-17 | 1991-10-17 | Semiconductor device |
| EP95113975A EP0689241A2 (en) | 1991-10-17 | 1992-10-14 | Carrier for carrying semiconductor device |
| EP19920309366 EP0538010A3 (en) | 1991-10-17 | 1992-10-14 | Semiconductor package, a holder, a method of production and testing for the same |
| US07/961,161 US5475259A (en) | 1991-10-17 | 1992-10-16 | Semiconductor device and carrier for carrying semiconductor device |
| KR92019118A KR960016562B1 (en) | 1991-10-17 | 1992-10-17 | Semiconductor package, a holder, a method for producing and testing for the same |
| US08/441,462 US5666064A (en) | 1991-10-17 | 1995-05-15 | Semiconductor device, carrier for carrying semiconductor device, and method of testing and producing semiconductor device |
| US08/455,909 US5637923A (en) | 1991-10-17 | 1995-05-31 | Semiconductor device, carrier for carrying semiconductor device |
| US08/789,661 US5736428A (en) | 1991-10-17 | 1997-01-27 | Process for manufacturing a semiconductor device having a stepped encapsulated package |
| US08/789,625 US5750421A (en) | 1991-10-17 | 1997-01-27 | Semiconductor device, carrier for carrying semiconductor device, and method of testing and producing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3269645A JP2933105B2 (en) | 1991-10-17 | 1991-10-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05109930A JPH05109930A (en) | 1993-04-30 |
| JP2933105B2 true JP2933105B2 (en) | 1999-08-09 |
Family
ID=17475237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3269645A Expired - Fee Related JP2933105B2 (en) | 1991-10-17 | 1991-10-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2933105B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0823042A (en) * | 1994-07-07 | 1996-01-23 | Fujitsu Ltd | Semiconductor device, its manufacture and mold used for it |
| WO1999052149A1 (en) * | 1998-04-06 | 1999-10-14 | Infineon Technologies Ag | Use of the constructional characteristics of an electronic component as a reference for positioning the component |
| JP5590981B2 (en) * | 2010-06-14 | 2014-09-17 | 三菱電機株式会社 | Semiconductor device |
| JP2013170930A (en) * | 2012-02-21 | 2013-09-02 | Toyota Motor Corp | Electronic component inspection method, electric characteristic inspection device therefor, and terminal of electronic component |
| JP2016032048A (en) * | 2014-07-29 | 2016-03-07 | トヨタ自動車株式会社 | Electromagnetic shield body and box |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01286343A (en) * | 1988-05-12 | 1989-11-17 | Mitsubishi Electric Corp | Resin sealed type semiconductor device |
-
1991
- 1991-10-17 JP JP3269645A patent/JP2933105B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05109930A (en) | 1993-04-30 |
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