JP2894705B2 - Synchronous signal multiplex transmission method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a synchronous signal multiplex transmission system for multiplexing and transmitting a plurality of synchronized digital signals.

[Conventional technology]

Conventionally, when a plurality of frequency-synchronized digital signals are multiplexed and transmitted, as shown in FIGS. 4 (a) to 4 (c), n (N: a natural number of 2 or more) digital signals are converted into one. In general, a method of arranging synchronization pulses at appropriate intervals in order to enable identification of n digital signals when multiplexing and demultiplexing is performed is widely used. Used.

In FIG. 4, which is a diagram showing signal waveforms of a multiplexing method which has been widely used in the past, C ₁ ... C _n are n synchronization signal sequences, and C is a signal sequence after multiplexing. is there. Note that the hatched portions indicate frame synchronization pulses.

When transmitting a multiplexed signal, conversion to an appropriate transmission line code is performed in order to secure stable transmission quality in digital transmission.

[Problems to be solved by the invention]

In the conventional multiplexing method and transmission method described above, since a frame must be formed and a synchronization pulse needs to be inserted in a multiplexed signal in a time-division manner, a speed conversion circuit that increases the clock pulse speed by the amount of the synchronization pulse insertion. , A frame generation circuit and the like are required, and the circuit configuration becomes complicated.

Further, since the demultiplexing function and the encoding / decoding function are performed independently, there is a problem that the circuit scale is increased in this respect.

[Means for Solving the Problems] The synchronous signal multiplex transmission method of the present invention is characterized in that, for n (n: 2 or more natural numbers) digital synchronous signals, a specific one digital synchronous signal is used as it is. After converting the signal other than the one digital synchronization signal into a biphase code,
The n signals are multiplexed and transmitted for each block of the biphase code.

On the receiving side, based on a timing signal obtained by comparing an exclusive OR output of an input signal from the transmitting side with a 1-bit delayed signal of the input signal and a predetermined frame pattern signal, The first one bit of one block of the bi-phase coding unit multiplexed on the input signal is read out, and the n digital synchronization signals are sequentially decoded based on the time position of the block in the frame. Output.

[Operation] In the present invention, biphasic code conversion is performed on multiplexed signals other than a specific one of n digital synchronization signals.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

 FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 ₁ , 1 ₂ ... 1 n are input terminals to which synchronized input digital signals are applied, and 2 ₁ , 2 ₂ ... 2 n are synchronized from these input terminals 1 ₂ , 1 _3. Baifuezu encoding circuit for converting the Baifuezu codes to the 2~n th signals except the first-th input digital signal, 3 a signal from the Baifuezu encoding circuit 2 _1, 2 ₂ · · · 2n A multiplexing circuit 4 for multiplexing one block of the biphase code is a transmission line.

Then, for the n digital synchronization signal sequences, a signal other than a specific one signal sequence is converted into a biphase code, and then the n signal sequences are multiplexed and transmitted for each block of the biphase code. I have.

5 is a synchronization circuit, 6 is a separation circuit, 7 is a timing signal,
8 _1, 8 ₂ ··· 8n are output terminals of the synchronizing signal output is obtained.

2 (a) to 2 (d) show the multiplexing circuit 3 in FIG.
FIG. 3 is a diagram showing input / output signal waveforms of FIG.

In FIG. 2, A ₁ , A ₂ ...
And A is the output signal waveform of the multiplexing circuit 3.

3 (a) to 3 (c) are diagrams showing signal waveforms associated with synchronization detection on the receiving side.

In FIG. 3, A is the separation circuit 6 in FIG.
B is a signal obtained by calculating the exclusive OR of the input signal A and the one-bit delayed signal of the input signal A, and F is a frame pattern signal generated by the synchronization circuit 5 in FIG.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIGS.
This will be described with reference to the drawings.

First, the synchronized input digital signals applied to the n input terminals 11 ₁ to 1n are used as biphasic encoding circuits 21, 22 ₂ ... 2n for the _{second to} n-th signals except the _first . Is converted into a biphasic code. These signals are applied to the multiplexing circuit 3 and the biphase code 1
It is multiplexed for each block, that is, for each time slot of the original signal. A _1, A ₂ ··· An of FIG. 2 shows the input signal to the multiplexing circuit 3. If the coding rule of the biphase code is defined as shown in the following table, the output of the multiplexing circuit 3 shown in FIG. Only this is a signal sequence in which a coding rule violation (CRV) has been applied, and this signal can be transmitted to the transmission line 4 as it is.

Next, on the receiving side, in the synchronization circuit 5 shown in FIG. 1, if the exclusive OR of the reception signal A, which is the output signal of the multiplexing circuit 3, and the one-bit delay signal of the reception signal A is obtained, As shown in the signal B of FIG. 3, a signal sequence giving a fixed "1" (1 in the time slot corresponding to the first input signal) for each bit is obtained according to the biphase coding rule. . By comparing this with the frame pattern signal F (see FIG. 3) generated by the synchronization circuit 5, the frame synchronization and the block synchronization used for decoding the biphase code can be simultaneously obtained.

The separation circuit 6 controls the n output signals in accordance with the timing signal 7 thus obtained. At the same time, it is necessary to read out only the information of the first half time slot in one block of the biphase code. Thus, decoding can also be performed.

As described above, on the receiving side, by detecting the coding rule, the frame synchronization and the block synchronization can be simultaneously established, and the separation circuit 6 can also decode the transmission line code. Then, the output terminal 8 _1, 8 ₂ ··· 8n synchronizing signal output is obtained.

〔The invention's effect〕

As described above, according to the present invention, a signal that satisfies the biphase code rule suitable for signal transmission is obtained by performing biphase code conversion and multiplexing on one of n digital synchronization signals other than a specific one. Can be Furthermore, since the receiving side can simultaneously establish the frame synchronization and the block synchronization, and can simultaneously decode the transmission line code in the demultiplexing circuit, the circuit scale of the encoding / decoding circuit, the demultiplexing circuit, etc., must be significantly reduced. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing input / output signal waveforms of the multiplexing circuit in FIG.
FIG. 3 is a diagram showing a signal waveform associated with synchronization detection on the receiving side, and FIG. 4 is a diagram showing a signal waveform of a multiplexing method generally used in the prior art. 2 _{1 to} 2n: biphase encoding circuit, 3: multiplexing circuit, 4: transmission line, 5: synchronous circuit, 6: separating circuit.

Claims (2)

(57) [Claims] 1. For n digital synchronization signals (n: 2 or more natural numbers), one specific digital synchronization signal is converted as it is into a biphase code except for the specific one digital synchronization signal. And a method of multiplexing and transmitting n signals for each block of the biphase code. 2. The synchronous signal multiplex transmission system according to claim 1, wherein the receiving side receives an input signal from the transmitting side and one of the input signals.
Based on a timing signal obtained by collating an exclusive OR output with a bit delay signal and a predetermined frame pattern signal, one block of the bi-phase coding unit multiplexed on the input signal is output. A synchronous signal multiplexing transmission system, wherein the first one bit is read out, and the n digital synchronization signals are sequentially decoded and output based on a time position of the block in a frame.