JPS61274438A - System for time division multiplex digital transmission - Google Patents

Abstract

PURPOSE:To simplify and economize a transmission equipment by performing a multiplexing and, at the same time, a dipulse conversion and also the insertion of a synchronizing signal at a parallel/series conversion part, performing a demultiplexing and a dipulse reverse conversion at a serial/parallel conversion part and performing a synchronous detection control at a low speed area. CONSTITUTION:At a transmission side 11, each of the digital signals CH1-CHn of the first - the n-th channels from input terminals 31-3n is supplied respectively to the first, the 3rd, ... the 2n-1th input terminals 11, 13,...12n-1 in a parallel/series converter 12 and also, each of the supplemental code signals is supplied respectively to the second, the fourth, ... the 2nth input terminals 12, 14,...12n through the respective inverter. However, one input terminal, for example, the 2nth input terminal 12n supplies a specified fix pattern signal from a specified fix pattern generator 22. At a receiving side 17, a clock separated from a serial/parallel conversion part 19 is supplied to a specified fix pattern generator 36 and with synchronizing the clock, a specified fix pattern signal same as the one of the transmission side 11 is generated and is supplied to a synchronous detection circuit 35 and the phase of demultiplexing in the serial/parallel conversion part 19 is controlled so that both inputs are to be allowed to coincide.

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention relates to a time division multiplexing digital transmission system that time division multiplexes and transmits digital signals of n channels (n is an integer of 2 or more), and particularly relates to a transmission code. In order to add DC balance, a dipulse (1) ipulse) is used on the transmitting side.
It relates to a transmission system that performs code conversion and decodes it on the receiving side. Dipulse code conversion means converting an input digital signal from "1" to 10" (or 01"), and from "o" to "01" (or "10").

"Prior Art" In the conventional time division multiplex transmission system of this type, as shown in FIG. 1 to n-th input terminals II to 1n respectively to obtain a time-division multiplexed multiplexed signal from the output terminal 13, the multiplexed signal is converted into a dipulse code by a dipulse converter 14, and the dipulse code is converted into a dipulse code. A coding rule violation device 15 periodically causes a coding rule violation for a specific channel in order to identify the channel, thereby inserting a synchronization signal and sending it to a transmission path 16.

On the receiving side 17, the received signal is input to a coding rule violation detector 18 to detect a coding rule violation and identify the synchronization signal, and its output is supplied to a serial/parallel converter 19, and the coding rule violation detector 18 corrects the sign rule violation in the input signal and supplies it to the dipulse inverse converter 21, and the inversely converted output is sent to the serial-parallel converter 19 in synchronization with the identified synchronization signal to
Separated into output terminals 2, ~2n, these output terminals 2, ~2n
n is the digital signal C of the first to n-th channels on the transmitting side;
H1~CH, are obtained.

``Problems to be Solved by the Invention'' However, in this conventional method, dipulse conversion, insertion of synchronization signals due to violation of coding rules, detection of violation of coding rules, and inverse dipulse conversion are all performed on multiplexed signals. This has the drawback that the high-speed processing section is large and its configuration is also complicated.

There is a conventional method for transmitting a frame along with code conversion, but in this case, the circuit configuration becomes even more complicated and the transmission line speed increases.
Not suitable for high-speed transmission systems.

An object of the present invention is to provide a time division multiplexing digital transmission system that performs processing as slowly as possible, has a simple circuit configuration, allows channel identification, and can correctly decode any information signal. .

"Means for Solving the Problems" According to the present invention, on the transmitting side, digital signals of the first to n-th channels are converted to the first channel of the parallel-to-serial converter. Third...
, 2n-1 input terminals, respectively, and the complementary code signals of the first to n-th channel digital signals are supplied to the second, fourth . . . . are supplied to the second n-th input terminals, respectively. The first ((k=1,...) of the 2n input terminals of the parallel-to-serial converter.

211) The input terminal supplies a special fixed pattern signal in place of the signal supplied thereto. The multiplexed signal output from this parallel-to-serial converter is transmitted. At this time, in the multiplexed signal, all digital signals of each channel other than the channel to which the above-mentioned input terminal is supplied are dipulse codes.

On the receiving side, the received multiplexed signal is supplied to the serial/parallel converter, and the multiplexed signal is separated and outputted to the first to second n output terminals using the clock of the multiplexed signal.

Further, the special fixed pattern signal is generated in synchronization with the clock of the separated and outputted signal, and the conversion phase of the serial/parallel converter is controlled so that the special fixed pattern signal and the output signal of the output terminal match. .

In this way, in this invention, parallel-serial conversion and multiplexing are performed on the transmitting side, and dipulse conversion is performed at the same time, and dipulse inverse conversion is performed simultaneously with serial-to-parallel conversion and demultiplexing on the receiving side, and a synchronization signal is inserted.

Since synchronization on the receiving side is not performed for multiplexed high-speed signals, the number of low-speed processing circuits increases.

Embodiment FIG. 1 shows an embodiment of the present invention. In the present invention, on the transmitting side 11, the digital signals CH1 to CH1 of the first to nth channels from the input terminals 3□ to 3n are converted to parallel-to-serial converters, respectively. 12 1st, 3rd, ..., 2nd n-1
Input terminal 1□, 18. ......, 1□. -1 and the complementary code signals are supplied to the second, fourth, .
r 14 #..., 1□. supplied to Ta\
゛What about that one input terminal? G2n input terminal 1
□. supplies a special fixed pattern signal from the special fixed pattern generator 22 in place of the signal supplied thereto.

FIG. 2 shows a case where n=3 as a specific example of the parallel-to-serial converter 12. The first to sixth input terminals are each connected to an AND circuit 4.
- One input end of 46 (= connected.

On the other hand, the D-type flip-flops 23 to 25 and the NOR circuit 5
1 to 56 constitute a hexadecimal counter 26, and when a clock CLK as shown in FIG. The clocks 01 to C6, which are divided into one-sixths, are obtained. These branch clocks 01-C6 are supplied to the input terminals of the AND circuits 41-46.

The respective outputs of the AND circuits 41 to 46 are combined by the OR circuits 31 to 33, and the combined output is timed by the clock of the terminal 27 in the D-type flip-flop 34, and is sent to the output terminal 1.
3, a multiplexed signal is obtained.

Digital signals CH of the first to third'f channels.

If CH2, CH, are given the codes as shown in FIG. 3, the multiplexed signal Dn at the output terminal 13 is obtained by sequentially time-division multiplexing the digital signals CH1, 0H2, CH8 using the clock CLK as shown in FIG. The output is the same as the one obtained by converting each bit into a Gui pulse.

Each channel can be separated on the receiving side (the special fixed pattern signal CHS from the special fixed pattern generator 22 is input to a specific input terminal of the two-parallel-to-serial converter 12, for example, the sixth input terminal 16 in FIG. 2). , for example, a repeating signal having a pattern of ``10'' is supplied in place of the complementary code signal τm of the third channel digital signal CH3.

In this case, the output of the output terminal 13 becomes the multiplexed signal width (FIG. 3). The signal thus obtained, which is multiplexed and made into a GUI pulse code and also includes a synchronization signal (special fixed pattern signal), is sent to the transmission line 16 as shown in FIG. 1 (-).

On the receiving side 17, as shown in FIG. 1, the received signal is supplied to the serial/parallel converter 19, and the multiplexed signal is outputted to the output terminals 2, 2□ with the clock of the multiplexed signal'. separated into The serial-to-parallel converter 1 corresponds to the kth (in this example, 2n) input terminal to which the special fixed pattern signal CH was supplied on the transmitting side 11.
The 9th output terminal is the 2nd nth output terminal 2□ in this example. The output of is supplied to the synchronization detection circuit 35. On the other hand, the clock of the separated output signal from the serial/parallel converter 19 is supplied to the special fixed pattern generator 36, which generates the same special fixed pattern signal as the special fixed pattern signal CHS of the transmitting side 11 in synchronization with this clock, This special fixed pattern signal is supplied to the synchronization detection circuit 35, and the phase of demultiplexing of the serial/parallel converter 19 is controlled so that both inputs match.

If the two inputs in the synchronization detection circuit 35 do not match, the serial/parallel converter 19 repeats hunting for each bit of the received signal by inhibiting one bit of the clock used for the conversion. Detect correct channel synchronization position.

The state of this operation is illustrated in FIG. In this case, the number of channels n is 3, and A in the figure shows channel signals CH1°CH,,C
H8 is all lIO” (01 in Thai Pulse)
, B in the same figure shows the case of O/L/(all) 1" (10 with di-pulse), and the special fixed pattern signal CH, is "
This is the case for 10' repetitions. Since n=3, the pattern obtained at the output terminal 26 is checked every 6 bits of received data. In other words, the pattern extracted at the point of arrow A1 in the same figure is oo
oo-..., special fixed pattern signal 1010
. . . does not match, so the demultiplexing is shifted by 1 bit and extracted at the arrow point shown in A2 in the same figure.
111..., which also does not match the special fixed pattern signal, so the signal is further shifted by 1 bit, and the same thing is done. “1010...” when the status is
Therefore, channel separation is performed correctly and it is determined that the synchronization state is established.

FIG. 5 shows an example of the configuration of the special fixed pattern generator 22 or 36. This is a well-known frequency divider by 2, and a clock CLKB obtained by clock CLK for 6 minutes is inputted to a terminal 37, and a special fixed pattern signal CHS is obtained at an output terminal 38 by dividing the clock CLKB into 2 minutes.

FIG. 6 shows an example of the circuit configuration of the synchronization detection circuit 36 provided on the receiving side. An exclusive OR of the output separated to the output terminal 26 and the special fixed pattern signal of the special fixed pattern generator 36 is performed, and if the two do not match, 111 is output to the output terminal 39.
Outputs 11.

FIG. 7 shows an example of the circuit configuration of the serial-to-parallel converter 19 on the receiving side, where n=3. The received multiplexed signal name from the terminal 41 is supplied to a 6(2n) IR shift register 42, and the shift register 42 is shifted by the multiplexed signal cylinder clock from the terminal 43. shift register 4
The outputs of each shift stage of 2 are connected to latch circuits 61 to 66, respectively.
supplied to

On the other hand, the clock at the terminal 43 is transmitted through a clock control section 44 to a frequency dividing circuit 4 which has three stages of D-type flip-flops connected in cascade.
5, and the rising edge of each Q output abc and Q output def of the three flip-flops causes a latch circuit 6
Data is taken in for ~66. Each output of latch circuits 61-66 is supplied to output terminals 21-26, respectively. Note that the output f of the minute circuit 45 is supplied as the manual clock for the special fixed pattern generator 36.

When the synchronization detection circuit 35 detects a mismatch, the clock control unit 44 inhibits one bit of the clock supplied to the frequency dividing circuit 45 based on the output from its output terminal 39. For this reason, synchronous control is performed as explained with reference to FIG. 4, and the output terminals 28.23.2. 1st. Digital signals CH1, CH2, CH of the second and third channels are obtained, and a special fixed pattern signal CHs is obtained at the output terminal 26.

A special fixed pattern signal CHs is inserted to enable channel synchronization, but as a result, the transmission line code sequence becomes different from a pure GUI pulse code sequence, and in the worst case, the number of consecutive same codes becomes 4 pits (for example, the 4th In the figure, there are 3 consecutive bits of the same sign). However, this degree of continuation of the same code has little effect on clock reproduction on the receiving side, and the clock can be correctly reproduced. Further, the special fixed pattern is not limited to a 2-bit pattern, but a fixed pattern of 3 or more bits may be used. It is convenient to insert the special fixed pattern signal CHs by supplying it to the terminal to which the complementary code is supplied as described above.

"Effects of the Invention" As explained above, according to the present invention, the parallel-to-serial converter 1
Dipulse conversion and synchronization signal insertion are performed at the same time as multiplexing in step 2, and demultiplexing and demultiplexing and inverse conversion are performed in the serial/parallel converter 19. Synchronization detection control is also performed in the low-speed region, and the transmitter and receiver In both cases, multiple synchronization can be performed almost only in the low-speed range, and the configuration is simple, so there is an advantage that the transmission device can be simplified and made more economical.

By implementing the present invention, the uplink multiplexing circuit becomes simple, so it becomes easy to multiplex a plurality of synchronous low-speed signals and transmit them onto one line, and the efficiency of using one line can be increased. For example, computer-to-computer communication, or LS
Effective for communication between I-packages.

Furthermore, in the conventional multiplexing and dipulse code conversion transmission system,
In the case of all "0" or all @1', it is impossible to distinguish between all "0" and all @1' without detecting the first bit of the received signal, but in this invention, a special fixed pattern signal is used. All @0” to perform channel synchronization
Or, even in the case of all "1#", it is possible to decode correctly. Also, the output terminal zi (i=i l 3 t
.......

3n-1) and the complementary code output terminal 21+1 always yields 11'', so this property can also be used to monitor errors in the transmission path.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of the time division multiplexing digital transmission system of the present invention, FIG. 2 is a logic circuit diagram showing an example of the circuit configuration of the parallel-to-serial converter 12 in FIG. 2 is a time chart showing examples of operation waveforms of each part in FIG. 4, FIG. 4 is a diagram for explaining channel synchronization operation on the receiving side, FIG. 5 is a diagram showing a specific example of the special fixed pattern generator 22, FIG. 6 is a diagram showing a specific example of a synchronization detection circuit, FIG. 7 is a diagram showing a specific example of the serial-to-parallel converter 19 in FIG. 1, and FIG. 8 is a block diagram showing a conventional time division multiplexing digital transmission system. It is a diagram. 1□~1□n: Input terminal of parallel-serial converter 12, 2, ~2
□n: Output terminal of serial-parallel converter 19, 31 to 3n: first
~nth channel input terminal, 12: Parallel-serial converter, 16:
Transmission line, 19: Serial-to-parallel converter. 22.36: Special fixed pattern generator, 35: Synchronization detection circuit. Patent applicant: Nippon Telegraph and Telephone Corporation Representative: Taku Kusano 1 Figure E6 Injured side tree 30 - Clear surface Q171' CH1CH+ CH2CH2CH3CH'
i CH+ CH+ CH2CH2CH3cHs CH
1 cow 4 circles 1 = Ya 5 figure 3176 decoy Ya 7 times

Claims (1)

[Claims] (1) On the transmitting side, the digital signals of the first to nth channels (n is an integer of 2 or more) are converted to the first, third, ..., parallel-to-serial converter having 2n input terminals. 2n-1 input terminals respectively, and the complementary code signals of the digital signals of the first to nth channels are supplied to the second and
4th, . . . , 2n-th input terminals, one
, 2, ..., 2n) Supplying a special fixed pattern signal to the input terminal in place of the signal supplied thereto, transmitting and receiving the multiplexed signal output from the parallel-to-serial converter. The side receives the transmitted multiplexed signal and supplies it to the input terminal of the serial-to-parallel converter having 2n output terminals, and converts the multiplexed signal into the serial-to-parallel converter in synchronization with the clock of the multiplexed signal. Separately output to the first to second n output terminals of the section,
The serial-to-parallel converter generates the special fixed pattern signal in synchronization with the clock of the separated output signal, and converts the serial-to-parallel converter so that the special fixed pattern signal matches the output signal of the first output terminal of the serial-to-parallel converter. A time division multiplexing digital transmission method that controls the conversion phase of