JPH0738649B2 - Asynchronous data conversion circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous data conversion circuit, and more particularly to an asynchronous data conversion circuit for transmitting asynchronous data via a synchronous data communication line.

[Conventional technology]

Conventionally, a multipoint sampling data transmission system has been used when transmitting asynchronous data via a synchronous data communication line which is not synchronized with this. However, in the multipoint sampling transmission method, in order to reduce code distortion,
The bit rate of the line must be made sufficiently higher than the bit rate of the start-stop data, which causes a problem of low transmission efficiency. In order to solve this difficulty, the bit rate of the start / stop data is made the same as the nominal value of the bit rate of the line, and the phase control of the start / stop data sample timing is performed when the start bit of the first word of the start / stop data is detected. A start-stop synchronous data conversion circuit has been proposed in which a data value sampled at the data bit rate is transmitted at the bit rate of the line, and the receiving side also performs similar sampling (for example, Japanese Patent No.
The circuit described in the specification. [Problems to be Solved by the Invention] In the above-described conventional asynchronous data conversion circuit, since both the start and end bit rates of the start-stop data and the line have the same nominal value, they are in an asynchronous relationship. As the transmission time elapses after the phase control of the sampling timing, the phase shift due to the accumulation of errors between both bit rates increases. As a result, the receiving side receives data in which bits are missing or extra bits are inserted in the middle of the start-stop data input by the transmitting side. In order to avoid this bit loss or insertion, it is necessary to limit the length of the start / stop data in advance.

That is, in the conventional asynchronous data conversion circuit, there is a restriction that both the start data and the bit rate in the line must be set to the same nominal value, and the data length that can be transmitted has an upper limit. There is a problem.

An object of the present invention is to solve the above problems and provide an asynchronous data conversion circuit capable of transmitting asynchronous data at a desired line bit rate higher than its bit rate and having no restriction on the transmittable data length. To do.

[Means for solving problems]

The circuit of the present invention receives start-stop data of a predetermined first bit rate consisting of words each having a start bit and a stop bit at a front end and a start bit, and receives the start-stop synchronous data of at least one predetermined number. Converting into line data having a predetermined second bit rate higher than the first bit rate for each data division divided into each word, and inserting a predetermined stuffing bit into an empty bit generated by the conversion. A first conversion circuit for transmitting and a time interval of the start bit at the front end of the data section included in the line data, which receives the line data, removes the stuffing bit contained therein The time width of only the stop bit at the end of the data section is changed according to the length of the data segment, and the bandwidth is substantially equal to the first bit rate. And a second conversion circuit for reproducing and transmission of the asynchronous data trait comprises.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation.
In FIG. 1, the conversion circuit 1, the transmission input control circuit 3, and the transmission output control circuit constitute a transmission unit, which converts data (1) that is start-stop synchronization data into line bit rate data (2). , To the receiver via the line. The conversion circuit 2, the reception input control circuit 5, and the reception output control circuit 6 constitute a reception unit, and the data (2) sent from the transmission unit via the line is reconverted into data (3) which is start-stop synchronization data. Convert and send.

The data (1) is a sequence of words in which a start bit (ST) is added to the beginning of a character consisting of m bits and a stop bit (SP) is added to the end thereof, and is sent at a predetermined bit rate. FIG. 2 illustrates the case where m = 8. The data (1) is sent to the flip-flops (FF) 10-1 to 10-m of the conversion circuit 1 and also to the transmission input control circuit 3. When detecting the ST of data (1), the transmission input control circuit 3 generates signals φ ₁ to φm indicating the timing (transmission input timing) at which the FFs 10-1 to 10-m read the character bits b ₁ to bm, respectively. At the same time, a trigger signal is generated which causes a pulse to rise when a predetermined time τ _{1 has} passed from the leading edge of ST of data (1). FF10-1 to 10-m are signals φ, respectively.
The signal of the data (1) at the time of the pulse rise of ₁ to φm, that is, the character bits b ₁ to bm are read and sent to the multiplexer 11 while being held until the pulse rise of the signal φ ₁ to φm appears. On the other hand, the transmission output control circuit 4 counts the pulses of the clock signal having the line bit rate to select the selection signal (D ₁ ) from the input signal group of the multiplexer 11 one by one. Occur. The line bit rate is set higher than the bit rate of data (1). The value of the selection data (D ₁ ) is reset to the value “0” at the first clock pulse after the rising edge of the trigger signal pulse, and then the value is “m +
After reaching "1" (value "9" in FIG. 2), the step is stopped. The time τ ₁ may be set so that the step to the value “m” of D ₁ is made after the reading timing of the signal φm. To the multiplexer 11, signals indicating start bits (ST) and stop bits (SP) are input in addition to the signals sent from the FFs 10-1 to 10-m.
The multiplexer 11 selects and sends ST when the value of D ₁ is “0”, and receives the signals received from FF10-1 to 10-m when the value is “1” to “m”, respectively. Send out,
When the value is "m + 1", SP is transmitted. Therefore, when the bit rate, that is, the line bit rate, of the data (2) transmitted by the multiplexer 11 is higher than the bit rate of the data (1), the frame format in which SP is inserted after the data for one word is inserted. become.

The conversion circuit 2 of the reception unit has the same circuit configuration as the conversion circuit 1 of the transmission unit. The reception input control circuit 5 receives the data (2) sent from the transmission unit, extracts the timing, and when ST is detected, the signal θ ₁ indicating the timing (reception input timing) for reading the character bits b ₁ to bm. Through θm, a reset signal indicating the timing of change from SP to ST is generated. On the other hand, the reception output control circuit 6 generates the selected data (D ₂ ) by counting the pulses of the clock signal having the same nominal bit rate as the data (1). The value of the selected data (D ₂ ) is reset to the value “0” when a predetermined time τ _{2 has} elapsed from the leading edge of the ST of the data (2), and then the value is incremented by one for each clock pulse. After that, the step is stopped after reaching the value "m + 1". Note the time tau ₂ is previously set to be after than read timing stepping the signal theta ₁ to D ₂ of the value "1". The data (3) transmitted by the conversion circuit 2 in accordance with the selected data (D ₂ ) is ST when the value of D ₂ is “0”, and the character bit b ₁ or the character bit b ₁ when the value is “1” to “m”, respectively. bm and the value "m +"
It becomes SP at 1 ”.

The number of bits of each frame of data (2), that is, the number of bits from each ST to immediately before the next ST is relative to the central value because both timings of data (1) and data (2) are asynchronous. Increase or decrease 1 bit. On the other hand, in the data (3), ST and character bit b ₁
Each of bm to bm appears at the timing synchronized with the clock pulse having the same nominal bit rate as that of the data (1), and only the time width of SP is uneven in each word. Explaining this point in a little more detail, the data (2) and the reset signal are synchronized, but the data (2) and the selected data (D ₂ ) are not synchronized. Therefore, the rising time of the reset signal does not coincide with the rising or falling of each bit of the selection data (D ₂ ). That is, the value "9" of the selection from the rise of the reset signal after tau ₂ data (D ₂₎ for (stop bit support) is completed, when the reset signal is up standing simultaneously the value "9" of the stop bit The width becomes τ ₂ , and if the reset signal rises just before the end of the value “9”, the width of the stop bit becomes (1 bit + τ ₂ ),
It will be uneven. The bit rates of the data (1) and the data (3) have the same nominal value, but there is some error between them in actual operation. The influence of this error is also absorbed by the increase or decrease of the time width of SP for each word of the data (3), and the code distortion of ST and the character bits b ₁ to bm is not deteriorated.

As described above, the transmitter inserts a stuffing bit (SP) between words of asynchronous data, converts it to higher-speed synchronous data, and sends it. The receiver also stuffs bit (SP). Is removed to reproduce the asynchronous data, and by changing the time width only for the stop bit (SP) of each word after the reproduction, the asynchronous data can be transmitted on the line at a higher desired bit rate. In addition, it is possible to eliminate the accumulation of errors between the bit rates of the start and end data of the transmission unit and the reception unit for each word, and to continue the line transmission without being restricted by the transmittable data length.

In this embodiment, stuffing and destuffing are performed for each word to make the time width of the stop bit of each word variable in the reproduction data of the receiving unit. However, a predetermined number of words Each is divided into frames, and staff and destuff are performed for each frame.
It is easy to change so that only the time width of the stop bit at the end of each frame of playback data is variable,
It is clear that the same effect as that of this embodiment can be obtained.

〔The invention's effect〕

INDUSTRIAL APPLICABILITY As described above, the present invention has an effect that it is possible to realize an asynchronous data conversion circuit capable of line transmission of asynchronous data at a desired bit rate higher than that and having no restriction on the transmittable data length. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining the operation of the embodiment of the present invention. 1,2 ... Conversion circuit, 10-1 to 10-m ... Flip-flop (FF), 11 ... Multiplexer, 3 ... Transmission input control circuit, 4 ... Transmission output control circuit, 5 ... Reception input control Circuit, 6 ... Reception output control circuit.

Claims (1)

[Claims] 1. A predetermined first comprising a word having a start bit and a stop bit at a leading end and a trailing end, respectively.
A second bit rate which is higher than the first bit rate for each data segment obtained by receiving the asynchronous data of the bit rate of at least one predetermined number of the words A first conversion circuit for converting the line data having the line number and inserting a predetermined stuffing bit into a vacant bit generated by the conversion and transmitting the stuffing bit; and the stuffing bit included in the line data for receiving the line data. And a second conversion circuit for reproducing and transmitting the start-stop synchronization data having a bit rate substantially equal to the first bit rate by varying the time width of the stop bit. A start-stop synchronous data conversion circuit.