JPS63131642A - Data signal reproducing method - Google Patents

Abstract

PURPOSE:To reproduce a signal suitable for data transmission where delay fluctuation is suppressed by adding information representing the time with varied level to a generated signal. CONSTITUTION:The level of a binary data signal is sampled at an equal time interval and converted into a binary logic code corresponding to the level. When the binary logic code differs, the change in the level of the binary data signal takes place between times sampling the level. On the other hand, the sampling time interval is divided by plural finer times and the time of occurrence of level change is made corresponding to the divided time and the combination of the binary logic codes corresponding respectively to each divided time are preset. The combination of the binary logic codes representing the occurrence time of the level change is added in succession to the binary logic code representing the change in the level of, e.g., the binary data signal. Thus, the time when the level change of the binary data signal takes place is grasped accurately and the delay fluctuation is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission system for multiplexing and transmitting digital data. In particular, it relates to a transmission system without delay fluctuations.

〔overview〕

The present invention provides a method in which a level value of a binary data signal is sampled to correspond to a binary logic code, and a frame made up of a predetermined number of binary logic codes is converted into a signal corresponding to the binary data signal. By adding information indicating the time at which the level value changed to the generated signal, it is possible to reproduce a signal suitable for data transmission with suppressed delay fluctuations.

[Conventional technology]

As a conventional data transmission method, if a modulation/demodulation device is used to convert the data into an analog signal, and this analog signal is multiplexed and transmitted using an analog multiplex conversion device, transmission with little delay variation is possible although there is an absolute delay. Similarly, even if an analog signal is converted from analog to digital, multiplexed using a digital multiplex converter, and then transmitted, transmission with little delay variation is possible.

[Problem that the invention seeks to solve]

In such conventional data transmission systems, in order to reduce delay fluctuations, a PG band or G band modem is used to convert the signal into an analog signal, which is extremely inefficient when considering the band and data rate.

There is also a method of simply sampling data and transmitting it digitally, but this method has the drawback of causing delay fluctuations due to sampling distortion.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data signal reproducing method in which occurrence of delay fluctuations caused by sampling distortion due to simple sampling is suppressed.

[Means for solving problems]

The present invention provides a method for configuring a frame of a predetermined number of binary logic codes corresponding to level values of a binary data signal sampled at equal time intervals and reproducing a data signal corresponding to the binary data signal. The time at which the level value changes corresponds to the time when the sampling time interval is quantized at a finer time interval, and a predetermined number of binary logic codes corresponding to this quantized time are set to a binary logic code indicating the change in the level value. It is characterized by being added successively to the code.

[For production]

The level value of the binary data signal is sampled at equal time intervals and converted into a binary logic code corresponding to this level value. Therefore, if the values of the binary logic codes are different, this means that a change in the level value of the binary data signal has occurred between the times when this level value was sampled.

On the other hand, the sampling time interval is divided into a plurality of smaller times, and the time at which the level value change occurs corresponds to this divided time.

Further, combinations of binary logic codes corresponding to each of the divided times are set in advance.

A combination of binary logic codes indicating the time of occurrence of this level value change is successively added to, for example, a binary logic code indicating a change in the level value of the binary data signal.

As a result, the time when the level value change of the binary data signal occurs can be accurately grasped, and even if coarse sampling is used, delay fluctuations are suppressed to the same extent as when fine sampling is performed.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a time chart showing the operation of this embodiment.

First, the configuration of this embodiment will be explained based on FIG. This embodiment includes a pulse pattern generator 1, an encoder 2,
The pulse pattern generator 1 generates a frame synchronization pulse and various clocks synchronized with this pulse, and these clocks include a simple sampling clock. The encoder 2 performs simple sampling of input data based on this simple sampling rofuku, performs time quantization to reduce sampling distortion, and further encodes the result. A multiplex converter 3 multiplexes the encoded signals.

Next, the operation of this embodiment will be explained based on FIGS. 1 and 2.

The sampling pulse is synchronized with the frame sync pulse. Here, there are eight sampling pulses A to H in one frame. The next frame also has eight sampling pulses A-H. The input data is sampled with sampling pulses A-H, and the sampling output r000
01111111-------" is obtained. Incidentally, the point of change in the input data is between the sampling pulse D and the sampling pulse E. This period is sampled using a high-speed clock, and the position of the change point is time quantized and encoded. Here, it is encoded with 5 bits (for example, 10110). This encoded output is added immediately after the changed code. Therefore, the output is [0000110
1101111-----J, the bits at the positions of sampling pulses D and E become "01" indicating that there has been a change in the input terminal, and the bits at the positions of sampling pulses F-B become The 5 bits become the code pattern for time quantization. In multiplex converter 3, sampling pulse A
- Multiplex the data corresponding to H onto the corresponding channel of the next frame. On the receiving side, this multiplexed data is output in the order of the frame synchronization pulse of the next frame to the sampling pulses A to H. The decoder starts from “0” to “
It is detected that the sign change to ``1'' occurs between the sampling pulse D and the sampling pulse E, and the 5 bits located at the position of the subsequent sampling pulse FB are regarded as time quantization bits and decoded. Based on this decoding result, data change points between sampling pulses D and E of the next frame are reproduced.

〔Effect of the invention〕

As explained above, the present invention has the advantage of being able to perform data transmission without delay fluctuations, although there is an absolute delay.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a time chart showing the operation of the embodiment of the present invention. 1...Pulse pattern generator, 2...Encoder, 3.
...Multiple converter.

Claims (1)

[Claims] (1) In a method for configuring a frame of a predetermined number of binary logic codes corresponding to the level value of a binary data signal sampled at equal time intervals, and reproducing a data signal corresponding to the binary data signal, the level The time at which the value changes corresponds to the time when the sampling time interval is quantized at finer time intervals, and a predetermined number of binary logic codes corresponding to the quantized time are converted into binary logic codes indicating the change in level value. A data signal reproducing method characterized in that the data signal is continuously added to the data signal.