JP2826162B2 - Signal encoding method and signal conversion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to, for example, transmitting a plurality of data signals based on various kinds of information for each transmission path through one data communication line. The present invention relates to a signal encoding method using time division multiplexing and a signal conversion device.

[Related Art] For example, when a signal based on various types of information for each transmission path is transmitted through one data communication line, a signal based on each information is multiplexed and compressed to increase the efficiency of use of the communication line. ing.

By the way, signal multiplexing is performed by modulating some information using different carrier waves, converting them into signals of different frequencies, and transmitting these signals through one communication line. And a time-division multiplexing method in which a signal of other information is inserted and transmitted in a vacant time between sample points where a signal exists.

Here, the time division multiplexing method according to the present invention will be described with reference to a multipoint sampling method and a fixed index method, which are generally used more frequently than before.

First, in the communication by the multipoint sampling method, the input signal which is the original signal on the transmitting side is sampled at predetermined time intervals by sampling pulses, and all the sampled pulses corresponding to each position of the sampling No. As shown in FIG. 8, the sampling ring is encoded into a pulse represented by 1 bit such as "0" in No. 0, "0" in No. 1, "1" in No. 2, and so on. After that, it is transmitted through a communication line. Then, on the receiving side, the coded pulse is composited to return the signal to the original state and determine the content of the transmitted information.

That is, in this method, the original signal is sampled at certain intervals to perform bit multiplexing.

In contrast, in communication using the fixed index method,
As shown in FIG. 9, a pulse expressed by 3 bits by a combination of “0” and “1” in accordance with a sampling pulse composed of 6 in one section (011, 111 indicates either 0 or 1 state,
The other three-bit coded pulse train indicates a transition point.)
After that, it is transmitted through a communication line. And
On the receiving side, the content of the transmitted information is determined by decoding the encoded pulse again based on the state indicated by each pulse.

That is, in this method, sampling is performed for a fixed time, the position of a change point of the original signal is encoded as change point data, and the encoded data is multiplexed and transmitted.

Conventionally, in a signal converter, when a low-speed asynchronous signal is put on a high-speed synchronous communication line, the low-speed asynchronous signal is converted into a high-speed synchronous signal using a signal converter. On a high-speed synchronous communication line.

FIG. 11 is a block diagram showing an example of a signal conversion device used for performing such signal conversion. In this figure, for the sake of simplicity, only a circuit for converting a low-speed asynchronous signal into a high-speed synchronous signal is shown.

The signal conversion device shown in FIG. 1 includes a plurality of signal conversion units 110 that convert signals of respective input signals, and a communication signal generation unit 111 that fetches code data output from each of the signal conversion units 110 and transmits the code data to a communication line. And

Each signal conversion unit 110 has a “decimal” counter 101 that increments a count result each time a clock signal is supplied, and receives an input signal each time the clock signal is supplied, and reads the value that was previously captured. Change point detection circuit 102 that generates a change detection signal when different
And a data generation circuit 103 that generates code data corresponding to the input signal in "10" clock units based on the output of the change point detection circuit 102, the output of the counter 101, and the input signal. Is initialized when a reset signal is supplied from the communication signal generation unit 111, and thereafter, the input signal is quantized in units of “10” clocks to generate code data, which is supplied to the communication signal generation unit 111. .

In this case, when the change detection signal is supplied from the change point detection circuit 102 before the value “9” is supplied from the counter 101, the data generation unit 103
, And generates code data corresponding to this value based on the code table shown in FIG. 5, and supplies this to the communication signal generation unit 111. Also, when the value “9” is supplied from the counter 101 and the change detection signal is not supplied from the change point detection circuit 102, the data generation unit 103
At this time, while taking in the input signal supplied,
Based on the court table shown in FIG. 6, code data corresponding to the input signal value at this time is generated and supplied to the communication signal generation unit 111.

The communication signal generator 111 first resets each of the signal converters 110 sequentially. Thereafter, each time code data is output from each of the signal conversion units 110, the code data is sequentially fetched to generate communication data, which is transmitted over a communication line.

Therefore, for example, when an input signal as shown in FIG. 14A is input and code data “0001” and “0111” as shown in FIG. 14B are output from the signal converter 110, , The communication signal generation unit 111
A communication signal as shown in FIG. 14 (c) is generated in combination with the code data from (1) and sent out on the communication line.

Although not shown, the circuit that converts the high-speed synchronous signal into the low-speed asynchronous signal is configured by a circuit that performs the reverse operation of the above-described circuit.

[Problems to be Solved by the Invention] By the way, in the multipoint sampling method among the above-mentioned methods, even if a bit error occurs in the encoded pulse as shown by a mark in FIG. If there is no error, it has the advantage that it can immediately return to the original accurate state at that time, but on the other hand, the input signal is regarded as either "0" or "1" at each sampling position. However, even if an input signal is input between each sampling, the input signal is not sampled, and the decoded signal has a very large distortion and lacks fidelity.

On the other hand, in the fixed index method, since the input signal is regarded as a change point, it is possible to reduce the distortion of the signal which has been particularly problematic in the above-described multipoint sampling method. When a bit error occurs in the encoded pulse as shown in FIG.
Until one of the 11,111 pulses arrives, it is not possible to return to the original accurate state, so that an accurate signal is not transmitted to the receiving side, and there is a problem that reliability is lacking.

Therefore, the present invention has been made in view of the above-described problems, and an object of the first invention of the present invention is to reduce the distortion of a signal to be decoded and sufficiently secure the fidelity to the original signal. It is another object of the present invention to provide a signal encoding method capable of returning to an original accurate state in a short time even if a bit error occurs in an encoded signal. Is small, the fidelity to the original signal can be sufficiently ensured, the signal can be sufficiently compressed at the time of encoding, and even if multiple change points occur in the original signal within the same sampling period, It is an object of the present invention to provide a signal encoding method that can reliably extract and process the signal.

By the way, in such a conventional signal conversion device,
In principle, only the change point information of the input signal is transmitted, so if the polarity is incorrectly inverted once due to a transmission error of the high-speed synchronization signal, etc., the logic "0" continuation or logic "1" continuation Until is transmitted, there is a problem that a correct signal cannot be reproduced on the receiving side.

In order to eliminate such inconvenience, it is conceivable to encode the initial level of the input signal and incorporate this into the first bit of the “4” bits. Point information must be shown, and conversion distortion increases.

The present invention has been made in view of the above circumstances,
It is an object of the present invention to provide a signal conversion device capable of preventing the error from being transmitted to the code data of a portion where a transmission error has occurred while preventing a decrease in resolution and minimizing conversion distortion.

[Means for Solving the Problems] In order to achieve the object of the above-described signal encoding method, a first invention of the signal encoding method according to the present invention samples input signals indicating various information data and performs a predetermined section T ₁ in the signal encoding method for encoding processing for each indicates the the status bits SP indicating the level state at the initial position in each section T _1, a change point at a given position corresponding to the input signal within said interval, a plurality The input signal is encoded on the basis of an encoding pulse FP composed of a combination of a change point bit string EDP forming one group by the above bits.

The state the second invention, shown in the signal encoding method for encoding processing for each predetermined interval T ₂ samples the input signal indicating various information data, said level state at the initial position in each section T ₂ A coding pulse FP comprising a combination of a bit SP and a plurality of groups of changing point bit strings EDP and LDP indicating a changing point at a predetermined position corresponding to the input signal in the section and forming one group by a plurality of bits. And encoding the input signal based on

Further, in order to achieve the object in the signal conversion device, the change point position of the input signal in the previous cycle and the subsequent cycle is detected, and the information obtained thereby is bit-compressed, and the polarity of the input signal in the previous cycle is changed. Then, an output signal is generated by combining the detection result and the bit compression result. When the output signal is input, the output signal is processed in a reverse procedure to reproduce the input signal.

[Operation] In the signal encoding system according to the first invention, the input signal indicating various information is input, the input signal is sampled, the code-level state of the initial position in the predetermined interval T ₁ is as bit SP Be transformed into Further, the pulse change point of the input signal in each section T ₁ is encoded as a change point bit sequence EDP constituting the one group of a plurality of bits, is coded based on a combination of these status bits SP and change point bit sequence EDP Is transmitted through a communication line.

Further, in the signal encoding method according to the second invention, when an input signal indicating various information is input, the input signal is sampled, the code as a level state status bit SP of the initial position in the predetermined interval T ₂ Be transformed into Furthermore, each section T ₂
Are changed into a plurality of groups as change point bit strings EDP and LDP forming one group by a plurality of bits, and are coded based on a combination of these state bits SP and the change point bit strings EDP and LDP of the plurality of groups. The converted pulse is transmitted through a communication line.

[Embodiment] The signal encoding method according to this embodiment is applied, for example, when transmitting a plurality of data signals (input signals) based on various information for each transmission path through one data communication line. Signal processing by division multiplexing is performed.

That is, in the signal encoding method according to this embodiment, sampling is performed for a fixed time, the position of the change point of the input signal which is the original signal is encoded as change point data, and each of the encoded data is multiplexed. And transmitted through one data communication line.

Further, the processing of processing an input signal by this encoding method will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing one embodiment of a signal encoding method according to the present invention, and is a diagram showing signal waveforms at the time of each processing.

In this signal encoding method, when an input signal as an original signal is input as shown in FIG. 1 (c), one section T1 becomes 6 based on a predetermined sampling frequency as shown in FIG. 1 (d). Sampling is performed for each sampling number by a sampling pulse EP composed of bits (E1 to E6). This allows
The position of the change point of the input signal is extracted. Then, the position of the change point by each data is represented by a change point bit string EDP forming one group by 3 bits as shown in FIG.

In this embodiment, 001 (change point at E1), 010 (change point at E2), 011 (change point at E3), 100 (change point at E4), 101
(Change point at E5), 110 (change point at E6), 111 (no change), the change point position is represented by seven kinds of change point bit strings EDP.

Furthermore, there is one bit of status bit SP is in front of the leading bit ED1 at the change point bit string EDP described above, the input signal at the initial position at the start of the status bit SP Each interval T ₁ is any of 0, 1 Indicates the status.
After the trailing bit ED3 of the change point bit string EDP, there is a channel monitor bit SVP to which the monitor data of the channel in that section is added, and as shown in FIG. 1 frame (5 bits) of the encoded pulse FP.

Here, based on the sampling result, 0011,1 011,0
.. Are encoded into encoded pulses FP, such as 010, 1 001..., And these data are multiplexed and transmitted through one communication line.

Then, on the receiving side, the transmitted encoded pulse
By encoding the FP, the transmitted information content is determined.

For example, in the example shown in FIG.
Is 0 011 (however, except for the channel monitoring bit SVP), and since the status bit SP which is the first bit is 0, the point is decoded to 0, and the subsequent 3-bit change point bit string EDP of 011 is Since it indicates the change point at E3, it is decrypted to 1 at the point. The coded bits of the subsequent second frame
Since the FP is 1 011 and the status bit SP is 1, the point is coded as 1, and the subsequent 3-bit change bit EDP is E
Since the change point at 3 is indicated, it is decrypted to 0 at the point.

As described above, in the signal encoding method of the above-described embodiment,
The input signal, which is the original signal, is sampled by a sampling pulse EP consisting of 6 bits each, and the change points in the input signal are extracted for each set. Therefore, compared to the conventional multipoint sampling method or fixed index method, Therefore, the distortion of the signal to be decoded is small, and the fidelity to the original signal can be sufficiently secured. Further, for example, even if a bit error occurs at a location indicated by a mark in FIG. 10G, the error can be reliably recovered by the status bit SP in the next frame, and the reliability of the transmitted signal increases. .

Next, FIG. 3 shows another embodiment of the signal encoding system according to the present invention.

The signal encoding method two pairs of transition points bit string EDP to the encoded pulse FP at every interval T ₂ Unlike scheme according to the embodiment described above, and a LDP.

When an input signal as an original signal is input as shown in FIG. 3 (c), one section T2 has 12 bits (E2 to E6, L1) based on a predetermined sampling frequency as shown in FIG. 3 (d). ... L6), sampling is performed for each sampling number. At this time, the sampling pulse EP is composed of two sets of data each consisting of 6 bits, and the position of the change point of the input signal is extracted based on each set of data.
Then, the position of the change point due to each data is represented by a change point bit string EDP, LDP which forms one group with 3 bits as shown in FIG.

In this embodiment, 001 (change point at E1, L1), 010 (E2, L2
, 011 (change point at E3, L3), 100 (change point at E4, L4), 101 (change point at E5, L5), 110 (change point at E6, L6), Seven kinds of change point bit strings EDP and LD of 111 (no change)
The three positions of the change points are represented by P.

Further, before the head bit ED1 in the above-mentioned first set of change point bit strings EDP, there is a 1-bit status bit SP, and this status bit SP is an initial position at the start of the section and the input signal is 0,1. The state is shown. After the tail bit LD3 of the second set of change point bit strings LDP, there is a channel monitor bit SVP to which the channel monitor data of that section is added. As shown in FIG. 4, the change point bit strings EDP, LDP, Status bit SP
Together with one frame (8 bits) of the encoded pulse FP.

Here, based on the sampling result, 0 011 011,0
010 001 ... is encoded into the encoded pulse FP,
These data are multiplexed and transmitted through one communication line.

Then, on the receiving side, the transmitted encoded pulse
By decoding the FP, the transmitted information content is determined.

For example, in the example shown in FIG.
Is 0 011 011 (however, excluding the channel monitoring bit SVP)
Since the status bit SP, which is the first bit, is 0, the point is decoded to 0, and the 3-bit change point bit sequence EDP of 011 indicates the change point at E3, so that the point is changed to 1 at the point. The 3-bit change bit LDP of 011 which is decoded and further indicates a change point at L3 is decoded to 0 at the point.

As described above, in the signal encoding method of the above-described embodiment,
The input signal which is the original signal is sampled by two sets of 6-bit sampling pulses, and each set is encoded to extract a change point in the input signal. Can be reliably extracted and transmitted even when the occurrence occurs. Also, compared to the conventional multi-point sampling method or fixed index method, distortion of the decoded signal is small, and sufficient fidelity to the original signal can be secured. Further, for example, even if a bit error occurs at a location indicated by a mark in FIG. 9G, the error can be reliably recovered by the status bit SP in the next frame, and the reliability of the transmitted signal increases. .

By the way, in the above-described embodiment, the case where the change point bit string EDP (LDP) in the coded pulse FP in one section is only one group and the case where the change point bit string is composed of two groups has been described. A group may be configured. In this case, although the detection accuracy for a bit error is reduced, even if two or more change points occur in the same section, the positions of the change points can be reliably extracted. Further, by reducing the total number of bits, the signal can be sufficiently compressed to suppress the distortion, and the total efficiency can be improved.

Next, an embodiment using a signal converter will be described with reference to the drawings.

FIG. 5 is a block diagram showing one embodiment of the signal conversion device according to the present invention.

The signal conversion device shown in FIG. 1 includes a transmission unit 1 that converts a low-speed asynchronous signal into a high-speed synchronous signal, and a receiving unit 2 that converts a high-speed synchronous signal into a low-speed asynchronous signal. .

The transmission unit 1 converts a plurality of low-speed asynchronous signals (input signals) into code data, and a plurality of signal conversion units. The transmission unit 1 takes in the code data output from each of the signal conversion units 3 and sends out the code data to a communication line. A communication signal generation unit 4;

Each of the signal converters 3 has a “decimal” counter 5 that increments a count result each time a clock signal is supplied, and receives an input signal each time the clock signal is supplied, and a value that was previously captured. A change point detection circuit 6 for generating a change detection signal when the input signal is different from the input signal based on the output of the change point detection circuit 6, the output of the counter 1 and the input signal. And a data generation circuit 7 for performing a process of generating corresponding 4-bit code data and a process of generating an initial data fetch signal each time two values “0” are supplied from the counter 5.

Each of the signal converters 3 receives an input signal each time an initial data capture signal is supplied from the data generation circuit 7 and outputs the input signal.
And a data compression circuit 9 which takes in 4-bit code data output from the data generation circuit 7 and bit-compresses the 2-bit code data to generate 7-bit code data. And a data combination circuit 10 for combining the compressed 7-bit code data and the 1-bit initial state display data output from the initial state detection circuit 8 to create 8-bit code data.

In this case, when the change detection signal is supplied from the change point detection circuit 6 before the value “9” is supplied from the counter 1, the data generation unit 7 determines the counter value supplied from the counter 5 at this time. At the same time, code data corresponding to this value is generated based on the code table shown in FIG. 6 and supplied to the data compression circuit 9. When the value “9” is supplied from the counter 5,
When the change detection signal is not supplied from the change point detection circuit 6, the data generator 3 generates code data “0000” indicating no change based on the code table,
This is supplied to the data compression circuit 9.

When two pieces of 4-bit code data are supplied from the data generation circuit 7, the data compression circuit 9 performs git compression on the two pieces of code data in the following procedure to create 7-bit code data. It is supplied to the combinational circuit 10.

Now, assuming that the value of the first code data supplied from the data generation circuit 7 is A, and the value of the second code data is B, the data compression circuit 9 calculates The code data A and B are compressed to obtain 7-bit code data C, which is supplied to the data combination circuit 10.

Therefore, for example, when an input signal as shown in FIG. 7A is supplied and the code data “0011” and “1000” shown in FIG. 7B are output from the data generation circuit 7,
The data compression circuit 9 performs bit processing to create 7-bit code data “1011011”, and supplies this to the data combination circuit 10.

Then, as shown in FIG. 7 (d), the 1-bit initial state display data output from the initial state detection circuit 8 is the 0th bit by the data combination circuit 10, and the 7th bit is output from the data compression circuit 9 as shown in FIG. 8-bit code data in which bit code data is arranged in the first to seventh bits is generated and supplied to the communication signal generation unit 4.

The communication signal generator 4 first resets the signal converters 3 sequentially. Thereafter, the signal conversion units 3 to 8
Each time bit code data is supplied, these are sequentially taken in to generate communication data, which is transmitted on a communication line.

On the other hand, the receiving unit 2 receives a high-speed synchronization signal supplied via a communication line and converts it into code data.
And a plurality of signal converters 21 for converting each code data output from the CDMA into a low-speed asynchronous signal (output signal).

Each signal converter 21 converts the 8-bit code data output from the code data reproducer 20 into the 0th bit and the 1st bit.
A data separation circuit 22 for separating the data into a 7th bit and a 0th bit data which is separated by the data separation circuit 22; a reset signal is generated when this data is a value "0"; When the value is "1", the initial state setting circuit 23 for generating a set signal, the data from the first bit to the seventh bit separated by the data separation circuit 22 are fetched, and the operation shown in the equation (1) is performed. A data decompression circuit 24 is provided to generate two 4-bit code data by performing the reverse operation and sequentially output these.

Each of these signal converters 21 is provided with a data decompression circuit 24.
, A latch circuit 25 for latching 4-bit code data output sequentially, a “decimal” counter 26 for incrementing a count result each time a clock signal is supplied,
A comparison circuit 27 for generating a pulse signal when the count result output from the counter 26 matches the value of the code data latched in the latch circuit 25, and a reset signal from the initial state setting circuit 23 When supplied, the value of the output signal is set to "0". When the set signal is supplied, the value of the output signal is set to "1". And a toggle flip-flop 28 for inverting the value.

When a high-speed synchronous signal is supplied via the communication line, 8-bit code data is extracted from this signal, and data from the first bit to 7 bits of the code data is expanded to 4 bits. Two bits of code data are generated.

In parallel with this operation, the toggle flip-flop 28 is set or reset based on the 0-bit data constituting the 8-bit code data. At the obtained timing, the toggle flip-flop 28 is inverted to generate an output signal, which is supplied to a corresponding low-speed asynchronous device.

As described above, in this embodiment, when quantizing a low-speed asynchronous signal, the initial state is detected and transmitted by including the output signal. An error can be prevented from being transmitted to the code data.

Further, in this case, the 4-bit code data obtained by quantizing the quick asynchronous signal is compressed into 7-bit code data as a set of two, and an output signal is created. Is expanded, the 4-bit code data before compression can be reproduced in units of two, thereby obtaining the same resolution as when two 4-bit code data are provided, and reducing the conversion distortion. Can be minimized.

Further, in the above-described embodiment, “unchanged” to “9”
There are 121 combinations (121 = 11 11) of expressing the two codes up to two codes, and paying attention to the fact that the combination “121” can be expressed by 7 bits, the 4-bit code data is represented by 2 bits. Although the data is compressed into 7-bit code data in units of individual units, an expression other than the expression (1) may be used as an expression used in this case.

In the above-described embodiment, the low-speed asynchronous signal is set to T
The present invention has been described by taking as an example the case where data is converted into 4-bit data divided every second and this is compressed into 7-bit data in units of two. However, another numerical value is used as the quantization number at this time. You may do it.

In this case, at the time of encoding every T seconds, the input signal change point position and no change point are associated with 0 to 2 ^N- n (decimal notation), and correspond to the first half T seconds and the second half T seconds. the combination of the N bits in correspondence with ^{0~ (2 N -n + 1)} 2 -1 (10 decimal representation), which was encoded with N-1 bits, the remaining 1
The logic level "1" or "0" for the first half T seconds may be incorporated in the bit. Here, n and N are integers satisfying the following conditions.

_{^{2 N -2 (2N-1)}} / 2 + 1 <n <2 N-1 -1 ...
(2) [Effects of the Invention] As described above, according to the first invention of the signal encoding method according to the present invention, the input signal is regarded as a change point, and the input signal in the section is provided at the head of the encoded pulse. , The distortion of the combined signal is smaller than that of the conventional multipoint sampling method, and the fidelity to the original signal can be sufficiently ensured. Also,
Even if a bit error occurs in the code ratio signal, it is possible to reliably return to the original correct state in a short time by the next state bit.

Further, according to the second aspect, similarly to the scheme according to the first aspect described above, the distortion of the decoded signal is smaller than that of the conventional multipoint sampling scheme, and the fidelity to the original signal can be sufficiently ensured. . Also, since a plurality of change point bit strings are provided in the coded pulse in one section, the signal can be sufficiently compressed at the time of coding, and a plurality of change points occur in the original signal within the same sampling period. Can be reliably extracted and processed.

According to the third and fourth aspects of the present invention, even if a transmission error or the like occurs or the transmission error occurs, the transmission can be performed while minimizing the conversion distortion by preventing a decrease in the resolution. The error can be prevented from being transmitted to the code data other than the part where the error has occurred.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a signal encoding method according to the present invention, and is a diagram showing a signal waveform at each processing, and FIG.
FIG. 3 is a diagram showing a frame configuration and operation of an encoding pulse in the system of FIG. 1, and FIG. 3 is a diagram showing another embodiment of the signal encoding system according to the present invention. FIG. 4 is a diagram showing the frame configuration and operation principle of the coded pulse in the system of FIG. 3, and FIG.
FIG. 6 is a block diagram showing an embodiment of a signal conversion apparatus according to the present invention, FIG. 6 is a diagram showing an example of a code table used in the embodiment, and FIG. 7 is a diagram for explaining an operation example of the embodiment. FIG. 8 is a diagram showing signal waveforms at the time of each processing of a multipoint sampling system which is a conventional signal encoding system, and FIG.
Figure is a diagram showing the operation principle of the fixed index coding pulse is a conventional signal encoding system, FIG. 10 is a diagram showing a signal waveform at each processing of the fixed index system is a conventional signal encoding system, FIG. 11 is a block diagram showing an example of a conventional signal converter, FIG. 12 is a diagram showing an example of a code table used in the signal converter shown in FIG.
FIG. 13 is a diagram showing an example of a code table used in the signal conversion device shown in FIG. 11, and FIGS. 14 (a) to (c) are diagrams for explaining an operation example of the signal conversion device shown in FIG. It is a schematic diagram. 1 ... transmitting unit, 2 ... receiving unit, 3, 21 ... signal converting unit,
6 ... change point position detection section (change point detection circuit), 8 ... polarity determination section (initial state detection circuit), 9 ... signal compression section (data compression circuit), 10 ... output signal generation section (data combination) Circuit), 23 ... Polarity determining unit (initial state setting circuit), 24
………………………………………………………………………………………………………………………………………………………… ……………………… …………

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hiroshi Itoki 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Fumio Abe 5- 10-27 Minamiazabu, Minato-ku, Tokyo Inside Anritsu Corporation (72) Inventor Masao Fukuda 5-10-27 Minamiazabu, Minato-ku, Tokyo Anritsu Corporation (72) Inventor Hiromichi Ohara 5-10-27 Minamiazabu, Minato-ku, Tokyo Anritsu Corporation (72) Inventor Tamio Amuro 2-1-1 Kotani, Samukawa-cho, Takaza-gun, Kanagawa Prefecture Toyo Communication Equipment Co., Ltd. (72) Inventor Tomozo Teraoka 2-1-1 Kotani, Samukawa-cho, Koza-gun, Kanagawa Prefecture Toyo Tsushinki Co., Ltd. (72) Inventor Yoshio Enomoto 2-1-1 Kotani, Samukawa-cho, Koza-gun, Kanagawa Prefecture Toyo Tsushinki Co., Ltd. (56) References JP-A-55-150111 (JP, A) JP-A-52-28214 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 25/08 H03M 5/12

Claims (4)

(57) [Claims] 1. A signal coding method for sampling an input signal indicating various information data and performing coding processing for each predetermined section (T ₁ ), wherein a level state at an initial position in each section (T ₁ ) is indicated. A state bit (SP) and a change point bit string (EDP) indicating a change point at a predetermined position corresponding to the input signal in each section, and forming a group by a plurality of bits
A signal encoding method for encoding the input signal based on an encoding pulse (FP) composed of a combination of the following. 2. A signal encoding method for sampling an input signal indicating various information data and performing encoding processing for each predetermined section (T ₂ ), wherein a level state at an initial position in each section (T ₂ ) is indicated. A state bit (SP) and a change point at a predetermined position corresponding to the input signal within the section, and a change point bit string (EDP, LD) forming a group by a plurality of bits
A signal encoding method, wherein the input signal is encoded based on an encoding pulse (FP) composed of a combination of a plurality of groups P). 3. A change point position detection unit for detecting a signal change point position of a preceding period and a subsequent period by time-sharing an input signal, a signal compression unit for bit-compressing the detection result of the change point position detection unit, A polarity determination unit that determines the polarity of the input signal at the beginning of the previous cycle, and an output signal generation unit that generates an output signal in combination with the determination result of the polarity determination unit and the compression result of the signal compression unit. A signal conversion device characterized by the above-mentioned. 4. A polarity determining unit for determining the polarity of an output signal based on a polarity bit of the input signal when an input signal is input, and reproducing an original signal by expanding a compressed partial bit of the input signal. A signal conversion device comprising: a signal decompression unit; and a signal reproduction unit that reproduces a signal indicated by the input signal based on a decompression result of the signal decompression unit and an output of the polarity determination unit.